arch: Move interrupt numbers to CMSIS configuration

Because we compile with `-fshort-enums`, the current CMSIS IRQ
enumeration, which only holds the exception numbers, is reduced in width
to a single 8-bit value. This means that any attempt to convert from a
large interrupt number to an IRQn_Type, which CMSIS does in the next
patch, is not safe.

We fix this by moving the interrupt numbers to the IRQn_Type, so that we
can use the CMSIS APIs to manage these interrupts.

Change-Id: Ic2644b5b97fb6dab412d50b8168597c056727295
Signed-off-by: Chris Kay <chris.kay@arm.com>

8 files changed, 182 insertions, 191 deletions

diff --git a/product/sgm775/include/fmw_cmsis.h b/product/sgm775/include/fmw_cmsis.h
index ece8426c..452b3a31 100644
--- a/product/sgm775/include/fmw_cmsis.h
+++ b/product/sgm775/include/fmw_cmsis.h
@@ -15,14 +15,177 @@
 #define __Vendor_SysTickConfig 0
 
 typedef enum IRQn {
-    NonMaskableInt_IRQn   = -14,
+    Reset_IRQn = -15,
+    NonMaskableInt_IRQn = -14,
+    HardFault_IRQn = -13,
     MemoryManagement_IRQn = -12,
-    BusFault_IRQn         = -11,
-    UsageFault_IRQn       = -10,
-    SVCall_IRQn           = -5,
-    DebugMonitor_IRQn     = -4,
-    PendSV_IRQn           = -2,
-    SysTick_IRQn          = -1,
+    BusFault_IRQn = -11,
+    UsageFault_IRQn = -10,
+    SVCall_IRQn = -5,
+    DebugMonitor_IRQn = -4,
+    PendSV_IRQn = -2,
+    SysTick_IRQn = -1,
+
+    TIM32KHZ_IRQ = 0, /* 32KHz Physical Timer */
+    CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */
+    CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */
+    CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */
+    GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */
+    RESERVED5_IRQ = 5, /* Reserved */
+    RESERVED6_IRQ = 6, /* Reserved */
+    RESERVED7_IRQ = 7, /* Reserved */
+    RESERVED8_IRQ = 8, /* Reserved */
+    RESERVED9_IRQ = 9, /* Reserved */
+    RESERVED10_IRQ = 10, /* Reserved */
+    RESERVED11_IRQ = 11, /* Reserved */
+    RESERVED12_IRQ = 12, /* Reserved */
+    RESERVED13_IRQ = 13, /* Reserved */
+    RESERVED14_IRQ = 14, /* Reserved */
+    RESERVED15_IRQ = 15, /* Reserved */
+    SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */
+    SOC_WAKEUP1_IRQ = 17, /* SoC Expansion Wakeup */
+    SOC_WAKEUP2_IRQ = 18, /* SoC Expansion Wakeup */
+    SOC_WAKEUP3_IRQ = 19, /* SoC Expansion Wakeup */
+    SOC_WAKEUP4_IRQ = 20, /* SoC Expansion Wakeup */
+    SOC_WAKEUP5_IRQ = 21, /* SoC Expansion Wakeup */
+    SOC_WAKEUP6_IRQ = 22, /* SoC Expansion Wakeup */
+    SOC_WAKEUP7_IRQ = 23, /* SoC Expansion Wakeup */
+    SOC_WAKEUP8_IRQ = 24, /* SoC Expansion Wakeup */
+    SOC_WAKEUP9_IRQ = 25, /* SoC Expansion Wakeup */
+    SOC_WAKEUP10_IRQ = 26, /* SoC Expansion Wakeup */
+    SOC_WAKEUP11_IRQ = 27, /* SoC Expansion Wakeup */
+    SOC_WAKEUP12_IRQ = 28, /* SoC Expansion Wakeup */
+    SOC_WAKEUP13_IRQ = 29, /* SoC Expansion Wakeup */
+    SOC_WAKEUP14_IRQ = 30, /* SoC Expansion Wakeup */
+    SOC_WAKEUP15_IRQ = 31, /* SoC Expansion Wakeup */
+    PPU_SCP_IRQ = 32, /* SCP Power Policy Unit */
+    TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */
+    MHU_HIGH_PRIO_IRQ = 34, /* MHU High Priority */
+    MHU_LOW_PRIO_IRQ = 35, /* MHU Low Priority */
+    MHU_SECURE_IRQ = 36, /* MHU Secure */
+    CTI_TRIGGER0_IRQ = 37, /* SCP CTI Trigger */
+    CTI_TRIGGER1_IRQ = 38, /* SCP CTI Trigger */
+    GIC_ERROR_ECC_IRQ = 39, /* GIC Error (ECC Fatal) */
+    GIC_ERROR_AXIM_IRQ = 40, /* GIC Error (AXIM) */
+    DMC_RESERVED0_IRQ = 41, /* DMC, Reserved */
+    DMC_0_ERROR_ECC_IRQ = 42, /* DMC0 Combined ECC Error */
+    DMC_0_ERROR_ACCESS_IRQ = 43, /* DMC0 Combined Misc Access Error */
+    DMC_RESERVED1_IRQ = 44, /* DMC, Reserved */
+    DMC_RESERVED2_IRQ = 45, /* DMC, Reserved */
+    DMC_1_ERROR_ECC_IRQ = 46, /* DMC1 Combined ECC Error */
+    DMC_1_ERROR_ACCESS_IRQ = 47, /* DMC1 Combined Misc Access Error */
+    DMC_RESERVED3_IRQ = 48, /* DMC, Reserved */
+    DMC_RESERVED4_IRQ = 49, /* DMC, Reserved */
+    DMC_2_ERROR_ECC_IRQ = 50, /* DMC2 Combined ECC Error */
+    DMC_2_ERROR_ACCESS_IRQ = 51, /* DMC2 Combined Misc Access Error */
+    DMC_RESERVED5_IRQ = 52, /* DMC, Reserved */
+    DMC_RESERVED6_IRQ = 53, /* DMC, Reserved */
+    DMC_3_ERROR_ECC_IRQ = 54, /* DMC3 Combined ECC Error */
+    DMC_3_ERROR_ACCESS_IRQ = 55, /* DMC3 Combined Misc Access Error */
+    DMC_RESERVED7_IRQ = 56, /* DMC, Reserved */
+    RESERVED57_IRQ = 57, /* Reserved */
+    RESERVED58_IRQ = 58, /* Reserved */
+    RESERVED59_IRQ = 59, /* Reserved */
+    RESERVED60_IRQ = 60, /* Reserved */
+    RESERVED61_IRQ = 61, /* Reserved */
+    RESERVED62_IRQ = 62, /* Reserved */
+    RESERVED63_IRQ = 63, /* Reserved */
+    PPU_CLUS0CORE0_IRQ = 64, /* Cluster 0 Core 0 Power Policy Unit */
+    PPU_CLUS0CORE1_IRQ = 65, /* Cluster 0 Core 1 Power Policy Unit */
+    PPU_CLUS0CORE2_IRQ = 66, /* Cluster 0 Core 2 Power Policy Unit */
+    PPU_CLUS0CORE3_IRQ = 67, /* Cluster 0 Core 3 Power Policy Unit */
+    PPU_CLUS0_IRQ = 68, /* Cluster 0 Power Policy Unit */
+    PPU_CLUS1CORE0_IRQ = 69, /* Cluster 1 Core 0 Power Policy Unit */
+    PPU_CLUS1CORE1_IRQ = 70, /* Cluster 1 Core 1 Power Policy Unit */
+    PPU_CLUS1CORE2_IRQ = 71, /* Cluster 1 Core 2 Power Policy Unit */
+    PPU_CLUS1CORE3_IRQ = 72, /* Cluster 1 Core 3 Power Policy Unit */
+    PPU_CLUS1_IRQ = 73, /* Cluster 1 Power Policy Unit */
+    PPU_SYS0_IRQ = 74, /* System Power Policy Unit 0 */
+    PPU_SYS1_IRQ = 75, /* System Power Policy Unit 1 */
+    PPU_GPU_IRQ = 76, /* GPU Power Policy Unit */
+    PPU_VPU_IRQ = 77, /* Video Power Policy Unit */
+    RESERVED78_IRQ = 78, /* Reserved */
+    PPU_DPU0_IRQ = 79, /* Display Power Policy Unit 0 */
+    PPU_DPU1_IRQ = 80, /* Display Power Policy Unit 1 */
+    PPU_DEBUG_IRQ = 81, /* DBGSYS Power Policy Unit */
+    RESERVED82_IRQ = 82, /* Reserved */
+    RESERVED83_IRQ = 83, /* Reserved */
+    RESERVED84_IRQ = 84, /* Reserved */
+    RESERVED85_IRQ = 85, /* Reserved */
+    RESERVED86_IRQ = 86, /* Reserved */
+    RESERVED87_IRQ = 87, /* Reserved */
+    RESERVED88_IRQ = 88, /* Reserved */
+    RESERVED89_IRQ = 89, /* Reserved */
+    PPU_CLUS0CORE4_IRQ = 90, /* Cluster 0 Core 4 Power Policy Unit */
+    PPU_CLUS0CORE5_IRQ = 91, /* Cluster 0 Core 5 Power Policy Unit */
+    PPU_CLUS0CORE6_IRQ = 92, /* Cluster 0 Core 6 Power Policy Unit */
+    PPU_CLUS0CORE7_IRQ = 93, /* Cluster 0 Core 7 Power Policy Unit */
+    PPU_CLUS1CORE4_IRQ = 94, /* Cluster 1 Core 4 Power Policy Unit */
+    PPU_CLUS1CORE5_IRQ = 95, /* Cluster 1 Core 5 Power Policy Unit */
+    PPU_CLUS1CORE6_IRQ = 96, /* Cluster 1 Core 6 Power Policy Unit */
+    PPU_CLUS1CORE7_IRQ = 97, /* Cluster 1 Core 7 Power Policy Unit */
+    PLL_CLUS0_LOCK_IRQ = 98, /* Cluster 0 CPU PLL Lock */
+    PLL_CLUS1_LOCK_IRQ = 99, /* Cluster 1 CPU PLL Lock */
+    PLL_GPU_LOCK_IRQ = 100, /* GPU PLL Lock */
+    PLL_VPU_LOCK_IRQ = 101, /* Video PLL Lock */
+    PLL_SYS_LOCK_IRQ = 102, /* System PLL Lock */
+    PLL_DPU_LOCK_IRQ = 103, /* Display PLL Lock */
+    PLL_CLUS0CORE0_IRQ = 104, /* Cluster 0 PLL0 Lock */
+    PLL_CLUS0CORE1_IRQ = 105, /* Cluster 0 PLL1 Lock */
+    PLL_CLUS0CORE2_IRQ = 106, /* Cluster 0 PLL2 Lock */
+    PLL_CLUS0CORE3_IRQ = 107, /* Cluster 0 PLL3 Lock */
+    PLL_CLUS0CORE4_IRQ = 108, /* Cluster 0 PLL4 Lock */
+    PLL_CLUS0CORE5_IRQ = 109, /* Cluster 0 PLL5 Lock */
+    PLL_CLUS0CORE6_IRQ = 110, /* Cluster 0 PLL6 Lock */
+    PLL_CLUS0CORE7_IRQ = 111, /* Cluster 0 PLL7 Lock */
+    PLL_CLUS1CORE0_IRQ = 112, /* Cluster 1 PLL0 Lock */
+    PLL_CLUS1CORE1_IRQ = 113, /* Cluster 1 PLL1 Lock */
+    PLL_CLUS1CORE2_IRQ = 114, /* Cluster 1 PLL2 Lock */
+    PLL_CLUS1CORE3_IRQ = 115, /* Cluster 1 PLL3 Lock */
+    PLL_CLUS1CORE4_IRQ = 116, /* Cluster 1 PLL4 Lock */
+    PLL_CLUS1CORE5_IRQ = 117, /* Cluster 1 PLL5 Lock */
+    PLL_CLUS1CORE6_IRQ = 118, /* Cluster 1 PLL6 Lock */
+    PLL_CLUS1CORE7_IRQ = 119, /* Cluster 1 PLL7 Lock */
+    RESERVED120_IRQ = 120, /* Reserved */
+    RESERVED121_IRQ = 121, /* Reserved */
+    RESERVED122_IRQ = 122, /* Reserved */
+    RESERVED123_IRQ = 123, /* Reserved */
+    RESERVED124_IRQ = 124, /* Reserved */
+    RESERVED125_IRQ = 125, /* Reserved */
+    RESERVED126_IRQ = 126, /* Reserved */
+    RESERVED127_IRQ = 127, /* Reserved */
+    SCP_EXT_INTR0_IRQ = 128, /* SCP Customer Extension */
+    SCP_EXT_INTR1_IRQ = 129, /* SCP Customer Extension */
+    SCP_EXT_INTR2_IRQ = 130, /* SCP Customer Extension */
+    SCP_EXT_INTR3_IRQ = 131, /* SCP Customer Extension */
+    SCP_EXT_INTR4_IRQ = 132, /* SCP Customer Extension */
+    SCP_EXT_INTR5_IRQ = 133, /* SCP Customer Extension */
+    SCP_EXT_INTR6_IRQ = 134, /* SCP Customer Extension */
+    SCP_EXT_INTR7_IRQ = 135, /* SCP Customer Extension */
+    SCP_EXT_INTR8_IRQ = 136, /* SCP Customer Extension */
+    SCP_EXT_INTR9_IRQ = 137, /* SCP Customer Extension */
+    SCP_EXT_INTR10_IRQ = 138, /* SCP Customer Extension */
+    SCP_EXT_INTR11_IRQ = 139, /* SCP Customer Extension */
+    SCP_EXT_INTR12_IRQ = 140, /* SCP Customer Extension */
+    SCP_EXT_INTR13_IRQ = 141, /* SCP Customer Extension */
+    SCP_EXT_INTR14_IRQ = 142, /* SCP Customer Extension */
+    SCP_EXT_INTR15_IRQ = 143, /* SCP Customer Extension */
+    SCP_EXT_INTR16_IRQ = 144, /* SCP Customer Extension */
+    SCP_EXT_INTR17_IRQ = 145, /* SCP Customer Extension */
+    SCP_EXT_INTR18_IRQ = 146, /* SCP Customer Extension */
+    SCP_EXT_INTR19_IRQ = 147, /* SCP Customer Extension */
+    SCP_EXT_INTR20_IRQ = 148, /* SCP Customer Extension */
+    SCP_EXT_INTR21_IRQ = 149, /* SCP Customer Extension */
+    SCP_EXT_INTR22_IRQ = 150, /* SCP Customer Extension */
+    SCP_EXT_INTR23_IRQ = 151, /* SCP Customer Extension */
+    SCP_EXT_INTR24_IRQ = 152, /* SCP Customer Extension */
+    SCP_EXT_INTR25_IRQ = 153, /* SCP Customer Extension */
+    SCP_EXT_INTR26_IRQ = 154, /* SCP Customer Extension */
+    SCP_EXT_INTR27_IRQ = 155, /* SCP Customer Extension */
+    SCP_EXT_INTR28_IRQ = 156, /* SCP Customer Extension */
+    SCP_EXT_INTR29_IRQ = 157, /* SCP Customer Extension */
+    SCP_EXT_INTR30_IRQ = 158, /* SCP Customer Extension */
+    SCP_EXT_INTR31_IRQ = 159, /* SCP Customer Extension */
 } IRQn_Type;
 
 #include <core_cm3.h>
diff --git a/product/sgm775/include/sgm775_irq.h b/product/sgm775/include/sgm775_irq.h
deleted file mode 100644
index 4a33cbf5..00000000
--- a/product/sgm775/include/sgm775_irq.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Arm SCP/MCP Software
- * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SGM775_IRQ_H
-#define SGM775_IRQ_H
-
-#include <fwk_interrupt.h>
-
-#define WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */
-
-enum sgm775_irq {
-    TIM32KHZ_IRQ               = 0, /* 32KHz Physical Timer */
-    CDBG_PWR_UP_REQ_IRQ        = 1, /* Coresight Debug Power Request */
-    CSYS_PWR_UP_REQ_IRQ        = 2, /* Coresight System Power Request */
-    CDBG_RST_REQ_IRQ           = 3, /* Coresight Debug Reset Request */
-    GIC_EXT_WAKEUP_IRQ         = 4, /* External GIC Wakeup Request */
-    RESERVED5_IRQ              = 5, /* Reserved */
-    RESERVED6_IRQ              = 6, /* Reserved */
-    RESERVED7_IRQ              = 7, /* Reserved */
-    RESERVED8_IRQ              = 8, /* Reserved */
-    RESERVED9_IRQ              = 9, /* Reserved */
-    RESERVED10_IRQ             = 10, /* Reserved */
-    RESERVED11_IRQ             = 11, /* Reserved */
-    RESERVED12_IRQ             = 12, /* Reserved */
-    RESERVED13_IRQ             = 13, /* Reserved */
-    RESERVED14_IRQ             = 14, /* Reserved */
-    RESERVED15_IRQ             = 15, /* Reserved */
-    SOC_WAKEUP0_IRQ            = 16, /* SoC Expansion Wakeup */
-    SOC_WAKEUP1_IRQ            = 17, /* SoC Expansion Wakeup */
-    SOC_WAKEUP2_IRQ            = 18, /* SoC Expansion Wakeup */
-    SOC_WAKEUP3_IRQ            = 19, /* SoC Expansion Wakeup */
-    SOC_WAKEUP4_IRQ            = 20, /* SoC Expansion Wakeup */
-    SOC_WAKEUP5_IRQ            = 21, /* SoC Expansion Wakeup */
-    SOC_WAKEUP6_IRQ            = 22, /* SoC Expansion Wakeup */
-    SOC_WAKEUP7_IRQ            = 23, /* SoC Expansion Wakeup */
-    SOC_WAKEUP8_IRQ            = 24, /* SoC Expansion Wakeup */
-    SOC_WAKEUP9_IRQ            = 25, /* SoC Expansion Wakeup */
-    SOC_WAKEUP10_IRQ           = 26, /* SoC Expansion Wakeup */
-    SOC_WAKEUP11_IRQ           = 27, /* SoC Expansion Wakeup */
-    SOC_WAKEUP12_IRQ           = 28, /* SoC Expansion Wakeup */
-    SOC_WAKEUP13_IRQ           = 29, /* SoC Expansion Wakeup */
-    SOC_WAKEUP14_IRQ           = 30, /* SoC Expansion Wakeup */
-    SOC_WAKEUP15_IRQ           = 31, /* SoC Expansion Wakeup */
-    PPU_SCP_IRQ                = 32, /* SCP Power Policy Unit */
-    TIMREFCLK_IRQ              = 33, /* REFCLK Physical Timer */
-    MHU_HIGH_PRIO_IRQ          = 34, /* MHU High Priority */
-    MHU_LOW_PRIO_IRQ           = 35, /* MHU Low Priority */
-    MHU_SECURE_IRQ             = 36, /* MHU Secure */
-    CTI_TRIGGER0_IRQ           = 37, /* SCP CTI Trigger */
-    CTI_TRIGGER1_IRQ           = 38, /* SCP CTI Trigger */
-    GIC_ERROR_ECC_IRQ          = 39, /* GIC Error (ECC Fatal) */
-    GIC_ERROR_AXIM_IRQ         = 40, /* GIC Error (AXIM) */
-    DMC_RESERVED0_IRQ          = 41, /* DMC, Reserved */
-    DMC_0_ERROR_ECC_IRQ        = 42, /* DMC0 Combined ECC Error */
-    DMC_0_ERROR_ACCESS_IRQ     = 43, /* DMC0 Combined Misc Access Error */
-    DMC_RESERVED1_IRQ          = 44, /* DMC, Reserved */
-    DMC_RESERVED2_IRQ          = 45, /* DMC, Reserved */
-    DMC_1_ERROR_ECC_IRQ        = 46, /* DMC1 Combined ECC Error */
-    DMC_1_ERROR_ACCESS_IRQ     = 47, /* DMC1 Combined Misc Access Error */
-    DMC_RESERVED3_IRQ          = 48, /* DMC, Reserved */
-    DMC_RESERVED4_IRQ          = 49, /* DMC, Reserved */
-    DMC_2_ERROR_ECC_IRQ        = 50, /* DMC2 Combined ECC Error */
-    DMC_2_ERROR_ACCESS_IRQ     = 51, /* DMC2 Combined Misc Access Error */
-    DMC_RESERVED5_IRQ          = 52, /* DMC, Reserved */
-    DMC_RESERVED6_IRQ          = 53, /* DMC, Reserved */
-    DMC_3_ERROR_ECC_IRQ        = 54, /* DMC3 Combined ECC Error */
-    DMC_3_ERROR_ACCESS_IRQ     = 55, /* DMC3 Combined Misc Access Error */
-    DMC_RESERVED7_IRQ          = 56, /* DMC, Reserved */
-    RESERVED57_IRQ             = 57, /* Reserved */
-    RESERVED58_IRQ             = 58, /* Reserved */
-    RESERVED59_IRQ             = 59, /* Reserved */
-    RESERVED60_IRQ             = 60, /* Reserved */
-    RESERVED61_IRQ             = 61, /* Reserved */
-    RESERVED62_IRQ             = 62, /* Reserved */
-    RESERVED63_IRQ             = 63, /* Reserved */
-    PPU_CLUS0CORE0_IRQ         = 64, /* Cluster 0 Core 0 Power Policy Unit */
-    PPU_CLUS0CORE1_IRQ         = 65, /* Cluster 0 Core 1 Power Policy Unit */
-    PPU_CLUS0CORE2_IRQ         = 66, /* Cluster 0 Core 2 Power Policy Unit */
-    PPU_CLUS0CORE3_IRQ         = 67, /* Cluster 0 Core 3 Power Policy Unit */
-    PPU_CLUS0_IRQ              = 68, /* Cluster 0 Power Policy Unit */
-    PPU_CLUS1CORE0_IRQ         = 69, /* Cluster 1 Core 0 Power Policy Unit */
-    PPU_CLUS1CORE1_IRQ         = 70, /* Cluster 1 Core 1 Power Policy Unit */
-    PPU_CLUS1CORE2_IRQ         = 71, /* Cluster 1 Core 2 Power Policy Unit */
-    PPU_CLUS1CORE3_IRQ         = 72, /* Cluster 1 Core 3 Power Policy Unit */
-    PPU_CLUS1_IRQ              = 73, /* Cluster 1 Power Policy Unit */
-    PPU_SYS0_IRQ               = 74, /* System Power Policy Unit 0 */
-    PPU_SYS1_IRQ               = 75, /* System Power Policy Unit 1 */
-    PPU_GPU_IRQ                = 76, /* GPU Power Policy Unit */
-    PPU_VPU_IRQ                = 77, /* Video Power Policy Unit */
-    RESERVED78_IRQ             = 78, /* Reserved */
-    PPU_DPU0_IRQ               = 79, /* Display Power Policy Unit 0 */
-    PPU_DPU1_IRQ               = 80, /* Display Power Policy Unit 1 */
-    PPU_DEBUG_IRQ              = 81, /* DBGSYS Power Policy Unit */
-    RESERVED82_IRQ             = 82, /* Reserved */
-    RESERVED83_IRQ             = 83, /* Reserved */
-    RESERVED84_IRQ             = 84, /* Reserved */
-    RESERVED85_IRQ             = 85, /* Reserved */
-    RESERVED86_IRQ             = 86, /* Reserved */
-    RESERVED87_IRQ             = 87, /* Reserved */
-    RESERVED88_IRQ             = 88, /* Reserved */
-    RESERVED89_IRQ             = 89, /* Reserved */
-    PPU_CLUS0CORE4_IRQ         = 90, /* Cluster 0 Core 4 Power Policy Unit */
-    PPU_CLUS0CORE5_IRQ         = 91, /* Cluster 0 Core 5 Power Policy Unit */
-    PPU_CLUS0CORE6_IRQ         = 92, /* Cluster 0 Core 6 Power Policy Unit */
-    PPU_CLUS0CORE7_IRQ         = 93, /* Cluster 0 Core 7 Power Policy Unit */
-    PPU_CLUS1CORE4_IRQ         = 94, /* Cluster 1 Core 4 Power Policy Unit */
-    PPU_CLUS1CORE5_IRQ         = 95, /* Cluster 1 Core 5 Power Policy Unit */
-    PPU_CLUS1CORE6_IRQ         = 96, /* Cluster 1 Core 6 Power Policy Unit */
-    PPU_CLUS1CORE7_IRQ         = 97, /* Cluster 1 Core 7 Power Policy Unit */
-    PLL_CLUS0_LOCK_IRQ         = 98, /* Cluster 0 CPU PLL Lock */
-    PLL_CLUS1_LOCK_IRQ         = 99, /* Cluster 1 CPU PLL Lock */
-    PLL_GPU_LOCK_IRQ           = 100, /* GPU PLL Lock */
-    PLL_VPU_LOCK_IRQ           = 101, /* Video PLL Lock */
-    PLL_SYS_LOCK_IRQ           = 102, /* System PLL Lock */
-    PLL_DPU_LOCK_IRQ           = 103, /* Display PLL Lock */
-    PLL_CLUS0CORE0_IRQ         = 104, /* Cluster 0 PLL0 Lock */
-    PLL_CLUS0CORE1_IRQ         = 105, /* Cluster 0 PLL1 Lock */
-    PLL_CLUS0CORE2_IRQ         = 106, /* Cluster 0 PLL2 Lock */
-    PLL_CLUS0CORE3_IRQ         = 107, /* Cluster 0 PLL3 Lock */
-    PLL_CLUS0CORE4_IRQ         = 108, /* Cluster 0 PLL4 Lock */
-    PLL_CLUS0CORE5_IRQ         = 109, /* Cluster 0 PLL5 Lock */
-    PLL_CLUS0CORE6_IRQ         = 110, /* Cluster 0 PLL6 Lock */
-    PLL_CLUS0CORE7_IRQ         = 111, /* Cluster 0 PLL7 Lock */
-    PLL_CLUS1CORE0_IRQ         = 112, /* Cluster 1 PLL0 Lock */
-    PLL_CLUS1CORE1_IRQ         = 113, /* Cluster 1 PLL1 Lock */
-    PLL_CLUS1CORE2_IRQ         = 114, /* Cluster 1 PLL2 Lock */
-    PLL_CLUS1CORE3_IRQ         = 115, /* Cluster 1 PLL3 Lock */
-    PLL_CLUS1CORE4_IRQ         = 116, /* Cluster 1 PLL4 Lock */
-    PLL_CLUS1CORE5_IRQ         = 117, /* Cluster 1 PLL5 Lock */
-    PLL_CLUS1CORE6_IRQ         = 118, /* Cluster 1 PLL6 Lock */
-    PLL_CLUS1CORE7_IRQ         = 119, /* Cluster 1 PLL7 Lock */
-    RESERVED120_IRQ            = 120, /* Reserved */
-    RESERVED121_IRQ            = 121, /* Reserved */
-    RESERVED122_IRQ            = 122, /* Reserved */
-    RESERVED123_IRQ            = 123, /* Reserved */
-    RESERVED124_IRQ            = 124, /* Reserved */
-    RESERVED125_IRQ            = 125, /* Reserved */
-    RESERVED126_IRQ            = 126, /* Reserved */
-    RESERVED127_IRQ            = 127, /* Reserved */
-    SCP_EXT_INTR0_IRQ          = 128, /* SCP Customer Extension */
-    SCP_EXT_INTR1_IRQ          = 129, /* SCP Customer Extension */
-    SCP_EXT_INTR2_IRQ          = 130, /* SCP Customer Extension */
-    SCP_EXT_INTR3_IRQ          = 131, /* SCP Customer Extension */
-    SCP_EXT_INTR4_IRQ          = 132, /* SCP Customer Extension */
-    SCP_EXT_INTR5_IRQ          = 133, /* SCP Customer Extension */
-    SCP_EXT_INTR6_IRQ          = 134, /* SCP Customer Extension */
-    SCP_EXT_INTR7_IRQ          = 135, /* SCP Customer Extension */
-    SCP_EXT_INTR8_IRQ          = 136, /* SCP Customer Extension */
-    SCP_EXT_INTR9_IRQ          = 137, /* SCP Customer Extension */
-    SCP_EXT_INTR10_IRQ         = 138, /* SCP Customer Extension */
-    SCP_EXT_INTR11_IRQ         = 139, /* SCP Customer Extension */
-    SCP_EXT_INTR12_IRQ         = 140, /* SCP Customer Extension */
-    SCP_EXT_INTR13_IRQ         = 141, /* SCP Customer Extension */
-    SCP_EXT_INTR14_IRQ         = 142, /* SCP Customer Extension */
-    SCP_EXT_INTR15_IRQ         = 143, /* SCP Customer Extension */
-    SCP_EXT_INTR16_IRQ         = 144, /* SCP Customer Extension */
-    SCP_EXT_INTR17_IRQ         = 145, /* SCP Customer Extension */
-    SCP_EXT_INTR18_IRQ         = 146, /* SCP Customer Extension */
-    SCP_EXT_INTR19_IRQ         = 147, /* SCP Customer Extension */
-    SCP_EXT_INTR20_IRQ         = 148, /* SCP Customer Extension */
-    SCP_EXT_INTR21_IRQ         = 149, /* SCP Customer Extension */
-    SCP_EXT_INTR22_IRQ         = 150, /* SCP Customer Extension */
-    SCP_EXT_INTR23_IRQ         = 151, /* SCP Customer Extension */
-    SCP_EXT_INTR24_IRQ         = 152, /* SCP Customer Extension */
-    SCP_EXT_INTR25_IRQ         = 153, /* SCP Customer Extension */
-    SCP_EXT_INTR26_IRQ         = 154, /* SCP Customer Extension */
-    SCP_EXT_INTR27_IRQ         = 155, /* SCP Customer Extension */
-    SCP_EXT_INTR28_IRQ         = 156, /* SCP Customer Extension */
-    SCP_EXT_INTR29_IRQ         = 157, /* SCP Customer Extension */
-    SCP_EXT_INTR30_IRQ         = 158, /* SCP Customer Extension */
-    SCP_EXT_INTR31_IRQ         = 159, /* SCP Customer Extension */
-};
-
-#endif /* SGM775_IRQ_H */
diff --git a/product/sgm775/scp_ramfw/config_mhu.c b/product/sgm775/scp_ramfw/config_mhu.c
index 38094c61..3df09453 100644
--- a/product/sgm775/scp_ramfw/config_mhu.c
+++ b/product/sgm775/scp_ramfw/config_mhu.c
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include "sgm775_irq.h"
 #include "sgm775_mhu.h"
 #include "sgm775_mmap.h"
 
@@ -15,6 +14,8 @@
 #include <fwk_id.h>
 #include <fwk_module.h>
 
+#include <fmw_cmsis.h>
+
 static const struct fwk_element mhu_element_table[] = {
     [SGM775_MHU_DEVICE_IDX_S] = {
         .name = "MHU_S",
diff --git a/product/sgm775/scp_ramfw/config_ppu_v0.c b/product/sgm775/scp_ramfw/config_ppu_v0.c
index 25a1451c..e2f196c9 100644
--- a/product/sgm775/scp_ramfw/config_ppu_v0.c
+++ b/product/sgm775/scp_ramfw/config_ppu_v0.c
@@ -6,7 +6,6 @@
  */
 
 #include "config_ppu_v0.h"
-#include "sgm775_irq.h"
 #include "sgm775_mmap.h"
 
 #include <mod_power_domain.h>
@@ -16,6 +15,8 @@
 #include <fwk_id.h>
 #include <fwk_module.h>
 
+#include <fmw_cmsis.h>
+
 #include <stdbool.h>
 #include <stddef.h>
 
diff --git a/product/sgm775/scp_ramfw/config_ppu_v1.c b/product/sgm775/scp_ramfw/config_ppu_v1.c
index dbbc3438..50b30219 100644
--- a/product/sgm775/scp_ramfw/config_ppu_v1.c
+++ b/product/sgm775/scp_ramfw/config_ppu_v1.c
@@ -7,7 +7,6 @@
 
 #include "config_power_domain.h"
 #include "sgm775_core.h"
-#include "sgm775_irq.h"
 #include "sgm775_mmap.h"
 
 #include <mod_power_domain.h>
@@ -19,6 +18,8 @@
 #include <fwk_module.h>
 #include <fwk_module_idx.h>
 
+#include <fmw_cmsis.h>
+
 #include <stddef.h>
 #include <stdint.h>
 
diff --git a/product/sgm775/scp_ramfw/config_system_power.c b/product/sgm775/scp_ramfw/config_system_power.c
index 7cd7e72b..038a2e51 100644
--- a/product/sgm775/scp_ramfw/config_system_power.c
+++ b/product/sgm775/scp_ramfw/config_system_power.c
@@ -6,7 +6,6 @@
  */
 
 #include "config_ppu_v0.h"
-#include "sgm775_irq.h"
 
 #include <mod_power_domain.h>
 #include <mod_sgm775_system.h>
@@ -18,6 +17,8 @@
 #include <fwk_module.h>
 #include <fwk_module_idx.h>
 
+#include <fmw_cmsis.h>
+
 #include <stdint.h>
 
 /*
diff --git a/product/sgm775/scp_ramfw/config_timer.c b/product/sgm775/scp_ramfw/config_timer.c
index 76ef9a71..bbac119b 100644
--- a/product/sgm775/scp_ramfw/config_timer.c
+++ b/product/sgm775/scp_ramfw/config_timer.c
@@ -7,7 +7,6 @@
 
 #include "clock_devices.h"
 #include "config_timer.h"
-#include "sgm775_irq.h"
 #include "sgm775_mmap.h"
 #include "system_clock.h"
 
@@ -19,6 +18,8 @@
 #include <fwk_module.h>
 #include <fwk_module_idx.h>
 
+#include <fmw_cmsis.h>
+
 /*
  * Generic timer driver config
  */
diff --git a/product/sgm775/scp_romfw/config_ppu_v0.c b/product/sgm775/scp_romfw/config_ppu_v0.c
index f57036f0..c965e590 100644
--- a/product/sgm775/scp_romfw/config_ppu_v0.c
+++ b/product/sgm775/scp_romfw/config_ppu_v0.c
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include "sgm775_irq.h"
 #include "sgm775_mmap.h"
 
 #include <mod_power_domain.h>
@@ -15,6 +14,8 @@
 #include <fwk_id.h>
 #include <fwk_module.h>
 
+#include <fmw_cmsis.h>
+
 #include <stdbool.h>
 
 static struct fwk_element sgm775_ppu_v0_element_table[] = {