diff options
author | Aditya Angadi <aditya.angadi@arm.com> | 2020-11-05 09:42:48 +0530 |
---|---|---|
committer | Thomas Abraham <thomas.abraham@arm.com> | 2020-11-28 01:48:28 +0530 |
commit | f9bef8b8006afe1564e6eb0e9ea0d5e344e7ed19 (patch) | |
tree | 61f24d250ae78f184cdbea6224922dd09b6a843a /product/rdn2/include/clock_soc.h | |
parent | 363019dcf97875e384d853b070a5705aa23962ea (diff) |
product/rdn2: add configuration data for PIK clock driver
The configuration data for PIK clock devices includes the base address
of control registers and the rate table with initial rate.
Change-Id: Iec4dcdf90770ac5ac6991997f0c5b4969a3646dd
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Diffstat (limited to 'product/rdn2/include/clock_soc.h')
-rw-r--r-- | product/rdn2/include/clock_soc.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/product/rdn2/include/clock_soc.h b/product/rdn2/include/clock_soc.h index c1112d3c..fbddb3ec 100644 --- a/product/rdn2/include/clock_soc.h +++ b/product/rdn2/include/clock_soc.h @@ -11,6 +11,7 @@ #include <fwk_macros.h> #define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) /* * PLL clock indexes. @@ -38,4 +39,34 @@ enum clock_pll_idx { CLOCK_PLL_IDX_COUNT }; +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_CLUS0_CPU0, + CLOCK_PIK_IDX_CLUS1_CPU0, + CLOCK_PIK_IDX_CLUS2_CPU0, + CLOCK_PIK_IDX_CLUS3_CPU0, + CLOCK_PIK_IDX_CLUS4_CPU0, + CLOCK_PIK_IDX_CLUS5_CPU0, + CLOCK_PIK_IDX_CLUS6_CPU0, + CLOCK_PIK_IDX_CLUS7_CPU0, + CLOCK_PIK_IDX_CLUS8_CPU0, + CLOCK_PIK_IDX_CLUS9_CPU0, + CLOCK_PIK_IDX_CLUS10_CPU0, + CLOCK_PIK_IDX_CLUS11_CPU0, + CLOCK_PIK_IDX_CLUS12_CPU0, + CLOCK_PIK_IDX_CLUS13_CPU0, + CLOCK_PIK_IDX_CLUS14_CPU0, + CLOCK_PIK_IDX_CLUS15_CPU0, + CLOCK_PIK_IDX_DMC, + CLOCK_PIK_IDX_INTERCONNECT, + CLOCK_PIK_IDX_SCP, + CLOCK_PIK_IDX_GIC, + CLOCK_PIK_IDX_PCLKSCP, + CLOCK_PIK_IDX_SYSPERCLK, + CLOCK_PIK_IDX_UARTCLK, + CLOCK_PIK_IDX_COUNT +}; + #endif /* CLOCK_SOC_H */ |