rcar/module: add rcar pd_sysc module and config data

Change-Id: I69b575fbeaeb33fc1b76618d3d516c26e6c9a793
Signed-off-by: Tsutomu Muroya <tsutomu.muroya.jy@bp.renesas.com>
Signed-off-by: Nicolas Royer <nroyer@baylibre.com>

7 files changed, 659 insertions, 0 deletions

diff --git a/product/rcar/module/rcar_pd_sysc/include/mod_rcar_pd_sysc.h b/product/rcar/module/rcar_pd_sysc/include/mod_rcar_pd_sysc.h
new file mode 100644
index 00000000..1faca31e
--- /dev/null
+++ b/product/rcar/module/rcar_pd_sysc/include/mod_rcar_pd_sysc.h
@@ -0,0 +1,84 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MOD_RCAR_PD_SYSC_H
+#define MOD_RCAR_PD_SYSC_H
+
+#include <mod_rcar_power_domain.h>
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*!
+ * \addtogroup GroupRCARModule RCAR Product Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupRCARPdSysc SYSC Driver
+ * @{
+ */
+
+/*!
+ * @cond
+ */
+
+/* Power domain context */
+struct rcar_sysc_pd_ctx {
+    /* Power domain configuration data */
+    const struct mod_rcar_pd_sysc_config *config;
+
+    /* Identifier of the entity bound to the power domain driver API */
+    fwk_id_t bound_id;
+
+    /* Power module driver input API */
+    struct mod_pd_driver_input_api *pd_driver_input_api;
+    /* Power Domain current state*/
+    unsigned int current_state;
+};
+
+/* Module context */
+struct rcar_sysc_ctx {
+    /* Table of the power domain contexts */
+    struct rcar_sysc_pd_ctx *pd_ctx_table;
+
+    /* Log API */
+    struct mod_log_api *log_api;
+};
+
+/*!
+ * @endcond
+ */
+
+/*!
+ * \brief Configuration data of a power domain of the SYSC module.
+ */
+struct mod_rcar_pd_sysc_config {
+    /*! Power domain type */
+    enum mod_pd_type pd_type;
+    /*! Offset of PWRSR register for this area */
+    unsigned int chan_offs;
+    /*! Bit in PWR* (except for PWRUP in PWRSR) */
+    unsigned char chan_bit;
+    /*! Bit in SYSCI*R */
+    unsigned char isr_bit;
+
+    /*!
+     * Flag indicating if this domain should be powered on during element init.
+     */
+    bool default_power_on;
+};
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_RCAR_PD_SYSC_H */
diff --git a/product/rcar/module/rcar_pd_sysc/src/Makefile b/product/rcar/module/rcar_pd_sysc/src/Makefile
new file mode 100644
index 00000000..41d2edb7
--- /dev/null
+++ b/product/rcar/module/rcar_pd_sysc/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Renesas SCP/MCP Software
+# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := RCAR_PS_SYSC
+BS_LIB_SOURCES = rcar_pd_sysc.c mod_rcar_pd_sysc.c
+
+include $(BS_DIR)/lib.mk
diff --git a/product/rcar/module/rcar_pd_sysc/src/mod_rcar_pd_sysc.c b/product/rcar/module/rcar_pd_sysc/src/mod_rcar_pd_sysc.c
new file mode 100644
index 00000000..daf39cc3
--- /dev/null
+++ b/product/rcar/module/rcar_pd_sysc/src/mod_rcar_pd_sysc.c
@@ -0,0 +1,214 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <rcar_pd_sysc.h>
+
+#include <mod_rcar_pd_sysc.h>
+#include <mod_rcar_power_domain.h>
+#include <mod_system_power.h>
+
+#include <fwk_assert.h>
+#include <fwk_id.h>
+#include <fwk_log.h>
+#include <fwk_macros.h>
+#include <fwk_mm.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+
+#include <stdint.h>
+
+/*
+ * Internal variables
+ */
+static struct rcar_sysc_ctx rcar_sysc_ctx;
+
+/*
+ * Power domain driver interface
+ */
+static int pd_set_state(fwk_id_t pd_id, unsigned int state)
+{
+    int status = FWK_SUCCESS;
+    struct rcar_sysc_pd_ctx *pd_ctx;
+
+    pd_ctx = rcar_sysc_ctx.pd_ctx_table + fwk_id_get_element_idx(pd_id);
+
+    switch (state) {
+    case MOD_PD_STATE_ON:
+        status = rcar_sysc_power(pd_ctx, true);
+        pd_ctx->current_state = state;
+        break;
+
+    case MOD_PD_STATE_OFF:
+        status = rcar_sysc_power(pd_ctx, false);
+        pd_ctx->current_state = state;
+        break;
+
+    default:
+        FWK_LOG_ERR("[PD] Requested power state (%i) is not supported.", state);
+        return FWK_E_PARAM;
+    }
+
+    return status;
+}
+
+static int pd_get_state(fwk_id_t pd_id, unsigned int *state)
+{
+    struct rcar_sysc_pd_ctx *pd_ctx;
+
+    pd_ctx = rcar_sysc_ctx.pd_ctx_table + fwk_id_get_element_idx(pd_id);
+
+    *state = pd_ctx->current_state;
+    return FWK_SUCCESS;
+}
+
+static int pd_reset(fwk_id_t pd_id)
+{
+    return FWK_SUCCESS;
+}
+
+static const struct mod_pd_driver_api pd_driver = {
+    .set_state = pd_set_state,
+    .get_state = pd_get_state,
+    .reset = pd_reset,
+};
+
+/*
+ * Framework handlers
+ */
+
+static int rcar_sysc_mod_init(
+    fwk_id_t module_id,
+    unsigned int pd_count,
+    const void *unused)
+{
+    rcar_sysc_ctx.pd_ctx_table =
+        fwk_mm_calloc(pd_count, sizeof(struct rcar_sysc_pd_ctx));
+    if (rcar_sysc_ctx.pd_ctx_table == NULL)
+        return FWK_E_NOMEM;
+
+    return FWK_SUCCESS;
+}
+
+static int rcar_sysc_pd_init(
+    fwk_id_t pd_id,
+    unsigned int unused,
+    const void *data)
+{
+    const struct mod_rcar_pd_sysc_config *config = data;
+    struct rcar_sysc_pd_ctx *pd_ctx;
+
+    if (config->pd_type >= MOD_PD_TYPE_COUNT)
+        return FWK_E_DATA;
+
+    pd_ctx = rcar_sysc_ctx.pd_ctx_table + fwk_id_get_element_idx(pd_id);
+    pd_ctx->config = config;
+    pd_ctx->bound_id = FWK_ID_NONE;
+
+    switch (config->pd_type) {
+    case MOD_PD_TYPE_DEVICE:
+    case MOD_PD_TYPE_DEVICE_DEBUG:
+    case MOD_PD_TYPE_SYSTEM:
+        return FWK_SUCCESS;
+    default:
+        return FWK_E_SUPPORT;
+    }
+}
+
+static int rcar_sysc_bind(fwk_id_t id, unsigned int round)
+{
+    struct rcar_sysc_pd_ctx *pd_ctx;
+
+    /* Nothing to do during the first round of calls where the power module
+       will bind to the power domains of this module. */
+    if (round == 0)
+        return FWK_SUCCESS;
+
+#if 0
+    /* In the case of the module, bind to the log component */
+    if (fwk_module_is_valid_module_id(id)) {
+        return fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG),
+                               FWK_ID_API(FWK_MODULE_IDX_LOG, 0),
+                               &rcar_sysc_ctx.log_api);
+    }
+#endif
+
+    pd_ctx = rcar_sysc_ctx.pd_ctx_table + fwk_id_get_element_idx(id);
+
+    if (fwk_id_is_equal(pd_ctx->bound_id, FWK_ID_NONE))
+        return FWK_SUCCESS;
+
+    switch (fwk_id_get_module_idx(pd_ctx->bound_id)) {
+    case FWK_MODULE_IDX_RCAR_POWER_DOMAIN:
+        return fwk_module_bind(
+            pd_ctx->bound_id,
+            mod_pd_api_id_driver_input,
+            &pd_ctx->pd_driver_input_api);
+        break;
+
+    case FWK_MODULE_IDX_SYSTEM_POWER:
+        return fwk_module_bind(
+            pd_ctx->bound_id,
+            mod_system_power_api_id_pd_driver_input,
+            &pd_ctx->pd_driver_input_api);
+        break;
+
+    default:
+        assert(false);
+        return FWK_E_SUPPORT;
+    }
+}
+
+static int rcar_sysc_process_bind_request(
+    fwk_id_t source_id,
+    fwk_id_t target_id,
+    fwk_id_t not_used,
+    const void **api)
+{
+    struct rcar_sysc_pd_ctx *pd_ctx;
+
+    pd_ctx = rcar_sysc_ctx.pd_ctx_table + fwk_id_get_element_idx(target_id);
+
+    switch (pd_ctx->config->pd_type) {
+    case MOD_PD_TYPE_SYSTEM:
+        if (!fwk_id_is_equal(pd_ctx->bound_id, FWK_ID_NONE)) {
+            assert(false);
+            return FWK_E_ACCESS;
+        }
+        /* Fallthrough */
+
+    case MOD_PD_TYPE_DEVICE:
+    case MOD_PD_TYPE_DEVICE_DEBUG:
+        if (fwk_id_get_module_idx(source_id) ==
+            FWK_MODULE_IDX_RCAR_POWER_DOMAIN) {
+            pd_ctx->bound_id = source_id;
+            *api = &pd_driver;
+            break;
+        }
+        if (fwk_id_get_module_idx(source_id) == FWK_MODULE_IDX_SYSTEM_POWER) {
+            *api = &pd_driver;
+            break;
+        }
+        assert(false);
+        return FWK_E_ACCESS;
+
+    default:
+        (void)pd_driver;
+        return FWK_E_SUPPORT;
+    }
+
+    return FWK_SUCCESS;
+}
+
+const struct fwk_module module_rcar_pd_sysc = {
+    .name = "RCAR_PD_SYSC",
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .api_count = 1,
+    .init = rcar_sysc_mod_init,
+    .element_init = rcar_sysc_pd_init,
+    .bind = rcar_sysc_bind,
+    .process_bind_request = rcar_sysc_process_bind_request,
+};
diff --git a/product/rcar/module/rcar_pd_sysc/src/rcar_pd_sysc.c b/product/rcar/module/rcar_pd_sysc/src/rcar_pd_sysc.c
new file mode 100644
index 00000000..09d7b0e2
--- /dev/null
+++ b/product/rcar/module/rcar_pd_sysc/src/rcar_pd_sysc.c
@@ -0,0 +1,104 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <rcar_common.h>
+#include <rcar_pd_sysc.h>
+
+#include <fwk_status.h>
+
+#include <stddef.h>
+
+/*****************************************************************************
+ * LOCAL FUNCTIONS
+ *****************************************************************************/
+static int rcar_sysc_pwr_on_off(struct rcar_sysc_pd_ctx *pd_ctx, bool on)
+{
+    unsigned int sr_bit, reg_offs;
+    int k;
+
+    if (on) {
+        sr_bit = SYSCSR_PONENB;
+        reg_offs = PWRONCR_OFFS;
+    } else {
+        sr_bit = SYSCSR_POFFENB;
+        reg_offs = PWROFFCR_OFFS;
+    }
+
+    /* Wait until SYSC is ready to accept a power request */
+    for (k = 0; k < SYSCSR_RETRIES; k++) {
+        if (mmio_read_32(SYSC_BASE_ADDR + SYSCSR) & BIT_SHIFT(sr_bit))
+            break;
+        udelay(SYSCSR_DELAY_US);
+    }
+
+    if (k == SYSCSR_RETRIES) {
+        return FWK_E_TIMEOUT;
+    }
+
+    /* Submit power shutoff or power resume request */
+    udelay(SYSCSR_DELAY_US);
+
+    mmio_write_32(
+        (SYSC_BASE_ADDR + pd_ctx->config->chan_offs + reg_offs),
+        BIT_SHIFT(pd_ctx->config->chan_bit));
+    return 0;
+}
+
+int rcar_sysc_power(struct rcar_sysc_pd_ctx *pd_ctx, bool on)
+{
+    unsigned int isr_mask = BIT_SHIFT(pd_ctx->config->isr_bit);
+    unsigned int chan_mask = BIT_SHIFT(pd_ctx->config->chan_bit);
+    unsigned int status;
+    int ret = 0;
+    int k;
+    uint32_t syscier, syscimr;
+
+    syscimr = mmio_read_32(SYSC_BASE_ADDR + SYSCIMR);
+    syscier = mmio_read_32(SYSC_BASE_ADDR + SYSCIER);
+    mmio_write_32((SYSC_BASE_ADDR + SYSCIMR), (syscimr | isr_mask));
+    mmio_write_32((SYSC_BASE_ADDR + SYSCIER), (syscier | isr_mask));
+    mmio_write_32((SYSC_BASE_ADDR + SYSCISCR), isr_mask);
+
+    /* Submit power shutoff or resume request until it was accepted */
+    for (k = 0; k < PWRER_RETRIES; k++) {
+        ret = rcar_sysc_pwr_on_off(pd_ctx, on);
+        if (ret)
+            return ret;
+
+        status = mmio_read_32(
+            SYSC_BASE_ADDR + pd_ctx->config->chan_offs + PWRER_OFFS);
+        if (!(status & chan_mask)) {
+            break;
+        }
+
+        udelay(PWRER_DELAY_US);
+    }
+
+    if (k == PWRER_RETRIES)
+        return FWK_E_BUSY;
+
+    /* Wait until the power shutoff or resume request has completed * */
+    for (k = 0; k < SYSCISR_RETRIES; k++) {
+        if (mmio_read_32(SYSC_BASE_ADDR + SYSCISR) & isr_mask)
+            break;
+        udelay(SYSCISR_DELAY_US);
+    }
+
+    if (k == SYSCISR_RETRIES) {
+        ret = FWK_E_BUSY;
+    }
+
+    mmio_write_32((SYSC_BASE_ADDR + SYSCISCR), isr_mask);
+
+    return ret;
+}
+
+int rcar_sysc_power_get(struct rcar_sysc_pd_ctx *pd_ctx, unsigned int *statee)
+{
+    return FWK_SUCCESS;
+}
diff --git a/product/rcar/module/rcar_pd_sysc/src/rcar_pd_sysc.h b/product/rcar/module/rcar_pd_sysc/src/rcar_pd_sysc.h
new file mode 100644
index 00000000..92901d53
--- /dev/null
+++ b/product/rcar/module/rcar_pd_sysc/src/rcar_pd_sysc.h
@@ -0,0 +1,70 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_PD_SYSC_H
+#define RCAR_PD_SYSC_H
+
+/*!
+ * \cond
+ * @{
+ */
+
+#include <mod_rcar_pd_sysc.h>
+
+#include <fwk_macros.h>
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#define BIT_SHIFT(nr) (1UL << (nr))
+
+/* SYSC Common */
+#define SYSC_BASE_ADDR (0xE6180000U) /* SYSC Base Address*/
+#define SYSCSR 0x00 /* SYSC Status Register */
+#define SYSCISR 0x04 /* Interrupt Status Register */
+#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
+#define SYSCIER 0x0c /* Interrupt Enable Register */
+#define SYSCIMR 0x10 /* Interrupt Mask Register */
+
+/* SYSC Status Register */
+#define SYSCSR_PONENB 1 /* Ready for power resume requests */
+#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
+
+/*
+ * Power Control Register Offsets inside the register block for each domain
+ * Note: The "CR" registers for ARM cores exist on H1 only
+ * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
+ * Use PSCI on R-Car Gen3
+ */
+#define PWRSR_OFFS 0x00 /* Power Status Register */
+#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
+#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
+#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
+#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
+#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
+
+#define SYSCSR_RETRIES 1000
+#define SYSCSR_DELAY_US 1
+
+#define PWRER_RETRIES 1000
+#define PWRER_DELAY_US 1
+
+#define SYSCISR_RETRIES 1000
+#define SYSCISR_DELAY_US 1
+
+/*
+ * Interface
+ */
+int rcar_sysc_power(struct rcar_sysc_pd_ctx *pd_ctx, bool on);
+int rcar_sysc_power_get(struct rcar_sysc_pd_ctx *pd_ctx, unsigned int *statee);
+
+/*!
+ * \endcond
+ * @}
+ */
+
+#endif /* RCAR_PD_SYSC_H */
diff --git a/product/rcar/scp_ramfw/config_rcar_pd_sysc.c b/product/rcar/scp_ramfw/config_rcar_pd_sysc.c
new file mode 100644
index 00000000..0b575923
--- /dev/null
+++ b/product/rcar/scp_ramfw/config_rcar_pd_sysc.c
@@ -0,0 +1,129 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <config_rcar_pd_sysc.h>
+
+#include <mod_rcar_pd_sysc.h>
+
+#include <fwk_element.h>
+#include <fwk_module.h>
+
+static struct fwk_element rcar_pd_sysc_element_table[] = {
+    [RCAR_PD_SYSC_ELEMENT_IDX_A3IR] =
+        {
+            .name = "a3ir",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x180,
+                .chan_bit = 0,
+                .isr_bit = R8A7795_PD_A3IR,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_3DGE] =
+        {
+            .name = "3dg-e",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x100,
+                .chan_bit = 4,
+                .isr_bit = R8A7795_PD_3DG_E,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_3DGD] =
+        {
+            .name = "3dg-d",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x100,
+                .chan_bit = 3,
+                .isr_bit = R8A7795_PD_3DG_D,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_3DGC] =
+        {
+            .name = "3dg-c",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x100,
+                .chan_bit = 2,
+                .isr_bit = R8A7795_PD_3DG_C,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_3DGB] =
+        {
+            .name = "3dg-b",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x100,
+                .chan_bit = 1,
+                .isr_bit = R8A7795_PD_3DG_B,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_3DGA] =
+        {
+            .name = "3dg-a",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x100,
+                .chan_bit = 0,
+                .isr_bit = R8A7795_PD_3DG_A,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_A2VC1] =
+        {
+            .name = "a2vc1",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x3c0,
+                .chan_bit = 1,
+                .isr_bit = R8A7795_PD_A2VC1,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_A3VC] =
+        {
+            .name = "a3vc",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x380,
+                .chan_bit = 0,
+                .isr_bit = R8A7795_PD_A3VC,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_CR7] =
+        {
+            .name = "cr7",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x240,
+                .chan_bit = 0,
+                .isr_bit = R8A7795_PD_CR7,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_A3VP] =
+        {
+            .name = "a3vp",
+            .data = &((struct mod_rcar_pd_sysc_config){
+                .pd_type = MOD_PD_TYPE_DEVICE,
+                .chan_offs = 0x340,
+                .chan_bit = 0,
+                .isr_bit = R8A7795_PD_A3VP,
+            }),
+        },
+    [RCAR_PD_SYSC_ELEMENT_IDX_COUNT] = { 0 }, /* Termination entry */
+};
+
+static const struct fwk_element *rcar_pd_sysc_get_element_table(fwk_id_t mod)
+{
+    return rcar_pd_sysc_element_table;
+}
+
+/*
+ * Power module configuration data
+ */
+const struct fwk_module_config config_rcar_pd_sysc = {
+    .elements = FWK_MODULE_DYNAMIC_ELEMENTS(rcar_pd_sysc_get_element_table),
+};
diff --git a/product/rcar/scp_ramfw/config_rcar_pd_sysc.h b/product/rcar/scp_ramfw/config_rcar_pd_sysc.h
new file mode 100644
index 00000000..ff786301
--- /dev/null
+++ b/product/rcar/scp_ramfw/config_rcar_pd_sysc.h
@@ -0,0 +1,47 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_RCAR_PD_SYSC_H
+#define CONFIG_RCAR_PD_SYSC_H
+
+enum rcar_pd_sysc_element_idx {
+    RCAR_PD_SYSC_ELEMENT_IDX_A3IR,
+    RCAR_PD_SYSC_ELEMENT_IDX_3DGE,
+    RCAR_PD_SYSC_ELEMENT_IDX_3DGD,
+    RCAR_PD_SYSC_ELEMENT_IDX_3DGC,
+    RCAR_PD_SYSC_ELEMENT_IDX_3DGB,
+    RCAR_PD_SYSC_ELEMENT_IDX_3DGA,
+    RCAR_PD_SYSC_ELEMENT_IDX_A2VC1,
+    RCAR_PD_SYSC_ELEMENT_IDX_A3VC,
+    RCAR_PD_SYSC_ELEMENT_IDX_CR7,
+    RCAR_PD_SYSC_ELEMENT_IDX_A3VP,
+    RCAR_PD_SYSC_ELEMENT_IDX_COUNT
+};
+
+#define R8A7795_PD_CA57_CPU0 0
+#define R8A7795_PD_CA57_CPU1 1
+#define R8A7795_PD_CA57_CPU2 2
+#define R8A7795_PD_CA57_CPU3 3
+#define R8A7795_PD_CA53_CPU0 5
+#define R8A7795_PD_CA53_CPU1 6
+#define R8A7795_PD_CA53_CPU2 7
+#define R8A7795_PD_CA53_CPU3 8
+#define R8A7795_PD_A3VP 9
+#define R8A7795_PD_CA57_SCU 12
+#define R8A7795_PD_CR7 13
+#define R8A7795_PD_A3VC 14
+#define R8A7795_PD_3DG_A 17
+#define R8A7795_PD_3DG_B 18
+#define R8A7795_PD_3DG_C 19
+#define R8A7795_PD_3DG_D 20
+#define R8A7795_PD_CA53_SCU 21
+#define R8A7795_PD_3DG_E 22
+#define R8A7795_PD_A3IR 24
+#define R8A7795_PD_A2VC0 25 /* ES1.x only */
+#define R8A7795_PD_A2VC1 26
+
+#endif /* CONFIG_RCAR_PD_SYSC_H */