diff options
author | Anurag Koul <anurag.koul@arm.com> | 2020-06-15 18:01:31 +0100 |
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committer | jimqui01 <54316584+jimqui01@users.noreply.github.com> | 2020-09-15 17:03:53 +0100 |
commit | d490f22a679365133e11f1db8dfe88ea730f61d4 (patch) | |
tree | f7786a41028859861c8cff3f1d18a4de20138da9 /product/morello | |
parent | b8495d675cdf7e3ca933cf24ae562e6910b4ed9d (diff) |
morello/mcp_ramfw_fvp: add config files for mcp ramfw
Change-Id: Ib2d83545a4ab1f484b83a384e2483aa526785118
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Diffstat (limited to 'product/morello')
-rw-r--r-- | product/morello/mcp_ramfw_fvp/RTX_Config.h | 56 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/config_armv7m_mpu.c | 64 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/config_clock.c | 14 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/config_clock.h | 28 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/config_pik_clock.c | 83 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/config_pl011.c | 32 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/fmw_cmsis.h | 13 | ||||
-rw-r--r-- | product/morello/mcp_ramfw_fvp/rtx_config.c | 57 |
8 files changed, 347 insertions, 0 deletions
diff --git a/product/morello/mcp_ramfw_fvp/RTX_Config.h b/product/morello/mcp_ramfw_fvp/RTX_Config.h new file mode 100644 index 00000000..d3dc1e19 --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/RTX_Config.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RTX2 v5 configuration file. + * The file must be called RTX_Config.h as it is included by an RTX + * file in order to create an object file containing the configuration. + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +/* System */ +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 + +/* Thread */ +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 + +/* Timer */ +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_CB_QUEUE 4 + +/* Event flags */ +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 + +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 + +#endif /* RTX_CONFIG_H_ */ diff --git a/product/morello/mcp_ramfw_fvp/config_armv7m_mpu.c b/product/morello/mcp_ramfw_fvp/config_armv7m_mpu.c new file mode 100644 index 00000000..227d66a3 --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/config_armv7m_mpu.c @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_mcp_system_mmap.h" + +#include <mod_armv7m_mpu.h> + +#include <fwk_macros.h> +#include <fwk_module.h> + +#include <fmw_cmsis.h> + +static const ARM_MPU_Region_t regions[] = { + { + /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), + }, + { + /* 0x0080_0000 - 0x0087_FFFF */ + .RBAR = ARM_MPU_RBAR(1, MCP_RAM0_BASE), + .RASR = ARM_MPU_RASR( + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_512KB), + }, + { + /* 0x2000_0000 - 0x2003_FFFF */ + .RBAR = ARM_MPU_RBAR(2, MCP_RAM1_BASE), + .RASR = ARM_MPU_RASR( + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/morello/mcp_ramfw_fvp/config_clock.c b/product/morello/mcp_ramfw_fvp/config_clock.c new file mode 100644 index 00000000..f715beef --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/config_clock.c @@ -0,0 +1,14 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_module.h> + +/* + * Empty placeholder for compatibility as all clocks are + * managed by SCP. + */ +const struct fwk_module_config config_clock = { 0 }; diff --git a/product/morello/mcp_ramfw_fvp/config_clock.h b/product/morello/mcp_ramfw_fvp/config_clock.h new file mode 100644 index 00000000..1aa678d2 --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/config_clock.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_CLOCK_H +#define CONFIG_CLOCK_H + +#include <fwk_macros.h> + +/* + * PIK clock rates. + */ +#define PIK_CLK_RATE_MCP_CORECLK (300 * FWK_MHZ) +#define PIK_CLK_RATE_MCP_AXICLK (300 * FWK_MHZ) + +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_MCP_CORECLK, + CLOCK_PIK_IDX_MCP_AXICLK, + CLOCK_PIK_IDX_COUNT +}; + +#endif /* CONFIG_CLOCK_H */ diff --git a/product/morello/mcp_ramfw_fvp/config_pik_clock.c b/product/morello/mcp_ramfw_fvp/config_pik_clock.c new file mode 100644 index 00000000..df4a71c3 --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/config_pik_clock.c @@ -0,0 +1,83 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_clock.h" +#include "morello_mcp_pik.h" +#include "morello_pik_mcp.h" +#include "morello_system_clock.h" + +#include <mod_pik_clock.h> + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_macros.h> +#include <fwk_module.h> + +#include <stdbool.h> + +/* + * Rate lookup tables + */ + +static const struct mod_pik_clock_rate rate_table_mcp_coreclk[] = { + { + .rate = PIK_CLK_RATE_MCP_CORECLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_CORECLK, + }, +}; + +static const struct mod_pik_clock_rate rate_table_mcp_axiclk[] = { + { + .rate = PIK_CLK_RATE_MCP_AXICLK, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_AXICLK, + }, +}; + +static const struct fwk_element pik_clock_element_table[] = { + [CLOCK_PIK_IDX_MCP_CORECLK] = + { + .name = "MCP CORECLK", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_MCP->CORECLK_CTRL, + .divsys_reg = &PIK_MCP->CORECLK_DIV1, + .rate_table = rate_table_mcp_coreclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_coreclk), + .initial_rate = PIK_CLK_RATE_MCP_CORECLK, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_MCP_AXICLK] = + { + .name = "MCP AXICLK", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_MCP->CORECLK_CTRL, + .divsys_reg = &PIK_MCP->CORECLK_DIV1, + .rate_table = rate_table_mcp_axiclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_axiclk), + .initial_rate = PIK_CLK_RATE_MCP_AXICLK, + .defer_initialization = true, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), +}; diff --git a/product/morello/mcp_ramfw_fvp/config_pl011.c b/product/morello/mcp_ramfw_fvp/config_pl011.c new file mode 100644 index 00000000..32fec589 --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/config_pl011.c @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_mcp_mmap.h" +#include "morello_system_clock.h" + +#include <mod_pl011.h> + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_module.h> + +struct fwk_module_config config_pl011 = { + .elements = FWK_MODULE_STATIC_ELEMENTS({ + [0] = { + .name = "MCP-UART", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = MCP_UART0_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_NONE_INIT, + }, + }, + + [1] = { 0 }, + }), +}; diff --git a/product/morello/mcp_ramfw_fvp/fmw_cmsis.h b/product/morello/mcp_ramfw_fvp/fmw_cmsis.h new file mode 100644 index 00000000..34fb79fa --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/fmw_cmsis.h @@ -0,0 +1,13 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#include <fmw_cmsis_mcp.h> + +#endif /* FMW_CMSIS_H */ diff --git a/product/morello/mcp_ramfw_fvp/rtx_config.c b/product/morello/mcp_ramfw_fvp/rtx_config.c new file mode 100644 index 00000000..c95f62eb --- /dev/null +++ b/product/morello/mcp_ramfw_fvp/rtx_config.c @@ -0,0 +1,57 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "morello_system_clock.h" + +#include <rtx_lib.c> +#include <rtx_os.h> + +#include <fwk_mm.h> + +#include <fmw_cmsis.h> + +#include <stdbool.h> +#include <stdint.h> + +/* + * Required by RTX to configure the SysTick timer. + */ +uint32_t SystemCoreClock = CLOCK_RATE_REFCLK; + +/* + * Idle thread + */ +__NO_RETURN void osRtxIdleThread(void *argument) +{ + while (true) + __WFI(); +} + +/* + * OS error handler + */ +uint32_t osRtxErrorNotify(uint32_t code, void *object_id) +{ + osRtxIdleThread(object_id); +} + +uint32_t osRtxMemoryInit(void *mem, uint32_t size) +{ + return 1; +} + +void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type) +{ + return fwk_mm_alloc(1, size); +} + +uint32_t osRtxMemoryFree(void *mem, void *block) +{ + fwk_mm_free(block); + + return 1; +} |