diff options
| author | Anurag Koul <anurag.koul@arm.com> | 2020-06-09 13:29:02 +0100 |
|---|---|---|
| committer | jimqui01 <54316584+jimqui01@users.noreply.github.com> | 2020-09-15 17:03:53 +0100 |
| commit | b8495d675cdf7e3ca933cf24ae562e6910b4ed9d (patch) | |
| tree | 078fe7317aaccbf3c7c785585db621754656a098 /product/morello | |
| parent | 4531d244bc40aab5fd0e9282d823c909d4c0edf3 (diff) | |
morello: add pik register definitions for mcp
Change-Id: I36b84a067abf874bcde95d3383dc0b51c1768ad4
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Diffstat (limited to 'product/morello')
| -rw-r--r-- | product/morello/include/morello_mcp_pik.h | 16 | ||||
| -rw-r--r-- | product/morello/include/morello_pik_mcp.h | 61 |
2 files changed, 77 insertions, 0 deletions
diff --git a/product/morello/include/morello_mcp_pik.h b/product/morello/include/morello_mcp_pik.h new file mode 100644 index 00000000..b879115e --- /dev/null +++ b/product/morello/include/morello_mcp_pik.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MORELLO_MCP_PIK_H +#define MORELLO_MCP_PIK_H + +#include "morello_mcp_mmap.h" +#include "morello_pik_mcp.h" + +#define PIK_MCP ((struct pik_mcp_reg *)MCP_PIK_BASE) + +#endif /* MORELLO_MCP_PIK_H */ diff --git a/product/morello/include/morello_pik_mcp.h b/product/morello/include/morello_pik_mcp.h new file mode 100644 index 00000000..5a985f23 --- /dev/null +++ b/product/morello/include/morello_pik_mcp.h @@ -0,0 +1,61 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MCP PIK registers + */ + +#ifndef MORELLO_PIK_MCP_H +#define MORELLO_PIK_MCP_H + +#include <fwk_macros.h> + +#include <stdint.h> + +/*! + * \brief MCP PIK register definitions + */ +struct pik_mcp_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0xA10 - 0x828]; + FWK_R uint32_t PLL_STATUS0; + uint8_t RESERVED8[0xFC0 - 0xA14]; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED18[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* MORELLO_PIK_MCP_H */ |