morello: add memory map headers for mcp

- Add MCP's peripheral memory map.
- Add MCP software mappings of memory shared b/w SCP and MCP.
- Add MCP's internal/external system memory map (ROM, SRAM, Flash, etc.).

Change-Id: I12a83a6b94d8635b10d078e969b780176e5b4cea
Signed-off-by: Anurag Koul <anurag.koul@arm.com>

3 files changed, 138 insertions, 0 deletions

diff --git a/product/morello/include/morello_mcp_mmap.h b/product/morello/include/morello_mcp_mmap.h
new file mode 100644
index 00000000..2b9377d1
--- /dev/null
+++ b/product/morello/include/morello_mcp_mmap.h
@@ -0,0 +1,68 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MORELLO_MCP_MMAP_H
+#define MORELLO_MCP_MMAP_H
+
+#include <stdint.h>
+
+/*
+ * Top-level base addresses
+ */
+#define MCP_SOC_EXPANSION1_BASE UINT32_C(0x01000000)
+#define MCP_SOC_EXPANSION2_BASE UINT32_C(0x21000000)
+#define MCP_SOC_EXPANSION3_BASE UINT32_C(0x40000000)
+#define MCP_SOC_EXPANSION4_BASE UINT32_C(0x48000000)
+#define MCP_PERIPH_BASE UINT32_C(0x4C000000)
+#define MCP_MEMORY_CONTROLLER UINT32_C(0x4E000000)
+#define MCP_POWER_PERIPH_BASE UINT32_C(0x50000000)
+#define MCP_SYS0_BASE UINT32_C(0x60000000)
+#define MCP_SYS1_BASE UINT32_C(0xA0000000)
+#define MCP_PPB_BASE_INTERNAL UINT32_C(0xE0000000)
+#define MCP_PPB_BASE_EXTERNAL UINT32_C(0xE0040000)
+
+/*
+ * Peripherals
+ */
+#define MCP_REFCLK_CNTCTL_BASE (MCP_PERIPH_BASE)
+#define MCP_REFCLK_CNTBASE0_BASE (MCP_PERIPH_BASE + 0x1000)
+#define MCP_UART0_BASE (MCP_PERIPH_BASE + 0x2000)
+#define MCP_WDOG_BASE (MCP_PERIPH_BASE + 0x6000)
+
+#define MCP_I2C0_BASE (0x3FFFE000)
+#define MCP_I2C1_BASE (0x3FFFF000)
+
+/*
+ * Power control peripherals
+ */
+#define MCP_PIK_BASE (MCP_POWER_PERIPH_BASE)
+
+/*
+ * Base addresses of MHUv1 devices
+ */
+#define MCP_MHU_AP_BASE (MCP_PERIPH_BASE + 0x400000)
+#define MCP_MHU_SCP_BASE UINT32_C(0x45600000)
+
+#define MHU_MCP_TO_AP_NS (MCP_MHU_AP_BASE + 0x0020)
+#define MHU_AP_TO_MCP_NS (MCP_MHU_AP_BASE + 0x0120)
+#define MHU_MCP_TO_AP_S (MCP_MHU_AP_BASE + 0x0200)
+#define MHU_AP_TO_MCP_S (MCP_MHU_AP_BASE + 0x0300)
+
+#define MHU_SCP_TO_MCP_NS (MCP_MHU_SCP_BASE + 0x0020)
+#define MHU_MCP_TO_SCP_NS (MCP_MHU_SCP_BASE + 0x0120)
+#define MHU_SCP_TO_MCP_S (MCP_MHU_SCP_BASE + 0x0200)
+#define MHU_MCP_TO_SCP_S (MCP_MHU_SCP_BASE + 0x0300)
+
+/*
+ * Shared memory regions
+ */
+#define MCP_AP_SHARED_SECURE_RAM (MCP_PERIPH_BASE + 0x420000)
+#define MCP_AP_SHARED_NONSECURE_RAM (MCP_PERIPH_BASE + 0x410000)
+#define MCP_SCP_SHARED_SECURE_RAM (0x45620000)
+#define MCP_SCP_SHARED_NONSECURE_RAM (0x45610000)
+
+#endif /* MORELLO_MCP_MMAP_H */
diff --git a/product/morello/include/morello_mcp_software_mmap.h b/product/morello/include/morello_mcp_software_mmap.h
new file mode 100644
index 00000000..a4c18da0
--- /dev/null
+++ b/product/morello/include/morello_mcp_software_mmap.h
@@ -0,0 +1,29 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     Software defined memory map shared between SCP and MCP cores.
+ */
+
+#ifndef MORELLO_MCP_SOFTWARE_MMAP_H
+#define MORELLO_MCP_SOFTWARE_MMAP_H
+
+#include "morello_mcp_mmap.h"
+
+/* SCMI payload size */
+#define MCP_SCMI_PAYLOAD_SIZE (128)
+
+/* SCMI non-secure payload areas */
+#define SCMI_PAYLOAD_SCP_TO_MCP_NS (MCP_SCP_SHARED_NONSECURE_RAM)
+#define SCMI_PAYLOAD_MCP_TO_SCP_NS \
+    (MCP_SCP_SHARED_NONSECURE_RAM + MCP_SCMI_PAYLOAD_SIZE)
+
+/* SCMI secure payload areas */
+#define SCMI_PAYLOAD_SCP_TO_MCP_S (MCP_SCP_SHARED_SECURE_RAM)
+#define SCMI_PAYLOAD_MCP_TO_SCP_S \
+    (MCP_SCP_SHARED_SECURE_RAM + MCP_SCMI_PAYLOAD_SIZE)
+
+#endif /* MORELLO_MCP_SOFTWARE_MMAP_H */
diff --git a/product/morello/include/morello_mcp_system_mmap.h b/product/morello/include/morello_mcp_system_mmap.h
new file mode 100644
index 00000000..fd356ef0
--- /dev/null
+++ b/product/morello/include/morello_mcp_system_mmap.h
@@ -0,0 +1,41 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MORELLO_MCP_SYSTEM_MMAP_H
+#define MORELLO_MCP_SYSTEM_MMAP_H
+
+/*
+ * External QSPI flash memory - mapped address
+ */
+#define MCP_QSPI_FLASH_BASE_ADDR 0x30000000
+#define MCP_QSPI_FLASH_BASE_ADDR_ALT 0x00800000
+#define MCP_QSPI_FLASH_SIZE 0x02000000
+
+/*
+ * Internal MCP's ROM/RAM base address
+ */
+#define MCP_ROM_BASE 0x00000000
+#define MCP_RAM0_BASE 0x00800000
+#define MCP_RAM1_BASE 0x20000000
+
+/*
+ * Internal MCP's ROM/RAM sizes
+ */
+#define MCP_ROM_SIZE (128 * 1024)
+#define MCP_RAM0_SIZE (512 * 1024)
+#define MCP_RAM1_SIZE (256 * 1024)
+
+/*
+ * MCP_BACKUP_DDR3 memory area where the MCP ROM
+ * bypass firmware should be placed. The MCP would
+ * be programmed to boot at this address by programming
+ * it in the MCP_BOOT_ADR SCC register.
+ */
+#define MCP_BACKUP_DDR3_BASE 0x16000000
+#define MCP_BACKUP_DDR3_SIZE (32 * 1024 * 1024)
+
+#endif /* MORELLO_MCP_SYSTEM_MMAP_H */