diff options
| author | Aditya Angadi <aditya.angadi@arm.com> | 2020-01-27 09:29:46 +0530 |
|---|---|---|
| committer | jimqui01 <54316584+jimqui01@users.noreply.github.com> | 2020-04-15 13:50:41 +0100 |
| commit | 20f3bc7738faaa997183187a8000ef400a766d8c (patch) | |
| tree | 932fb3991a45157f7519bd9365a01942c0550c4a | |
| parent | 69ed7d6837ef104923478bc8b647f74265f57084 (diff) | |
product/rddanielxlr: add build support for scp ram firmware
Add the makefile to build the RAM firmware and the corresponding linker
script.
Change-Id: I458a7303cf041b3d75417a10752b9c61fe8d8770
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
| -rw-r--r-- | product/rddanielxlr/include/scp_software_mmap.h | 1 | ||||
| -rw-r--r-- | product/rddanielxlr/scp_ramfw/firmware.mk | 64 | ||||
| -rw-r--r-- | product/rddanielxlr/scp_ramfw/fmw_memory.h | 33 |
3 files changed, 98 insertions, 0 deletions
diff --git a/product/rddanielxlr/include/scp_software_mmap.h b/product/rddanielxlr/include/scp_software_mmap.h index a9eff8d0..36693662 100644 --- a/product/rddanielxlr/include/scp_software_mmap.h +++ b/product/rddanielxlr/include/scp_software_mmap.h @@ -15,6 +15,7 @@ /* SCP ROM and RAM firmware size loaded on main memory */ #define SCP_BOOT_ROM_SIZE (64 * 1024) #define SCP_DTC_RAM_SIZE (256 * 1024) +#define SCP_ITC_RAM_SIZE (256 * 1024) /* SCP RAM firmware base and size on the flash */ #define SCP_RAMFW_IMAGE_FLASH_BASE (SCP_NOR0_FLASH_BASE + 0x03D80000) diff --git a/product/rddanielxlr/scp_ramfw/firmware.mk b/product/rddanielxlr/scp_ramfw/firmware.mk new file mode 100644 index 00000000..b175cf69 --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/firmware.mk @@ -0,0 +1,64 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := yes +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_NOTIFICATION_COUNT := 128 + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + sid \ + system_info \ + pcid \ + pl011 \ + log \ + pik_clock \ + css_clock \ + clock \ + gtimer \ + timer \ + cmn_rhodes \ + ppu_v1 \ + system_power \ + mhu2 \ + smt \ + scmi \ + sds \ + system_pll \ + apcontext \ + power_domain \ + scmi_power_domain \ + scmi_system_power \ + rddanielxlr_system + +BS_FIRMWARE_SOURCES := \ + config_system_power.c \ + config_sid.c \ + config_system_info.c \ + rtx_config.c \ + config_armv7m_mpu.c \ + config_pl011.c \ + config_log.c \ + config_power_domain.c \ + config_ppu_v1.c \ + config_mhu2.c \ + config_smt.c \ + config_scmi.c \ + config_sds.c \ + config_timer.c \ + config_gtimer.c \ + config_cmn_rhodes.c \ + config_scmi_system_power.c \ + config_scmi_power_domain.c \ + config_system_pll.c \ + config_pik_clock.c \ + config_css_clock.c \ + config_clock.c \ + config_apcontext.c + +include $(BS_DIR)/firmware.mk diff --git a/product/rddanielxlr/scp_ramfw/fmw_memory.h b/product/rddanielxlr/scp_ramfw/fmw_memory.h new file mode 100644 index 00000000..446e743e --- /dev/null +++ b/product/rddanielxlr/scp_ramfw/fmw_memory.h @@ -0,0 +1,33 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_H +#define FMW_MEMORY_H + +#include "scp_mmap.h" +#include "scp_software_mmap.h" + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FIRMWARE_MEM0_SIZE SCP_ITC_RAM_SIZE +#define FIRMWARE_MEM0_BASE SCP_ITC_RAM_BASE + +/* + * RAM data memory + */ +#define FIRMWARE_MEM1_SIZE SCP_DTC_RAM_SIZE +#define FIRMWARE_MEM1_BASE SCP_DTC_RAM_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_H */ |