morello: make ROM code to use SCC BOOT_GPR0 for FIP

This patch makes ROM code flexible in a way user can load FIP
capsule image in any memory that SCP can access and set the
SCC BOOT_GPR0 to that memory such that ROM code reads SCC
BOOT_GPR0 and uses that as FIP base if it has a non-zero value.

Change-Id: Iec4bb2fbc81ed48766680813d2dc0721e7c9ac86
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

2 files changed, 40 insertions, 10 deletions

diff --git a/product/morello/module/morello_rom/src/mod_morello_rom.c b/product/morello/module/morello_rom/src/mod_morello_rom.c
index bb3931bf..8203440f 100644
--- a/product/morello/module/morello_rom/src/mod_morello_rom.c
+++ b/product/morello/module/morello_rom/src/mod_morello_rom.c
@@ -5,6 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include "morello_scp_pik.h"
+
 #include <mod_fip.h>
 #include <mod_morello_rom.h>
 
@@ -20,6 +22,7 @@
 #include <fmw_cmsis.h>
 
 #include <inttypes.h>
+#include <stddef.h>
 #include <stdint.h>
 #include <string.h>
 
@@ -120,11 +123,30 @@ static int morello_rom_process_event(
     struct fwk_event *resp)
 {
     struct mod_fip_entry_data entry;
-    int status = morello_rom_ctx.fip_api->get_entry(
-        morello_rom_ctx.rom_config->image_type,
-        &entry,
-        morello_rom_ctx.rom_config->fip_base_address,
-        morello_rom_ctx.rom_config->fip_nvm_size);
+    uintptr_t fip_base;
+    size_t fip_size;
+    int status;
+
+    /*
+     * SCP ROM has the flexibility to choose where to look for FIP header
+     * based on the SCC BOOT_GPR0 register. If SCC BOOT_GPR0 has non-zero
+     * value use that as FIP storage else use the base address passed from
+     * config file.
+     */
+    if ((morello_rom_ctx.rom_config->image_type == MOD_FIP_TOC_ENTRY_SCP_BL2) &&
+        (SCC->BOOT_GPR0 != 0x0)) {
+        fip_base = SCC->BOOT_GPR0;
+        /* Assume maximum size limit */
+        fip_size = 0xFFFFFFFF;
+    } else {
+        fip_base = morello_rom_ctx.rom_config->fip_base_address;
+        fip_size = morello_rom_ctx.rom_config->fip_nvm_size;
+    }
+
+    FWK_LOG_INFO("[ROM] Trying to identify FIP at 0x%X\n", fip_base);
+
+    status = morello_rom_ctx.fip_api->get_entry(
+        morello_rom_ctx.rom_config->image_type, &entry, fip_base, fip_size);
     const char *image_type =
         get_image_type_str(morello_rom_ctx.rom_config->image_type);
 
diff --git a/product/morello/module/morello_system/src/mod_morello_system.c b/product/morello/module/morello_system/src/mod_morello_system.c
index 374ae9e4..d38d7e7a 100644
--- a/product/morello/module/morello_system/src/mod_morello_system.c
+++ b/product/morello/module/morello_system/src/mod_morello_system.c
@@ -43,6 +43,7 @@
 
 #include <inttypes.h>
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 #include <string.h>
 
@@ -330,6 +331,8 @@ static int morello_system_init_primary_core(void)
     unsigned int core_idx;
     unsigned int cluster_idx;
     unsigned int cluster_count;
+    uintptr_t fip_base;
+    size_t fip_size;
 
     FWK_LOG_INFO(
         "[MORELLO SYSTEM] Setting AP Reset Address to 0x%08" PRIX32,
@@ -348,12 +351,17 @@ static int morello_system_init_primary_core(void)
 
     if (morello_get_chipid() == 0x0) {
         struct mod_fip_entry_data entry;
-        status = morello_system_ctx.fip_api->get_entry(
-            MOD_FIP_TOC_ENTRY_TFA_BL31,
-            &entry,
-            SCP_QSPI_FLASH_BASE_ADDR,
-            SCP_QSPI_FLASH_SIZE);
+        if (SCC->BOOT_GPR0 != 0x0) {
+            fip_base = SCC->BOOT_GPR0;
+            /* Assume maximum size limit */
+            fip_size = 0xFFFFFFFF;
+        } else {
+            fip_base = SCP_QSPI_FLASH_BASE_ADDR;
+            fip_size = SCP_QSPI_FLASH_SIZE;
+        }
 
+        status = morello_system_ctx.fip_api->get_entry(
+            MOD_FIP_TOC_ENTRY_TFA_BL31, &entry, fip_base, fip_size);
         if (status != FWK_SUCCESS) {
             FWK_LOG_INFO(
                 "[MORELLO SYSTEM] Failed to locate AP TF_BL31, error: %d\n",