diff options
| author | Jagadeesh Ujja <jagadeesh.ujja@arm.com> | 2020-11-10 12:31:04 +0530 |
|---|---|---|
| committer | tarek-arm <56722698+tarek-arm@users.noreply.github.com> | 2020-11-11 09:48:00 +0000 |
| commit | 3deb59c5f4c64aa092bb3a4ebc018acf3f746f47 (patch) | |
| tree | 1ac67e9684df16a72ca905991ce1b3069d4215a7 | |
| parent | 5ebacc4ba7f194f8598071febd8e60edf0beb2a0 (diff) | |
product/n1sdp: set CCIX speed to GEN3 to work with interposer C2C setup
Set CCIX speed to GEN3 to work with interposer C2C setup
In this use case set downstream/upstream port transmitter
preset value to 4.
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: I635566574babbb7591b5bba97105f76f1f8e550a
| -rw-r--r-- | product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c index 901e0464..ba02144f 100644 --- a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c +++ b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c @@ -206,7 +206,12 @@ static int n1sdp_pcie_phy_init(fwk_id_t id) if (dev_ctx == NULL) return FWK_E_PARAM; - gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3; + if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable || + pcie_ctx.c2c_api->is_slave_alive()) + gen_speed = PCIE_GEN_3; + else + gen_speed = PCIE_GEN_4; + lane_count = LAN_COUNT_IN_X_16; FWK_LOG_INFO("[%s] Initializing PHY...", pcie_type[did]); @@ -239,7 +244,12 @@ static int n1sdp_pcie_controller_init(fwk_id_t id, bool ep_mode) if (dev_ctx == NULL) return FWK_E_PARAM; - gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3; + if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable || + pcie_ctx.c2c_api->is_slave_alive()) + gen_speed = PCIE_GEN_3; + else + gen_speed = PCIE_GEN_4; + lane_count = LAN_COUNT_IN_X_16; if (ep_mode) { @@ -282,12 +292,18 @@ static int n1sdp_pcie_link_training(fwk_id_t id, bool ep_mode) if (dev_ctx == NULL) return FWK_E_PARAM; - gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3; + if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable || + pcie_ctx.c2c_api->is_slave_alive()) { + gen_speed = PCIE_GEN_3; + down_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE; + up_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE; + } else { + gen_speed = PCIE_GEN_4; + down_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE; + up_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE; + } + lane_count = LAN_COUNT_IN_X_16; - down_stream_tx_preset = dev_ctx->config->ccix_capable ? - CCIX_RC_TX_PRESET_VALUE : PCIE_RC_TX_PRESET_VALUE; - up_stream_tx_preset = dev_ctx->config->ccix_capable ? - CCIX_RC_TX_PRESET_VALUE : PCIE_RC_TX_PRESET_VALUE; if (gen_speed >= PCIE_GEN_3 && !ep_mode) { FWK_LOG_INFO( |