diff options
| author | Usama Arif <usama.arif@arm.com> | 2020-09-23 10:55:29 +0100 |
|---|---|---|
| committer | Chris Kay <chris@cjkay.com> | 2020-09-25 13:33:26 +0100 |
| commit | 251eec399f29b2f5f7d50fcaed464a13bcff7fbe (patch) | |
| tree | ca363ea62a3bc8e83eeaad89c88021af505f11d3 | |
| parent | a0f3d7e9a9d7116e9ec0fff5326ca727d1d5f6ad (diff) | |
tc0: apply clang-format to platform
Any new patches apply clang-format to them.
This patch will allow consistency to entire platform.
Change-Id: I295b0e00eeb22affb97062a5fa243d0dafdd5654
Signed-off-by: Usama Arif <usama.arif@arm.com>
45 files changed, 1201 insertions, 1088 deletions
diff --git a/product/tc0/include/clock_soc.h b/product/tc0/include/clock_soc.h index d129c872..1303cf5f 100644 --- a/product/tc0/include/clock_soc.h +++ b/product/tc0/include/clock_soc.h @@ -10,8 +10,8 @@ #include <fwk_macros.h> -#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) -#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) +#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) /* * PLL clock indexes. diff --git a/product/tc0/include/cpu_pik.h b/product/tc0/include/cpu_pik.h index 5ec66456..ab3fd95a 100644 --- a/product/tc0/include/cpu_pik.h +++ b/product/tc0/include/cpu_pik.h @@ -14,78 +14,77 @@ #include <stdint.h> - /*! * \brief PE Static Configuration register definitions */ struct static_config_reg { - FWK_RW uint32_t STATIC_CONFIG; - FWK_RW uint32_t RVBARADDR_LW; - FWK_RW uint32_t RVBARADDR_UP; - uint32_t RESERVED; + FWK_RW uint32_t STATIC_CONFIG; + FWK_RW uint32_t RVBARADDR_LW; + FWK_RW uint32_t RVBARADDR_UP; + uint32_t RESERVED; }; /*! * \brief AP cores clock control register definitions */ struct coreclk_reg { - FWK_RW uint32_t CTRL; - FWK_RW uint32_t DIV; - uint32_t RESERVED; - FWK_RW uint32_t MOD; + FWK_RW uint32_t CTRL; + FWK_RW uint32_t DIV; + uint32_t RESERVED; + FWK_RW uint32_t MOD; }; /*! * \brief CPU (V8.2) PIK register definitions */ struct pik_cpu_reg { - FWK_RW uint32_t CLUSTER_CONFIG; - uint8_t RESERVED0[0x10 - 0x4]; + FWK_RW uint32_t CLUSTER_CONFIG; + uint8_t RESERVED0[0x10 - 0x4]; struct static_config_reg STATIC_CONFIG[16]; - uint8_t RESERVED1[0x800 - 0x110]; - FWK_RW uint32_t PPUCLK_CTRL; - FWK_RW uint32_t PPUCLK_DIV1; - uint8_t RESERVED2[0x810 - 0x808]; - FWK_RW uint32_t PCLK_CTRL; - uint8_t RESERVED3[0x820 - 0x814]; - FWK_RW uint32_t DBGCLK_CTRL; - FWK_RW uint32_t DBGCLK_DIV1; - uint8_t RESERVED4[0x830 - 0x828]; - FWK_RW uint32_t GICCLK_CTRL; - uint8_t RESERVED5[0x840 - 0x834]; - FWK_RW uint32_t AMBACLK_CTRL; - uint8_t RESERVED6[0x850 - 0x844]; - FWK_RW uint32_t CLUSCLK_CTRL; - FWK_RW uint32_t CLUSCLK_DIV1; - uint8_t RESERVED7[0x860 - 0x858]; - struct coreclk_reg CORECLK[8]; - uint8_t RESERVED8[0xA00 - 0x8E0]; - FWK_R uint32_t CLKFORCE_STATUS; - FWK_W uint32_t CLKFORCE_SET; - FWK_W uint32_t CLKFORCE_CLR; - uint8_t RESERVED9[0xB00 - 0xA0C]; - FWK_R uint32_t NERRIQ_INT_STATUS; - FWK_R uint32_t NFAULTIQ_INT_STATUS; - uint8_t RESERVED10[0xFB4 - 0xB08]; - FWK_R uint32_t CAP3; - FWK_R uint32_t CAP2; - FWK_R uint32_t CAP; - FWK_R uint32_t PCL_CONFIG; - uint8_t RESERVED11[0xFD0 - 0xFC4]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; + uint8_t RESERVED1[0x800 - 0x110]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED2[0x810 - 0x808]; + FWK_RW uint32_t PCLK_CTRL; + uint8_t RESERVED3[0x820 - 0x814]; + FWK_RW uint32_t DBGCLK_CTRL; + FWK_RW uint32_t DBGCLK_DIV1; + uint8_t RESERVED4[0x830 - 0x828]; + FWK_RW uint32_t GICCLK_CTRL; + uint8_t RESERVED5[0x840 - 0x834]; + FWK_RW uint32_t AMBACLK_CTRL; + uint8_t RESERVED6[0x850 - 0x844]; + FWK_RW uint32_t CLUSCLK_CTRL; + FWK_RW uint32_t CLUSCLK_DIV1; + uint8_t RESERVED7[0x860 - 0x858]; + struct coreclk_reg CORECLK[8]; + uint8_t RESERVED8[0xA00 - 0x8E0]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB00 - 0xA0C]; + FWK_R uint32_t NERRIQ_INT_STATUS; + FWK_R uint32_t NFAULTIQ_INT_STATUS; + uint8_t RESERVED10[0xFB4 - 0xB08]; + FWK_R uint32_t CAP3; + FWK_R uint32_t CAP2; + FWK_R uint32_t CAP; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; }; -#define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *) SCP_PIK_CLUSTER_BASE(IDX)) +#define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *)SCP_PIK_CLUSTER_BASE(IDX)) -#endif /* CPU_PIK_H */ +#endif /* CPU_PIK_H */ diff --git a/product/tc0/include/dpu_pik.h b/product/tc0/include/dpu_pik.h index bce45dbb..25af0404 100644 --- a/product/tc0/include/dpu_pik.h +++ b/product/tc0/include/dpu_pik.h @@ -18,31 +18,31 @@ * \brief DPU PIK register definitions */ struct pik_dpu_reg { - FWK_R uint8_t RESERVED0[0x830]; - FWK_RW uint32_t ACLKDP_CTRL; - FWK_RW uint32_t ACLKDP_DIV1; - FWK_RW uint32_t ACLKDP_DIV2; - uint8_t RESERVED3[0xA00 - 0x83C]; - FWK_R uint32_t CLKFORCE_STATUS; - FWK_W uint32_t CLKFORCE_SET; - FWK_W uint32_t CLKFORCE_CLR; - uint8_t RESERVED4[0xFC0 - 0xA0C]; - FWK_RW uint32_t PCL_CONFIG; - uint8_t RESERVED5[0xFD0 - 0xFC4]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; + FWK_R uint8_t RESERVED0[0x830]; + FWK_RW uint32_t ACLKDP_CTRL; + FWK_RW uint32_t ACLKDP_DIV1; + FWK_RW uint32_t ACLKDP_DIV2; + uint8_t RESERVED3[0xA00 - 0x83C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED4[0xFC0 - 0xA0C]; + FWK_RW uint32_t PCL_CONFIG; + uint8_t RESERVED5[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; }; -#define DPU_PIK_PTR ((struct pik_dpu_reg *) SCP_PIK_DPU_BASE) +#define DPU_PIK_PTR ((struct pik_dpu_reg *)SCP_PIK_DPU_BASE) -#endif /* DPU_PIK_H */ +#endif /* DPU_PIK_H */ diff --git a/product/tc0/include/scp_css_mmap.h b/product/tc0/include/scp_css_mmap.h index f9f7975b..301c4d43 100644 --- a/product/tc0/include/scp_css_mmap.h +++ b/product/tc0/include/scp_css_mmap.h @@ -10,35 +10,32 @@ #include "scp_mmap.h" -#define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000) +#define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000) -#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000) -#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) -#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) -#define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) -#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000) +#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000) +#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) +#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) +#define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) +#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000) -#define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) -#define SCP_PIK_CLUSTER_BASE(n) ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ - + 0x60000) + ((n) * 0x20000)) -#define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ - + 0x40000) +#define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) +#define SCP_PIK_CLUSTER_BASE(n) \ + ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x60000) + ((n)*0x20000)) +#define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x40000) -#define SCP_PIK_DPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \ - + 0x860000) +#define SCP_PIK_DPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x860000) -#define SCP_PPU_CLUSTER_BASE(n) (SCP_PIK_CLUSTER_BASE((n)) + 0x1000) -#define SCP_PPU_CORE_BASE(n, m) (SCP_PPU_CLUSTER_BASE((n)) + \ - ((m) + 1) * 0x1000) +#define SCP_PPU_CLUSTER_BASE(n) (SCP_PIK_CLUSTER_BASE((n)) + 0x1000) +#define SCP_PPU_CORE_BASE(n, m) (SCP_PPU_CLUSTER_BASE((n)) + ((m) + 1) * 0x1000) -#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000) -#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000) +#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000) +#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000) -#define SCP_PPU_BASE(n) (SCP_PIK_CLUSTER_BASE(n) + 0x2000) +#define SCP_PPU_BASE(n) (SCP_PIK_CLUSTER_BASE(n) + 0x2000) -#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x00000) -#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x10000) -#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x400000) -#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x410000) +#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x00000) +#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x10000) +#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x400000) +#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x410000) #endif /* SCP_CSS_MMAP_H */ diff --git a/product/tc0/include/scp_mmap.h b/product/tc0/include/scp_mmap.h index e048ce7a..68bc7ad1 100644 --- a/product/tc0/include/scp_mmap.h +++ b/product/tc0/include/scp_mmap.h @@ -8,13 +8,13 @@ #ifndef SCP_MMAP_H #define SCP_MMAP_H -#define SCP_BOOT_ROM_BASE 0x00000000 -#define SCP_ITC_RAM_BASE 0x00800000 -#define SCP_DTC_RAM_BASE 0x20000000 -#define SCP_SOC_EXPANSION3_BASE 0x40000000 -#define SCP_PERIPHERAL_BASE 0x44000000 +#define SCP_BOOT_ROM_BASE 0x00000000 +#define SCP_ITC_RAM_BASE 0x00800000 +#define SCP_DTC_RAM_BASE 0x20000000 +#define SCP_SOC_EXPANSION3_BASE 0x40000000 +#define SCP_PERIPHERAL_BASE 0x44000000 #define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE 0x50000000 -#define SCP_SYSTEM_ACCESS_PORT0_BASE 0x60000000 -#define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 +#define SCP_SYSTEM_ACCESS_PORT0_BASE 0x60000000 +#define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 #endif /* SCP_MMAP_H */ diff --git a/product/tc0/include/scp_pik.h b/product/tc0/include/scp_pik.h index a90efda9..1a6df42c 100644 --- a/product/tc0/include/scp_pik.h +++ b/product/tc0/include/scp_pik.h @@ -21,88 +21,87 @@ * \brief SCP PIK register definitions */ struct pik_scp_reg { - uint8_t RESERVED0[0x10 - 0x0]; - FWK_RW uint32_t RESET_SYNDROME; - uint8_t RESERVED1[0x20 - 0x14]; - FWK_RW uint32_t SURVIVAL_RESET_STATUS; - uint8_t RESERVED2[0x34 - 0x24]; - FWK_RW uint32_t ADDR_TRANS; - FWK_RW uint32_t DBG_ADDR_TRANS; - uint8_t RESERVED3[0x40 - 0x3C]; - FWK_RW uint32_t WS1_TIMER_MATCH; - FWK_RW uint32_t WS1_TIMER_EN; - uint8_t RESERVED4[0x200 - 0x48]; - FWK_R uint32_t SS_RESET_STATUS; - FWK_W uint32_t SS_RESET_SET; - FWK_W uint32_t SS_RESET_CLR; - uint8_t RESERVED5[0x810 - 0x20C]; - FWK_RW uint32_t CORECLK_CTRL; - FWK_RW uint32_t CORECLK_DIV1; - uint8_t RESERVED6[0x820 - 0x818]; - FWK_RW uint32_t ACLK_CTRL; - FWK_RW uint32_t ACLK_DIV1; - uint8_t RESERVED7[0x830 - 0x828]; - FWK_RW uint32_t GTSYNCCLK_CTRL; - FWK_RW uint32_t GTSYNCCLK_DIV1; - uint8_t RESERVED8[0xA10 - 0x838]; - FWK_R uint32_t PLL_STATUS[17]; - uint8_t RESERVED9[0xA60 - 0xA54]; - FWK_R uint32_t CONS_MMUTCU_INT_STATUS; - FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; - FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; - FWK_W uint32_t CONS_MMUTCU_INT_CLR; - FWK_W uint32_t CONS_MMUTBU_INT_CLR0; - FWK_W uint32_t CONS_MMUTBU_INT_CLR1; - uint8_t RESERVED10[0xB00 - 0xA78]; - FWK_R uint32_t MHU_NS_INT_STATUS; - FWK_R uint32_t MHU_S_INT_STATUS; - uint8_t RESERVED11[0xB20 - 0xB08]; - FWK_R uint32_t CPU_PPU_INT_STATUS[8]; - FWK_R uint32_t CLUS_PPU_INT_STATUS; - uint8_t RESERVED12[0xB60 - 0xB44]; - FWK_R uint32_t TIMER_INT_STATUS[8]; - FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; - uint8_t RESERVED13[0xBC0 - 0xBA0]; - FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; - uint8_t RESERVED14[0xBF0 - 0xBE0]; - FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS; - FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS; - uint8_t RESERVED15[0xC00 - 0xBF8]; - FWK_R uint32_t CLUS_FAULT_INT_STATUS; - uint8_t RESERVED16[0xC30 - 0xC04]; - FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS; - uint8_t RESERVED17[0xD00 - 0xC34]; - FWK_R uint32_t DMC0_4_INT_STATUS; - FWK_R uint32_t DMC1_5_INT_STATUS; - FWK_R uint32_t DMC2_6_INT_STATUS; - FWK_R uint32_t DMC3_7_INT_STATUS; - uint8_t RESERVED18[0xFC0 - 0xD10]; - FWK_R uint32_t PCL_CFG; - uint8_t RESERVED19[0xFD0 - 0xFC4]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0x830 - 0x828]; + FWK_RW uint32_t GTSYNCCLK_CTRL; + FWK_RW uint32_t GTSYNCCLK_DIV1; + uint8_t RESERVED8[0xA10 - 0x838]; + FWK_R uint32_t PLL_STATUS[17]; + uint8_t RESERVED9[0xA60 - 0xA54]; + FWK_R uint32_t CONS_MMUTCU_INT_STATUS; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; + FWK_W uint32_t CONS_MMUTCU_INT_CLR; + FWK_W uint32_t CONS_MMUTBU_INT_CLR0; + FWK_W uint32_t CONS_MMUTBU_INT_CLR1; + uint8_t RESERVED10[0xB00 - 0xA78]; + FWK_R uint32_t MHU_NS_INT_STATUS; + FWK_R uint32_t MHU_S_INT_STATUS; + uint8_t RESERVED11[0xB20 - 0xB08]; + FWK_R uint32_t CPU_PPU_INT_STATUS[8]; + FWK_R uint32_t CLUS_PPU_INT_STATUS; + uint8_t RESERVED12[0xB60 - 0xB44]; + FWK_R uint32_t TIMER_INT_STATUS[8]; + FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; + uint8_t RESERVED13[0xBC0 - 0xBA0]; + FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; + uint8_t RESERVED14[0xBF0 - 0xBE0]; + FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS; + FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS; + uint8_t RESERVED15[0xC00 - 0xBF8]; + FWK_R uint32_t CLUS_FAULT_INT_STATUS; + uint8_t RESERVED16[0xC30 - 0xC04]; + FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS; + uint8_t RESERVED17[0xD00 - 0xC34]; + FWK_R uint32_t DMC0_4_INT_STATUS; + FWK_R uint32_t DMC1_5_INT_STATUS; + FWK_R uint32_t DMC2_6_INT_STATUS; + FWK_R uint32_t DMC3_7_INT_STATUS; + uint8_t RESERVED18[0xFC0 - 0xD10]; + FWK_R uint32_t PCL_CFG; + uint8_t RESERVED19[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; }; -#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) -#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) -#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) -#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) -#define PLL_STATUS_0_DISPLAYPLLLOCK UINT32_C(0x00000040) +#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) +#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) +#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) +#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) +#define PLL_STATUS_0_DISPLAYPLLLOCK UINT32_C(0x00000040) - -#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) +#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) /* Pointer to SCP PIK */ -#define SCP_PIK_PTR ((struct pik_scp_reg *) SCP_PIK_SCP_BASE) +#define SCP_PIK_PTR ((struct pik_scp_reg *)SCP_PIK_SCP_BASE) -#endif /* SCP_PIK_H */ +#endif /* SCP_PIK_H */ diff --git a/product/tc0/include/scp_soc_mmap.h b/product/tc0/include/scp_soc_mmap.h index e59924c3..433f9092 100644 --- a/product/tc0/include/scp_soc_mmap.h +++ b/product/tc0/include/scp_soc_mmap.h @@ -10,17 +10,17 @@ #include "scp_mmap.h" -#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) +#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) -#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) -#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014) -#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018) -#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C) -#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) +#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) +#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014) +#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018) +#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C) +#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) -#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) -#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) -#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) -#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) +#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) +#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) +#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) +#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) #endif /* SCP_SOC_MMAP_H */ diff --git a/product/tc0/include/scp_software_mmap.h b/product/tc0/include/scp_software_mmap.h index 12d75406..93eefe65 100644 --- a/product/tc0/include/scp_software_mmap.h +++ b/product/tc0/include/scp_software_mmap.h @@ -8,51 +8,46 @@ #ifndef SCP_SOFTWARE_MMAP_H #define SCP_SOFTWARE_MMAP_H - #include "scp_soc_mmap.h" #include <fwk_macros.h> /* SCP ROM and RAM firmware size loaded on main memory */ -#define SCP_BOOT_ROM_SIZE (64 * 1024) -#define SCP_DTC_RAM_SIZE (256 * 1024) -#define SCP_ITC_RAM_SIZE (256 * 1024) +#define SCP_BOOT_ROM_SIZE (64 * 1024) +#define SCP_DTC_RAM_SIZE (256 * 1024) +#define SCP_ITC_RAM_SIZE (256 * 1024) /* SCP trusted and non-trusted RAM base address */ -#define SCP_TRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \ - 0x04000000) -#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \ - 0x06000000) +#define SCP_TRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x04000000) +#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x06000000) /* Secure Shared memory between AP and SCP */ -#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE) -#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB) +#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE) +#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB) /* Non-secure Shared memory between AP and SCP */ -#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE) -#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB) +#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE) +#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB) /* AP Context Area */ -#define SCP_AP_CONTEXT_BASE (SCP_AP_SHARED_SECURE_BASE + \ - SCP_AP_SHARED_SECURE_SIZE - \ - SCP_AP_CONTEXT_SIZE) -#define SCP_AP_CONTEXT_SIZE (64) +#define SCP_AP_CONTEXT_BASE \ + (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \ + SCP_AP_CONTEXT_SIZE) +#define SCP_AP_CONTEXT_SIZE (64) /* SDS Memory Region */ -#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) -#define SCP_SDS_MEM_SIZE (3520) +#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) +#define SCP_SDS_MEM_SIZE (3520) /* SCMI Secure Payload Areas */ -#define SCP_SCMI_PAYLOAD_SIZE (128) -#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + \ - SCP_SDS_MEM_SIZE) -#define SCP_SCMI_PAYLOAD_S_P2A_BASE (SCP_SCMI_PAYLOAD_S_A2P_BASE + \ - SCP_SCMI_PAYLOAD_SIZE) +#define SCP_SCMI_PAYLOAD_SIZE (128) +#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE) +#define SCP_SCMI_PAYLOAD_S_P2A_BASE \ + (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) /* SCMI Non-Secure Payload Areas */ -#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE) -#define SCP_SCMI_PAYLOAD_NS_P2A_BASE (SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ - SCP_SCMI_PAYLOAD_SIZE) - +#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE) +#define SCP_SCMI_PAYLOAD_NS_P2A_BASE \ + (SCP_SCMI_PAYLOAD_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) #endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/tc0/include/system_pik.h b/product/tc0/include/system_pik.h index d83bd1de..495d0af7 100644 --- a/product/tc0/include/system_pik.h +++ b/product/tc0/include/system_pik.h @@ -18,62 +18,62 @@ * \brief TCU clock register definitions */ struct tcuclk_ctrl_reg { - FWK_RW uint32_t TCUCLK_CTRL; - FWK_RW uint32_t TCUCLK_DIV1; + FWK_RW uint32_t TCUCLK_CTRL; + FWK_RW uint32_t TCUCLK_DIV1; }; /*! * \brief System PIK register definitions */ struct pik_system_reg { - uint8_t RESERVED0[0x800 - 0x0]; - FWK_RW uint32_t PPUCLK_CTRL; - FWK_RW uint32_t PPUCLK_DIV1; - uint8_t RESERVED1[0x820 - 0x808]; - FWK_RW uint32_t INTCLK_CTRL; - FWK_RW uint32_t INTCLK_DIV1; - uint8_t RESERVED2[0x830 - 0x828]; - struct tcuclk_ctrl_reg TCUCLK[4]; - FWK_RW uint32_t GICCLK_CTRL; - FWK_RW uint32_t GICCLK_DIV1; - uint8_t RESERVED3[0x860 - 0x858]; - FWK_RW uint32_t PCLKSCP_CTRL; - FWK_RW uint32_t PCLKSCP_DIV1; - uint8_t RESERVED4[0x870 - 0x868]; - FWK_RW uint32_t SYSPERCLK_CTRL; - FWK_RW uint32_t SYSPERCLK_DIV1; - uint8_t RESERVED5[0x880 - 0x878]; - FWK_RW uint32_t DMCCLK_CTRL; - FWK_RW uint32_t DMCCLK_DIV1; - uint8_t RESERVED6[0x890 - 0x888]; - FWK_RW uint32_t SYSPCLKDBG_CTRL; - FWK_RW uint32_t SYSPCLKDBG_DIV1; - uint8_t RESERVED7[0x8A0 - 0x898]; - FWK_RW uint32_t UARTCLK_CTRL; - FWK_RW uint32_t UARTCLK_DIV1; - uint8_t RESERVED8[0xA00 - 0x8A8]; - FWK_R uint32_t CLKFORCE_STATUS; - FWK_W uint32_t CLKFORCE_SET; - FWK_W uint32_t CLKFORCE_CLR; - uint8_t RESERVED9[0xB0C - 0xA0C]; - FWK_RW uint32_t SYSTOP_RST_DLY; - uint8_t RESERVED10[0xFC0 - 0xB10]; - FWK_R uint32_t PCL_CONFIG; - uint8_t RESERVED11[0xFD0 - 0xFC4]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; + uint8_t RESERVED0[0x800 - 0x0]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED1[0x820 - 0x808]; + FWK_RW uint32_t INTCLK_CTRL; + FWK_RW uint32_t INTCLK_DIV1; + uint8_t RESERVED2[0x830 - 0x828]; + struct tcuclk_ctrl_reg TCUCLK[4]; + FWK_RW uint32_t GICCLK_CTRL; + FWK_RW uint32_t GICCLK_DIV1; + uint8_t RESERVED3[0x860 - 0x858]; + FWK_RW uint32_t PCLKSCP_CTRL; + FWK_RW uint32_t PCLKSCP_DIV1; + uint8_t RESERVED4[0x870 - 0x868]; + FWK_RW uint32_t SYSPERCLK_CTRL; + FWK_RW uint32_t SYSPERCLK_DIV1; + uint8_t RESERVED5[0x880 - 0x878]; + FWK_RW uint32_t DMCCLK_CTRL; + FWK_RW uint32_t DMCCLK_DIV1; + uint8_t RESERVED6[0x890 - 0x888]; + FWK_RW uint32_t SYSPCLKDBG_CTRL; + FWK_RW uint32_t SYSPCLKDBG_DIV1; + uint8_t RESERVED7[0x8A0 - 0x898]; + FWK_RW uint32_t UARTCLK_CTRL; + FWK_RW uint32_t UARTCLK_DIV1; + uint8_t RESERVED8[0xA00 - 0x8A8]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB0C - 0xA0C]; + FWK_RW uint32_t SYSTOP_RST_DLY; + uint8_t RESERVED10[0xFC0 - 0xB10]; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; }; -#define SYSTEM_PIK_PTR ((struct pik_system_reg *) SCP_PIK_SYSTEM_BASE) +#define SYSTEM_PIK_PTR ((struct pik_system_reg *)SCP_PIK_SYSTEM_BASE) -#endif /* SYSTEM_PIK_H */ +#endif /* SYSTEM_PIK_H */ diff --git a/product/tc0/include/tc0_core.h b/product/tc0/include/tc0_core.h index 508e3883..493086e0 100644 --- a/product/tc0/include/tc0_core.h +++ b/product/tc0/include/tc0_core.h @@ -12,8 +12,8 @@ #define TC0_CORE_PER_CLUSTER_MAX 4 -#define CORES_PER_CLUSTER 4 -#define NUMBER_OF_CLUSTERS 1 +#define CORES_PER_CLUSTER 4 +#define NUMBER_OF_CLUSTERS 1 static inline unsigned int tc0_core_get_cluster_count(void) { @@ -31,7 +31,7 @@ static inline unsigned int tc0_core_get_core_per_cluster_count( static inline unsigned int tc0_core_get_core_count(void) { return tc0_core_get_core_per_cluster_count(0) * - tc0_core_get_cluster_count(); + tc0_core_get_cluster_count(); } #endif /* TC0_CORE_H */ diff --git a/product/tc0/include/tc0_power_domain.h b/product/tc0/include/tc0_power_domain.h index f7ef2363..6eab1612 100644 --- a/product/tc0/include/tc0_power_domain.h +++ b/product/tc0/include/tc0_power_domain.h @@ -11,15 +11,10 @@ #include <mod_power_domain.h> /*! Mask for the cluster valid power states */ -#define TC0_CLUSTER_VALID_STATE_MASK ( \ - MOD_PD_STATE_OFF_MASK | \ - MOD_PD_STATE_ON_MASK \ - ) +#define TC0_CLUSTER_VALID_STATE_MASK \ + (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) /*! Mask for the core valid power states */ -#define TC0_CORE_VALID_STATE_MASK ( \ - MOD_PD_STATE_OFF_MASK | \ - MOD_PD_STATE_ON_MASK \ - ) +#define TC0_CORE_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) #endif /* TC0_POWER_DOMAIN_H */ diff --git a/product/tc0/include/tc0_sds.h b/product/tc0/include/tc0_sds.h index e8d9ae25..ccf0d864 100644 --- a/product/tc0/include/tc0_sds.h +++ b/product/tc0/include/tc0_sds.h @@ -19,44 +19,41 @@ enum tc0_sds_struct_id { TC0_SDS_BOOTLOADER = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), }; -enum tc0_sds_region_idx { - TC0_SDS_REGION_SECURE, - TC0_SDS_REGION_COUNT -}; +enum tc0_sds_region_idx { TC0_SDS_REGION_SECURE, TC0_SDS_REGION_COUNT }; /* * Structure sizes. */ -#define TC0_SDS_CPU_INFO_SIZE 4 +#define TC0_SDS_CPU_INFO_SIZE 4 #define TC0_SDS_FEATURE_AVAILABILITY_SIZE 4 -#define TC0_SDS_BOOTLOADER_SIZE 12 +#define TC0_SDS_BOOTLOADER_SIZE 12 /* * Field masks and offsets for TC0_SDS_AP_CPU_INFO structure. */ -#define TC0_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF -#define TC0_SDS_CPU_INFO_PRIMARY_POS 0 +#define TC0_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF +#define TC0_SDS_CPU_INFO_PRIMARY_POS 0 /* * Field masks and offsets for TC0_SDS_FEATURE_AVAILABILITY structure. */ -#define TC0_SDS_FEATURE_FIRMWARE_MASK 0x1 -#define TC0_SDS_FEATURE_DMC_MASK 0x2 -#define TC0_SDS_FEATURE_MESSAGING_MASK 0x4 +#define TC0_SDS_FEATURE_FIRMWARE_MASK 0x1 +#define TC0_SDS_FEATURE_DMC_MASK 0x2 +#define TC0_SDS_FEATURE_MESSAGING_MASK 0x4 -#define TC0_SDS_FEATURE_FIRMWARE_POS 0 -#define TC0_SDS_FEATURE_DMC_POS 1 -#define TC0_SDS_FEATURE_MESSAGING_POS 2 +#define TC0_SDS_FEATURE_FIRMWARE_POS 0 +#define TC0_SDS_FEATURE_DMC_POS 1 +#define TC0_SDS_FEATURE_MESSAGING_POS 2 /* * Field masks and offsets for the TC0_SDS_BOOTLOADER structure. */ -#define TC0_SDS_BOOTLOADER_VALID_MASK 0x1 -#define TC0_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF -#define TC0_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF +#define TC0_SDS_BOOTLOADER_VALID_MASK 0x1 +#define TC0_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF +#define TC0_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF -#define TC0_SDS_BOOTLOADER_VALID_POS 0 -#define TC0_SDS_BOOTLOADER_OFFSET_POS 0 -#define TC0_SDS_BOOTLOADER_SIZE_POS 0 +#define TC0_SDS_BOOTLOADER_VALID_POS 0 +#define TC0_SDS_BOOTLOADER_OFFSET_POS 0 +#define TC0_SDS_BOOTLOADER_SIZE_POS 0 #endif /* TC0_SDS_H */ diff --git a/product/tc0/module/tc0_system/src/mod_tc0_system.c b/product/tc0/module/tc0_system/src/mod_tc0_system.c index cfbb3928..e375f6f4 100644 --- a/product/tc0/module/tc0_system/src/mod_tc0_system.c +++ b/product/tc0/module/tc0_system/src/mod_tc0_system.c @@ -63,9 +63,9 @@ struct tc0_system_isr { static struct tc0_system_ctx tc0_system_ctx; const struct fwk_module_config config_tc0_system = { 0 }; -static const uint32_t feature_flags = (TC0_SDS_FEATURE_FIRMWARE_MASK | - TC0_SDS_FEATURE_DMC_MASK | - TC0_SDS_FEATURE_MESSAGING_MASK); +static const uint32_t feature_flags = + (TC0_SDS_FEATURE_FIRMWARE_MASK | TC0_SDS_FEATURE_DMC_MASK | + TC0_SDS_FEATURE_MESSAGING_MASK); static fwk_id_t sds_feature_availability_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, 1); @@ -112,34 +112,26 @@ static void ppu_cores_isr(unsigned int first, uint32_t status) static void ppu_cores_isr_0(void) { - ppu_cores_isr(0, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[0]); - ppu_cores_isr(128, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[4]); + ppu_cores_isr(0, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[0]); + ppu_cores_isr(128, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[4]); } static void ppu_cores_isr_1(void) { - ppu_cores_isr(32, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[1]); - ppu_cores_isr(160, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[5]); + ppu_cores_isr(32, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[1]); + ppu_cores_isr(160, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[5]); } static void ppu_cores_isr_2(void) { - ppu_cores_isr(64, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[2]); - ppu_cores_isr(192, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[6]); + ppu_cores_isr(64, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[2]); + ppu_cores_isr(192, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[6]); } static void ppu_cores_isr_3(void) { - ppu_cores_isr(96, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[3]); - ppu_cores_isr(224, - tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[7]); + ppu_cores_isr(96, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[3]); + ppu_cores_isr(224, tc0_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[7]); } static void ppu_clusters_isr(void) @@ -150,9 +142,8 @@ static void ppu_clusters_isr(void) while (status != 0) { cluster_idx = __builtin_ctz(status); - tc0_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler( - FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, - tc0_core_get_core_count() + cluster_idx)); + tc0_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler(FWK_ID_ELEMENT( + FWK_MODULE_IDX_PPU_V1, tc0_core_get_core_count() + cluster_idx)); status &= ~(1 << cluster_idx); } @@ -163,24 +154,18 @@ static void ppu_clusters_isr(void) */ static struct tc0_system_isr isrs[] = { - [0] = { .interrupt = PPU_CORES0_IRQ, - .handler = ppu_cores_isr_0 }, - [1] = { .interrupt = PPU_CORES1_IRQ, - .handler = ppu_cores_isr_1 }, - [2] = { .interrupt = PPU_CORES2_IRQ, - .handler = ppu_cores_isr_2 }, - [3] = { .interrupt = PPU_CORES3_IRQ, - .handler = ppu_cores_isr_3 }, - [4] = { .interrupt = PPU_CLUSTERS_IRQ, - .handler = ppu_clusters_isr }, + [0] = { .interrupt = PPU_CORES0_IRQ, .handler = ppu_cores_isr_0 }, + [1] = { .interrupt = PPU_CORES1_IRQ, .handler = ppu_cores_isr_1 }, + [2] = { .interrupt = PPU_CORES2_IRQ, .handler = ppu_cores_isr_2 }, + [3] = { .interrupt = PPU_CORES3_IRQ, .handler = ppu_cores_isr_3 }, + [4] = { .interrupt = PPU_CLUSTERS_IRQ, .handler = ppu_clusters_isr }, }; /* * System power's driver API */ -static int tc0_system_shutdown( - enum mod_pd_system_shutdown system_shutdown) +static int tc0_system_shutdown(enum mod_pd_system_shutdown system_shutdown) { NVIC_SystemReset(); @@ -189,14 +174,15 @@ static int tc0_system_shutdown( static const struct mod_system_power_driver_api tc0_system_system_power_driver_api = { - .system_shutdown = tc0_system_shutdown, -}; + .system_shutdown = tc0_system_shutdown, + }; /* * Functions fulfilling the framework's module interface */ -static int tc0_system_mod_init(fwk_id_t module_id, +static int tc0_system_mod_init( + fwk_id_t module_id, unsigned int unused, const void *unused2) { @@ -211,8 +197,7 @@ static int tc0_system_mod_init(fwk_id_t module_id, return status; } - tc0_system_ctx.pik_scp_reg = - (struct pik_scp_reg *)SCP_PIK_SCP_BASE; + tc0_system_ctx.pik_scp_reg = (struct pik_scp_reg *)SCP_PIK_SCP_BASE; return FWK_SUCCESS; } @@ -224,25 +209,31 @@ static int tc0_system_bind(fwk_id_t id, unsigned int round) if (round > 0) return FWK_SUCCESS; - status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), &tc0_system_ctx.mod_pd_restricted_api); if (status != FWK_SUCCESS) return status; - status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), + status = fwk_module_bind( + FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR), &tc0_system_ctx.ppu_v1_isr_api); if (status != FWK_SUCCESS) return status; - return fwk_module_bind(fwk_module_id_sds, + return fwk_module_bind( + fwk_module_id_sds, FWK_ID_API(FWK_MODULE_IDX_SDS, 0), &tc0_system_ctx.sds_api); } -static int tc0_system_process_bind_request(fwk_id_t requester_id, - fwk_id_t pd_id, fwk_id_t api_id, const void **api) +static int tc0_system_process_bind_request( + fwk_id_t requester_id, + fwk_id_t pd_id, + fwk_id_t api_id, + const void **api) { *api = &tc0_system_system_power_driver_api; return FWK_SUCCESS; @@ -262,8 +253,8 @@ static int tc0_system_start(fwk_id_t id) for (i = 0; i < FWK_ARRAY_SIZE(scmi_notification_table); i++) { status = fwk_notification_subscribe( mod_scmi_notification_id_initialized, - fwk_id_build_element_id(fwk_module_id_scmi, - scmi_notification_table[i]), + fwk_id_build_element_id( + fwk_module_id_scmi, scmi_notification_table[i]), id); if (status != FWK_SUCCESS) return status; @@ -274,9 +265,7 @@ static int tc0_system_start(fwk_id_t id) * PSCI agent know that the SCMI stack is initialized. */ status = fwk_notification_subscribe( - mod_sds_notification_id_initialized, - fwk_module_id_sds, - id); + mod_sds_notification_id_initialized, fwk_module_id_sds, id); if (status != FWK_SUCCESS) return status; @@ -291,7 +280,8 @@ static int tc0_system_start(fwk_id_t id) MOD_PD_STATE_OFF)); } -int tc0_system_process_notification(const struct fwk_event *event, +int tc0_system_process_notification( + const struct fwk_event *event, struct fwk_event *resp_event) { static unsigned int scmi_notification_count = 0; @@ -299,11 +289,10 @@ int tc0_system_process_notification(const struct fwk_event *event, fwk_assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); - if (fwk_id_is_equal(event->id, - mod_scmi_notification_id_initialized)) { + if (fwk_id_is_equal(event->id, mod_scmi_notification_id_initialized)) { scmi_notification_count++; - } else if (fwk_id_is_equal(event->id, - mod_sds_notification_id_initialized)) { + } else if (fwk_id_is_equal( + event->id, mod_sds_notification_id_initialized)) { sds_notification_received = true; } else return FWK_E_PARAM; diff --git a/product/tc0/scp_ramfw/RTX_Config.h b/product/tc0/scp_ramfw/RTX_Config.h index 35ce37d1..2fae6ea2 100644 --- a/product/tc0/scp_ramfw/RTX_Config.h +++ b/product/tc0/scp_ramfw/RTX_Config.h @@ -14,43 +14,43 @@ #define RTX_CONFIG_H_ /* System */ -#define OS_DYNAMIC_MEM_SIZE 0 -#define OS_TICK_FREQ 1000 /* Hz */ -#define OS_ROBIN_ENABLE 0 -#define OS_ROBIN_TIMEOUT 0 -#define OS_ISR_FIFO_QUEUE 16 +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 /* Thread */ -#define OS_THREAD_OBJ_MEM 0 -#define OS_THREAD_NUM 1 -#define OS_THREAD_DEF_STACK_NUM 0 -#define OS_THREAD_USER_STACK_SIZE 0 -#define OS_STACK_SIZE 200 -#define OS_IDLE_THREAD_STACK_SIZE 200 -#define OS_STACK_CHECK 1 -#define OS_STACK_WATERMARK 0 -#define OS_PRIVILEGE_MODE 1 +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 /* Timer */ -#define OS_TIMER_OBJ_MEM 0 -#define OS_TIMER_NUM 1 -#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 #define OS_TIMER_THREAD_STACK_SIZE 200 -#define OS_TIMER_CB_QUEUE 4 +#define OS_TIMER_CB_QUEUE 4 /* Event flags */ -#define OS_EVFLAGS_OBJ_MEM 0 -#define OS_EVFLAGS_NUM 1 +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 -#define OS_MUTEX_OBJ_MEM 0 -#define OS_MUTEX_NUM 1 -#define OS_SEMAPHORE_OBJ_MEM 0 -#define OS_SEMAPHORE_NUM 1 -#define OS_MEMPOOL_OBJ_MEM 0 -#define OS_MEMPOOL_NUM 1 -#define OS_MEMPOOL_DATA_SIZE 0 -#define OS_MSGQUEUE_OBJ_MEM 0 -#define OS_MSGQUEUE_NUM 1 -#define OS_MSGQUEUE_DATA_SIZE 0 +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 #endif /* RTX_CONFIG_H_ */ diff --git a/product/tc0/scp_ramfw/config_armv7m_mpu.c b/product/tc0/scp_ramfw/config_armv7m_mpu.c index cdeeac7a..d4426875 100644 --- a/product/tc0/scp_ramfw/config_armv7m_mpu.c +++ b/product/tc0/scp_ramfw/config_armv7m_mpu.c @@ -16,35 +16,75 @@ #include <fmw_cmsis.h> static const ARM_MPU_Region_t regions[] = { - { /* 0x0000_0000 - 0xFFFF_FFFF */ + { + /* 0x0000_0000 - 0xFFFF_FFFF */ .RBAR = ARM_MPU_RBAR(0, 0x00000000), .RASR = ARM_MPU_RASR( - 1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB), + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 0, + 1, + 0, + ARM_MPU_REGION_SIZE_4GB), }, - { /* 0x0080_0000 - 0x00FF_FFFF */ + { + /* 0x0080_0000 - 0x00FF_FFFF */ .RBAR = ARM_MPU_RBAR(1, SCP_ITC_RAM_BASE), .RASR = ARM_MPU_RASR( - 0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB), + 0, + ARM_MPU_AP_PRO, + 0, + 0, + 1, + 0, + 0, + ARM_MPU_REGION_SIZE_256KB), }, - { /* 0x2000_0000 - 0x20FF_FFFF */ + { + /* 0x2000_0000 - 0x20FF_FFFF */ .RBAR = ARM_MPU_RBAR(2, SCP_DTC_RAM_BASE), .RASR = ARM_MPU_RASR( - 1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB), + 1, + ARM_MPU_AP_PRIV, + 0, + 0, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256KB), }, - { /* 0xA400_0000 - 0xA400_7FFF*/ + { + /* 0xA400_0000 - 0xA400_7FFF*/ .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE), .RASR = ARM_MPU_RASR( - 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_4KB), + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_4KB), }, - { /* 0xA600_0000 - 0xA600_7FFF */ + { + /* 0xA600_0000 - 0xA600_7FFF */ .RBAR = ARM_MPU_RBAR(4, SCP_NONTRUSTED_RAM_BASE), .RASR = ARM_MPU_RASR( - 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), + 1, + ARM_MPU_AP_PRIV, + 0, + 1, + 1, + 1, + 0, + ARM_MPU_REGION_SIZE_256B), }, }; const struct fwk_module_config config_armv7m_mpu = { - .data = &((struct mod_armv7m_mpu_config) { + .data = &((struct mod_armv7m_mpu_config){ .region_count = FWK_ARRAY_SIZE(regions), .regions = regions, }), diff --git a/product/tc0/scp_ramfw/config_clock.c b/product/tc0/scp_ramfw/config_clock.c index 083f6491..56fc073c 100644 --- a/product/tc0/scp_ramfw/config_clock.c +++ b/product/tc0/scp_ramfw/config_clock.c @@ -19,53 +19,67 @@ #include <fwk_module.h> #include <fwk_module_idx.h> - static const struct fwk_element clock_dev_desc_table[] = { - [CLOCK_IDX_INTERCONNECT] = { - .name = "Interconnect", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, - CLOCK_PIK_IDX_INTERCONNECT), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_CPU_GROUP0] = { - .name = "CPU_GROUP0", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP0), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_DPU] = { - .name = "DPU", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_DPU), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_PIXEL_0] = { - .name = "PIXEL_0", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_PIX0), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - }), - }, - [CLOCK_IDX_PIXEL_1] = { - .name = "PIXEL_1", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_PIX1), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - }), - }, + [CLOCK_IDX_INTERCONNECT] = + { + .name = "Interconnect", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + CLOCK_PIK_IDX_INTERCONNECT), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP0] = + { + .name = "CPU_GROUP0", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_DPU] = + { + .name = "DPU", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_DPU), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_PIXEL_0] = + { + .name = "PIXEL_0", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_PIX0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + }), + }, + [CLOCK_IDX_PIXEL_1] = + { + .name = "PIXEL_1", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_PIX1), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + }), + }, { 0 }, /* Termination description. */ }; diff --git a/product/tc0/scp_ramfw/config_css_clock.c b/product/tc0/scp_ramfw/config_css_clock.c index 5f999c40..e4c90f65 100644 --- a/product/tc0/scp_ramfw/config_css_clock.c +++ b/product/tc0/scp_ramfw/config_css_clock.c @@ -79,48 +79,58 @@ static const fwk_id_t member_table_dpu[] = { }; static const struct fwk_element css_clock_element_table[] = { - [CLOCK_CSS_IDX_CPU_GROUP0] = { - .name = "CPU_GROUP_0", - .data = &((struct mod_css_clock_dev_config) { - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), - .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, - .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU0), - .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_0, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), - .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 2271 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_DPU] = { - .name = "DPU", - .data = &((struct mod_css_clock_dev_config) { - .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED, - .clock_default_source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, - .clock_switching_source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_SYSREFCLK, - .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_DPU), - .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_dpu, - .member_count = FWK_ARRAY_SIZE(member_table_dpu), - .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 600 * FWK_MHZ, - .modulation_supported = false, - }), - }, + [CLOCK_CSS_IDX_CPU_GROUP0] = + { + .name = "CPU_GROUP_0", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + .clock_switching_source = + MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU0), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_0, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2271 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_DPU] = + { + .name = "DPU", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED, + .clock_default_source = + MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, + .clock_switching_source = + MOD_PIK_CLOCK_ACLKDPU_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_DPU), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_dpu, + .member_count = FWK_ARRAY_SIZE(member_table_dpu), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 600 * FWK_MHZ, + .modulation_supported = false, + }), + }, [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ }; -static const struct fwk_element *css_clock_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) { return css_clock_element_table; } diff --git a/product/tc0/scp_ramfw/config_dvfs.c b/product/tc0/scp_ramfw/config_dvfs.c index f509842e..a5f071ea 100644 --- a/product/tc0/scp_ramfw/config_dvfs.c +++ b/product/tc0/scp_ramfw/config_dvfs.c @@ -58,13 +58,12 @@ static const struct mod_dvfs_domain_config cpu_group = { .opps = opps, }; -static const struct fwk_element element_table[] = { - [0] = { - .name = "CPU_GROUP", - .data = &cpu_group, - }, - { 0 } -}; +static const struct fwk_element element_table[] = { [0] = + { + .name = "CPU_GROUP", + .data = &cpu_group, + }, + { 0 } }; static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id) { diff --git a/product/tc0/scp_ramfw/config_gtimer.c b/product/tc0/scp_ramfw/config_gtimer.c index 8845182b..eb063a2c 100644 --- a/product/tc0/scp_ramfw/config_gtimer.c +++ b/product/tc0/scp_ramfw/config_gtimer.c @@ -20,17 +20,15 @@ * Generic timer driver config */ static const struct fwk_element gtimer_dev_table[] = { - [0] = { - .name = "REFCLK", - .data = &((struct mod_gtimer_dev_config) { - .hw_timer = SCP_REFCLK_CNTBASE0_BASE, - .hw_counter = SCP_REFCLK_CNTCTL_BASE, - .control = SCP_REFCLK_CNTCONTROL_BASE, - .frequency = CLOCK_RATE_REFCLK, - .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_INTERCONNECT) - }) - }, + [0] = { .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config){ + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) }) }, [1] = { 0 }, }; diff --git a/product/tc0/scp_ramfw/config_mhu2.c b/product/tc0/scp_ramfw/config_mhu2.c index 00b01b90..fd324802 100644 --- a/product/tc0/scp_ramfw/config_mhu2.c +++ b/product/tc0/scp_ramfw/config_mhu2.c @@ -17,26 +17,30 @@ #include <fmw_cmsis.h> static const struct fwk_element mhu_element_table[] = { - [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0] = { - .name = "MHU_SCP_AP_S", - .sub_element_count = 1, - .data = &((struct mod_mhu2_channel_config) { - .irq = MHU_AP_SEC_IRQ, - .recv = SCP_MHU_SCP_AP_RCV_S_CLUS0, - .send = SCP_MHU_SCP_AP_SND_S_CLUS0, - .channel = 0, - }) - }, - [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0] = { - .name = "MHU_SCP_AP_NS", - .sub_element_count = 1, - .data = &((struct mod_mhu2_channel_config) { - .irq = MHU_AP_NONSEC_IRQ, - .recv = SCP_MHU_SCP_AP_RCV_NS_CLUS0, - .send = SCP_MHU_SCP_AP_SND_NS_CLUS0, - .channel = 0, - }) - }, + [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0] = { .name = "MHU_SCP_AP_S", + .sub_element_count = 1, + .data = &(( + struct + mod_mhu2_channel_config){ + .irq = MHU_AP_SEC_IRQ, + .recv = + SCP_MHU_SCP_AP_RCV_S_CLUS0, + .send = + SCP_MHU_SCP_AP_SND_S_CLUS0, + .channel = 0, + }) }, + [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0] = { .name = "MHU_SCP_AP_NS", + .sub_element_count = 1, + .data = &(( + struct + mod_mhu2_channel_config){ + .irq = MHU_AP_NONSEC_IRQ, + .recv = + SCP_MHU_SCP_AP_RCV_NS_CLUS0, + .send = + SCP_MHU_SCP_AP_SND_NS_CLUS0, + .channel = 0, + }) }, [SCP_TC0_MHU_DEVICE_IDX_COUNT] = { 0 }, }; diff --git a/product/tc0/scp_ramfw/config_pik_clock.c b/product/tc0/scp_ramfw/config_pik_clock.c index 909c0702..f97cf77b 100644 --- a/product/tc0/scp_ramfw/config_pik_clock.c +++ b/product/tc0/scp_ramfw/config_pik_clock.c @@ -196,8 +196,7 @@ static const struct fwk_element pik_clock_element_table[] = { [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ }; -static const struct fwk_element *pik_clock_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) { return pik_clock_element_table; } diff --git a/product/tc0/scp_ramfw/config_pl011.c b/product/tc0/scp_ramfw/config_pl011.c index dad590c6..de69081b 100644 --- a/product/tc0/scp_ramfw/config_pl011.c +++ b/product/tc0/scp_ramfw/config_pl011.c @@ -17,19 +17,20 @@ const struct fwk_module_config config_pl011 = { .elements = FWK_MODULE_STATIC_ELEMENTS({ - [0] = { - .name = "uart", - .data = - &(struct mod_pl011_element_cfg){ - .reg_base = SCP_UART_BASE, - .baud_rate_bps = 115200, - .clock_rate_hz = 24 * FWK_MHZ, - .clock_id = FWK_ID_NONE_INIT, - .pd_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_POWER_DOMAIN, - PD_STATIC_DEV_IDX_SYSTOP), - }, - }, + [0] = + { + .name = "uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + .pd_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + PD_STATIC_DEV_IDX_SYSTOP), + }, + }, [1] = { 0 }, }), diff --git a/product/tc0/scp_ramfw/config_power_domain.c b/product/tc0/scp_ramfw/config_power_domain.c index a6844aa2..60a63d95 100644 --- a/product/tc0/scp_ramfw/config_power_domain.c +++ b/product/tc0/scp_ramfw/config_power_domain.c @@ -31,7 +31,7 @@ /* Mask of the allowed states for the systop power domain */ static const uint32_t systop_allowed_state_mask_table[] = { - [0] = MOD_PD_STATE_ON_MASK + [0] = MOD_PD_STATE_ON_MASK }; /* @@ -50,31 +50,30 @@ static const uint32_t core_pd_allowed_state_mask_table[] = { }; /* Power module specific configuration data (none) */ -static const struct mod_power_domain_config - tc0_power_domain_config = { 0 }; +static const struct mod_power_domain_config tc0_power_domain_config = { 0 }; static struct fwk_element tc0_power_domain_static_element_table[] = { - [PD_STATIC_DEV_IDX_SYSTOP] = { - .name = "SYSTOP", - .data = &((struct mod_power_domain_element_config) { - .attributes.pd_type = MOD_PD_TYPE_SYSTEM, - .parent_idx = PD_STATIC_DEV_IDX_NONE, - .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_POWER, - MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), - .allowed_state_mask_table = systop_allowed_state_mask_table, - .allowed_state_mask_table_size = - FWK_ARRAY_SIZE(systop_allowed_state_mask_table) - }), - }, + [PD_STATIC_DEV_IDX_SYSTOP] = + { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config){ + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .parent_idx = PD_STATIC_DEV_IDX_NONE, + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) }), + }, }; /* * Function definitions with internal linkage */ -static const struct fwk_element *tc0_power_domain_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *tc0_power_domain_get_element_table( + fwk_id_t module_id) { return create_power_domain_element_table( tc0_core_get_core_count(), diff --git a/product/tc0/scp_ramfw/config_ppu_v1.c b/product/tc0/scp_ramfw/config_ppu_v1.c index 9dc013b6..ba475911 100644 --- a/product/tc0/scp_ramfw/config_ppu_v1.c +++ b/product/tc0/scp_ramfw/config_ppu_v1.c @@ -6,8 +6,8 @@ */ #include "config_power_domain.h" -#include "tc0_core.h" #include "scp_css_mmap.h" +#include "tc0_core.h" #include <mod_power_domain.h> #include <mod_ppu_v1.h> @@ -37,22 +37,24 @@ static struct mod_ppu_v1_config ppu_v1_config_data = { }; static struct fwk_element ppu_v1_system_element_table[] = { - [0] = { - .name = "SYS0", - .data = &((struct mod_ppu_v1_pd_config) { - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS0_BASE, - .observer_id = FWK_ID_NONE_INIT, - }), - }, - [1] = { - .name = "SYS1", - .data = &((struct mod_ppu_v1_pd_config) { - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS1_BASE, - .observer_id = FWK_ID_NONE_INIT, - }), - }, + [0] = + { + .name = "SYS0", + .data = &((struct mod_ppu_v1_pd_config){ + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS0_BASE, + .observer_id = FWK_ID_NONE_INIT, + }), + }, + [1] = + { + .name = "SYS1", + .data = &((struct mod_ppu_v1_pd_config){ + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS1_BASE, + .observer_id = FWK_ID_NONE_INIT, + }), + }, }; static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) @@ -75,21 +77,21 @@ static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) * + Number of system power domain descriptors * + 1 terminator descriptor */ - element_table = fwk_mm_calloc(core_count + cluster_count + - FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, + element_table = fwk_mm_calloc( + core_count + cluster_count + + FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, sizeof(struct fwk_element)); if (element_table == NULL) return NULL; - pd_config_table = fwk_mm_calloc(core_count + cluster_count, - sizeof(struct mod_ppu_v1_pd_config)); + pd_config_table = fwk_mm_calloc( + core_count + cluster_count, sizeof(struct mod_ppu_v1_pd_config)); if (pd_config_table == NULL) return NULL; for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { for (core_idx = 0; - core_idx < tc0_core_get_core_per_cluster_count( - cluster_idx); + core_idx < tc0_core_get_core_per_cluster_count(cluster_idx); core_idx++) { element = &element_table[core_element_count]; pd_config = &pd_config_table[core_element_count]; @@ -98,17 +100,20 @@ static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) if (element->name == NULL) return NULL; - snprintf((char *)element->name, PPU_CORE_NAME_SIZE, "CLUS%uCORE%u", - cluster_idx, core_idx); + snprintf( + (char *)element->name, + PPU_CORE_NAME_SIZE, + "CLUS%uCORE%u", + cluster_idx, + core_idx); element->data = pd_config; pd_config->pd_type = MOD_PD_TYPE_CORE; pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(cluster_idx, core_idx); pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->cluster_id = - FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, - (core_count + cluster_idx)); + pd_config->cluster_id = FWK_ID_ELEMENT( + FWK_MODULE_IDX_PPU_V1, (core_count + cluster_idx)); pd_config->observer_id = FWK_ID_NONE; core_element_count++; } @@ -120,8 +125,8 @@ static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) if (element->name == NULL) return NULL; - snprintf((char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS%u", - cluster_idx); + snprintf( + (char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS%u", cluster_idx); element->data = pd_config; @@ -131,9 +136,10 @@ static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) pd_config->observer_id = FWK_ID_NONE; } - memcpy(&element_table[core_count + cluster_count], - ppu_v1_system_element_table, - sizeof(ppu_v1_system_element_table)); + memcpy( + &element_table[core_count + cluster_count], + ppu_v1_system_element_table, + sizeof(ppu_v1_system_element_table)); /* * Configure pd_source_id with the SYSTOP identifier from the power domain diff --git a/product/tc0/scp_ramfw/config_psu.c b/product/tc0/scp_ramfw/config_psu.c index ab3a390a..59f42f54 100644 --- a/product/tc0/scp_ramfw/config_psu.c +++ b/product/tc0/scp_ramfw/config_psu.c @@ -15,11 +15,12 @@ static const struct fwk_element element_table[] = { { .name = "DVFS_GROUP0", - .data = &(const struct mod_psu_element_cfg) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MOCK_PSU, - MOD_MOCK_PSU_API_IDX_DRIVER) - }, + .data = + &(const struct mod_psu_element_cfg){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_DRIVER) }, }, { 0 } }; diff --git a/product/tc0/scp_ramfw/config_resource_perms.c b/product/tc0/scp_ramfw/config_resource_perms.c index af234714..afc0fddf 100644 --- a/product/tc0/scp_ramfw/config_resource_perms.c +++ b/product/tc0/scp_ramfw/config_resource_perms.c @@ -45,47 +45,63 @@ static struct mod_res_agent_protocol_permissions agent_protocol_permissions[] = * protocols, hence message 0x3 maps to bit[0], message 0x4 maps * to bit[1], etc. */ -static struct mod_res_agent_msg_permissions agent_msg_permissions[] = { - [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = { - .messages[MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = 0x0, - }, - [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = { - .messages[MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = - ((1 << (MOD_SCMI_PERF_DOMAIN_ATTRIBUTES - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - /* DESCRIBE_LEVELS is required for some reason ... */ - (0 << (MOD_SCMI_PERF_DESCRIBE_LEVELS - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_LIMITS_SET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_LIMITS_GET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_LEVEL_SET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_LEVEL_GET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_NOTIFY_LIMITS - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_NOTIFY_LEVEL - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 << (MOD_SCMI_PERF_DESCRIBE_FAST_CHANNEL - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES))), - /* Clocks, no access */ - .messages[MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0xff, - .messages[MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, - .messages[MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = 0x0, - }, - }; - +static struct mod_res_agent_msg_permissions + agent_msg_permissions[] = + { + [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = + { + .messages[MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = + 0x0, + .messages[MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = + 0x0, + }, + [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = + { + .messages[MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = + 0x0, + .messages[MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = + ((1 + << (MOD_SCMI_PERF_DOMAIN_ATTRIBUTES - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + /* DESCRIBE_LEVELS is required for some reason ... */ + (0 + << (MOD_SCMI_PERF_DESCRIBE_LEVELS - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LIMITS_SET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LIMITS_GET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LEVEL_SET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_LEVEL_GET - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_NOTIFY_LIMITS - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_NOTIFY_LEVEL - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | + (1 + << (MOD_SCMI_PERF_DESCRIBE_FAST_CHANNEL - + MOD_SCMI_PERF_DOMAIN_ATTRIBUTES))), + /* Clocks, no access */ + .messages[MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0xff, + .messages[MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, + .messages[MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = + 0x0, + }, + }; static struct mod_res_agent_permission agent_permissions = { .agent_protocol_permissions = agent_protocol_permissions, diff --git a/product/tc0/scp_ramfw/config_scmi.c b/product/tc0/scp_ramfw/config_scmi.c index a0007405..21a2d466 100644 --- a/product/tc0/scp_ramfw/config_scmi.c +++ b/product/tc0/scp_ramfw/config_scmi.c @@ -17,38 +17,40 @@ #include <fwk_module_idx.h> static const struct fwk_element service_table[] = { - [SCP_TC0_SCMI_SERVICE_IDX_PSCI] = { - .name = "PSCI", - .data = &((struct mod_scmi_service_config) { - .transport_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SMT, - SCP_TC0_SCMI_SERVICE_IDX_PSCI), - .transport_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SMT, - MOD_SMT_API_IDX_SCMI_TRANSPORT), - .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_SMT, - MOD_SMT_NOTIFICATION_IDX_INITIALIZED), - .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, - .scmi_p2a_id = FWK_ID_NONE_INIT, - }), - }, - [SCP_TC0_SCMI_SERVICE_IDX_OSPM] = { - .name = "OSPM", - .data = &((struct mod_scmi_service_config) { - .transport_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SMT, - SCP_TC0_SCMI_SERVICE_IDX_OSPM), - .transport_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SMT, - MOD_SMT_API_IDX_SCMI_TRANSPORT), - .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_SMT, - MOD_SMT_NOTIFICATION_IDX_INITIALIZED), - .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, - .scmi_p2a_id = FWK_ID_NONE_INIT, - }), - }, + [SCP_TC0_SCMI_SERVICE_IDX_PSCI] = + { + .name = "PSCI", + .data = &((struct mod_scmi_service_config){ + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_TC0_SCMI_SERVICE_IDX_PSCI), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, + [SCP_TC0_SCMI_SERVICE_IDX_OSPM] = + { + .name = "OSPM", + .data = &((struct mod_scmi_service_config){ + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_TC0_SCMI_SERVICE_IDX_OSPM), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, + .scmi_p2a_id = FWK_ID_NONE_INIT, + }), + }, [SCP_TC0_SCMI_SERVICE_IDX_COUNT] = { 0 } }; @@ -58,14 +60,16 @@ static const struct fwk_element *get_service_table(fwk_id_t module_id) } static struct mod_scmi_agent agent_table[] = { - [SCP_SCMI_AGENT_ID_OSPM] = { - .type = SCMI_AGENT_TYPE_OSPM, - .name = "OSPM", - }, - [SCP_SCMI_AGENT_ID_PSCI] = { - .type = SCMI_AGENT_TYPE_PSCI, - .name = "PSCI", - }, + [SCP_SCMI_AGENT_ID_OSPM] = + { + .type = SCMI_AGENT_TYPE_OSPM, + .name = "OSPM", + }, + [SCP_SCMI_AGENT_ID_PSCI] = + { + .type = SCMI_AGENT_TYPE_PSCI, + .name = "PSCI", + }, }; const struct fwk_module_config config_scmi = { diff --git a/product/tc0/scp_ramfw/config_scmi_clock.c b/product/tc0/scp_ramfw/config_scmi_clock.c index 8a38aa75..84b3d381 100644 --- a/product/tc0/scp_ramfw/config_scmi_clock.c +++ b/product/tc0/scp_ramfw/config_scmi_clock.c @@ -18,8 +18,7 @@ static const struct mod_scmi_clock_device agent_device_table_ospm[] = { { /* DPU */ - .element_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_DPU), + .element_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_DPU), }, { /* PIXEL_0 */ @@ -33,17 +32,18 @@ static const struct mod_scmi_clock_device agent_device_table_ospm[] = { }, }; -static const struct mod_scmi_clock_agent - agent_table[SCP_SCMI_AGENT_ID_COUNT] = { - [SCP_SCMI_AGENT_ID_PSCI] = { 0 /* No access */ }, - [SCP_SCMI_AGENT_ID_OSPM] = { - .device_table = agent_device_table_ospm, - .device_count = FWK_ARRAY_SIZE(agent_device_table_ospm), - }, -}; +static const struct mod_scmi_clock_agent agent_table[SCP_SCMI_AGENT_ID_COUNT] = + { + [SCP_SCMI_AGENT_ID_PSCI] = { 0 /* No access */ }, + [SCP_SCMI_AGENT_ID_OSPM] = + { + .device_table = agent_device_table_ospm, + .device_count = FWK_ARRAY_SIZE(agent_device_table_ospm), + }, + }; const struct fwk_module_config config_scmi_clock = { - .data = &((struct mod_scmi_clock_config) { + .data = &((struct mod_scmi_clock_config){ .max_pending_transactions = 0, .agent_table = agent_table, .agent_count = FWK_ARRAY_SIZE(agent_table), diff --git a/product/tc0/scp_ramfw/config_scmi_perf.c b/product/tc0/scp_ramfw/config_scmi_perf.c index 52a9ec98..d2017f81 100644 --- a/product/tc0/scp_ramfw/config_scmi_perf.c +++ b/product/tc0/scp_ramfw/config_scmi_perf.c @@ -14,8 +14,7 @@ #include <stdint.h> static const struct mod_scmi_perf_domain_config domains[] = { - [0] = { - }, + [0] = {}, }; const struct fwk_module_config config_scmi_perf = { diff --git a/product/tc0/scp_ramfw/config_scmi_system_power.c b/product/tc0/scp_ramfw/config_scmi_system_power.c index 20b22582..e5a491ae 100644 --- a/product/tc0/scp_ramfw/config_scmi_system_power.c +++ b/product/tc0/scp_ramfw/config_scmi_system_power.c @@ -11,8 +11,7 @@ #include <fwk_module.h> const struct fwk_module_config config_scmi_system_power = { - .data = &((struct mod_scmi_system_power_config) { + .data = &((struct mod_scmi_system_power_config){ .system_view = MOD_SCMI_SYSTEM_VIEW_FULL, - .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0 - }), + .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0 }), }; diff --git a/product/tc0/scp_ramfw/config_sds.c b/product/tc0/scp_ramfw/config_sds.c index 05694adc..94b3a405 100644 --- a/product/tc0/scp_ramfw/config_sds.c +++ b/product/tc0/scp_ramfw/config_sds.c @@ -6,9 +6,9 @@ */ #include "clock_soc.h" -#include "tc0_sds.h" #include "scp_pik.h" #include "scp_software_mmap.h" +#include "tc0_sds.h" #include <mod_sds.h> @@ -25,27 +25,29 @@ static const uint32_t feature_flags = TC0_SDS_FEATURE_FIRMWARE_MASK; static const struct mod_sds_region_desc sds_module_regions[] = { - [TC0_SDS_REGION_SECURE] = { - .base = (void*)SCP_SDS_MEM_BASE, - .size = SCP_SDS_MEM_SIZE, - }, + [TC0_SDS_REGION_SECURE] = + { + .base = (void *)SCP_SDS_MEM_BASE, + .size = SCP_SDS_MEM_SIZE, + }, }; -static_assert(FWK_ARRAY_SIZE(sds_module_regions) == TC0_SDS_REGION_COUNT, - "Mismatch between number of SDS regions and number of regions " - "provided by the SDS configuration."); +static_assert( + FWK_ARRAY_SIZE(sds_module_regions) == TC0_SDS_REGION_COUNT, + "Mismatch between number of SDS regions and number of regions " + "provided by the SDS configuration."); const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC0_SDS_REGION_COUNT, - .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_INTERCONNECT) + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT) }; static struct fwk_element sds_element_table[] = { { .name = "CPU Info", - .data = &((struct mod_sds_structure_desc) { + .data = &((struct mod_sds_structure_desc){ .id = TC0_SDS_CPU_INFO, .size = TC0_SDS_CPU_INFO_SIZE, .region_id = TC0_SDS_REGION_SECURE, @@ -54,7 +56,7 @@ static struct fwk_element sds_element_table[] = { }, { .name = "Feature Availability", - .data = &((struct mod_sds_structure_desc) { + .data = &((struct mod_sds_structure_desc){ .id = TC0_SDS_FEATURE_AVAILABILITY, .size = TC0_SDS_FEATURE_AVAILABILITY_SIZE, .payload = &feature_flags, @@ -65,10 +67,10 @@ static struct fwk_element sds_element_table[] = { { 0 }, /* Termination description. */ }; -static_assert(SCP_SDS_MEM_SIZE > - TC0_SDS_CPU_INFO_SIZE + - TC0_SDS_FEATURE_AVAILABILITY_SIZE, - "SDS structures too large for SDS SRAM.\n"); +static_assert( + SCP_SDS_MEM_SIZE > + TC0_SDS_CPU_INFO_SIZE + TC0_SDS_FEATURE_AVAILABILITY_SIZE, + "SDS structures too large for SDS SRAM.\n"); static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) { diff --git a/product/tc0/scp_ramfw/config_smt.c b/product/tc0/scp_ramfw/config_smt.c index 35a2b9ce..e019fd46 100644 --- a/product/tc0/scp_ramfw/config_smt.c +++ b/product/tc0/scp_ramfw/config_smt.c @@ -6,10 +6,10 @@ */ #include "config_power_domain.h" +#include "scp_software_mmap.h" +#include "scp_tc0_mhu.h" #include "tc0_core.h" #include "tc0_scmi.h" -#include "scp_tc0_mhu.h" -#include "scp_software_mmap.h" #include <mod_smt.h> @@ -21,30 +21,43 @@ #include <stdint.h> static const struct fwk_element smt_element_table[] = { - [SCP_TC0_SCMI_SERVICE_IDX_PSCI] = { - .name = "PSCI", - .data = &((struct mod_smt_channel_config) { - .type = MOD_SMT_CHANNEL_TYPE_SLAVE, - .policies = MOD_SMT_POLICY_INIT_MAILBOX | MOD_SMT_POLICY_SECURE, - .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_S_A2P_BASE, - .mailbox_size = SCP_SCMI_PAYLOAD_SIZE, - .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), - }) - }, - [SCP_TC0_SCMI_SERVICE_IDX_OSPM] = { - .name = "OSPM", - .data = &((struct mod_smt_channel_config) { - .type = MOD_SMT_CHANNEL_TYPE_SLAVE, - .policies = MOD_SMT_POLICY_INIT_MAILBOX, - .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_NS_A2P_BASE, - .mailbox_size = SCP_SCMI_PAYLOAD_SIZE, - .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0, 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), - }) - }, + [SCP_TC0_SCMI_SERVICE_IDX_PSCI] = { .name = "PSCI", + .data = &(( + struct mod_smt_channel_config){ + .type = MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX | + MOD_SMT_POLICY_SECURE, + .mailbox_address = (uintptr_t) + SCP_SCMI_PAYLOAD_S_A2P_BASE, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU2, + SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, + 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU2, + 0), + }) }, + [SCP_TC0_SCMI_SERVICE_IDX_OSPM] = { .name = "OSPM", + .data = &(( + struct mod_smt_channel_config){ + .type = MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = + MOD_SMT_POLICY_INIT_MAILBOX, + .mailbox_address = (uintptr_t) + SCP_SCMI_PAYLOAD_NS_A2P_BASE, + .mailbox_size = + SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT( + FWK_MODULE_IDX_MHU2, + SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0, + 0), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_MHU2, + 0), + }) }, [SCP_TC0_SCMI_SERVICE_IDX_COUNT] = { 0 }, }; diff --git a/product/tc0/scp_ramfw/config_system_pll.c b/product/tc0/scp_ramfw/config_system_pll.c index aef20e94..0fe4c777 100644 --- a/product/tc0/scp_ramfw/config_system_pll.c +++ b/product/tc0/scp_ramfw/config_system_pll.c @@ -16,85 +16,93 @@ #include <fwk_macros.h> #include <fwk_module.h> -static const struct fwk_element system_pll_element_table[] = { - [CLOCK_PLL_IDX_CPU0] = { - .name = "CPU_PLL_0", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_CPU0, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), - .initial_rate = 1750 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_SYS] = { - .name = "SYS_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_SYSPLL, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_INTERCONNECT] = { - .name = "INT_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_INTERCONNECT, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_DPU] = { - .name = "DPU_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_DISPLAY, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_DISPLAYPLLLOCK, - .initial_rate = 600 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_PIX0] = { - .name = "PIX0_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_PIX0, - .status_reg = NULL, - .initial_rate = 594 * FWK_MHZ, - .min_rate = 12500 * FWK_KHZ, - .max_rate = 594 * FWK_MHZ, - .min_step = 25 * FWK_KHZ, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_PIX1] = { - .name = "PIX1_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_PIX1, - .status_reg = NULL, - .initial_rate = 594 * FWK_MHZ, - .min_rate = 12500 * FWK_KHZ, - .max_rate = 594 * FWK_MHZ, - .min_step = 25 * FWK_KHZ, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ -}; +static const struct fwk_element system_pll_element_table[] = + { + [CLOCK_PLL_IDX_CPU0] = + { + .name = "CPU_PLL_0", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_CPU0, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), + .initial_rate = 1750 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_SYS] = + { + .name = "SYS_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_SYSPLL, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_INTERCONNECT] = + { + .name = "INT_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_INTERCONNECT, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_DPU] = + { + .name = "DPU_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_DISPLAY, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_DISPLAYPLLLOCK, + .initial_rate = 600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_PIX0] = + { + .name = "PIX0_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_PIX0, + .status_reg = NULL, + .initial_rate = 594 * FWK_MHZ, + .min_rate = 12500 * FWK_KHZ, + .max_rate = 594 * FWK_MHZ, + .min_step = 25 * FWK_KHZ, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_PIX1] = + { + .name = "PIX1_PLL", + .data = &( + (struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_PIX1, + .status_reg = NULL, + .initial_rate = 594 * FWK_MHZ, + .min_rate = 12500 * FWK_KHZ, + .max_rate = 594 * FWK_MHZ, + .min_step = 25 * FWK_KHZ, + .defer_initialization = false, + }), + }, + [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ + }; -static const struct fwk_element *system_pll_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *system_pll_get_element_table( + fwk_id_t module_id) { return system_pll_element_table; } diff --git a/product/tc0/scp_ramfw/config_system_power.c b/product/tc0/scp_ramfw/config_system_power.c index 142daeb4..737ab94e 100644 --- a/product/tc0/scp_ramfw/config_system_power.c +++ b/product/tc0/scp_ramfw/config_system_power.c @@ -23,35 +23,39 @@ #include <stdint.h> static const uint8_t system_power_to_sys_ppu0_state[] = { - [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, - [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, }; static const uint8_t system_power_to_sys_ppu1_state[] = { - [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_ON, - [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, }; static struct fwk_element system_power_element_table[] = { - [0] = { - .name = "SYS-PPU-0", - .data = &((struct mod_system_power_dev_config) { - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, - MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), - .sys_state_table = system_power_to_sys_ppu0_state, - }), - }, - - [1] = { - .name = "SYS-PPU-1", - .data = &((struct mod_system_power_dev_config) { - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, - MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), - .sys_state_table = system_power_to_sys_ppu1_state, - }), - }, + [0] = + { + .name = "SYS-PPU-0", + .data = &((struct mod_system_power_dev_config){ + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu0_state, + }), + }, + + [1] = + { + .name = "SYS-PPU-1", + .data = &((struct mod_system_power_dev_config){ + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu1_state, + }), + }, [2] = { 0 }, /* Termination description */ }; @@ -61,26 +65,27 @@ static struct mod_system_power_config system_power_config = { /* System driver */ .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_TC0_SYSTEM), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_TC0_SYSTEM, - MOD_TC0_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), + .driver_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_TC0_SYSTEM, + MOD_TC0_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), /* Initial system state */ .initial_system_power_state = MOD_PD_STATE_OFF, }; -static const struct fwk_element *tc0_system_get_element_table( - fwk_id_t unused) +static const struct fwk_element *tc0_system_get_element_table(fwk_id_t unused) { struct mod_system_power_dev_config *dev_config_table; unsigned int i; /* The system PPUs are placed after the core and cluster PPUs */ - unsigned int ppu_idx_base = tc0_core_get_core_count() + - tc0_core_get_cluster_count(); + unsigned int ppu_idx_base = + tc0_core_get_core_count() + tc0_core_get_cluster_count(); for (i = 0; i < (FWK_ARRAY_SIZE(system_power_element_table) - 1); i++) { - dev_config_table = (struct mod_system_power_dev_config *) - system_power_element_table[i].data; + dev_config_table = + (struct mod_system_power_dev_config *)system_power_element_table[i] + .data; dev_config_table->sys_ppu_id = fwk_id_build_element_id(fwk_module_id_ppu_v1, ppu_idx_base + i); } diff --git a/product/tc0/scp_ramfw/config_timer.c b/product/tc0/scp_ramfw/config_timer.c index 4d6a311d..a5b9266f 100644 --- a/product/tc0/scp_ramfw/config_timer.c +++ b/product/tc0/scp_ramfw/config_timer.c @@ -20,15 +20,16 @@ * Timer HAL config */ static const struct fwk_element timer_dev_table[] = { - [0] = { - .name = "REFCLK", - .data = &((struct mod_timer_dev_config) { - .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), - .timer_irq = TIMREFCLK_IRQ, - }), - /* Number of alarms */ - .sub_element_count = CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, - }, + [0] = + { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config){ + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = TIMREFCLK_IRQ, + }), + /* Number of alarms */ + .sub_element_count = CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, + }, [1] = { 0 }, }; diff --git a/product/tc0/scp_romfw/config_clock.c b/product/tc0/scp_romfw/config_clock.c index 56f9b405..2fe204f5 100644 --- a/product/tc0/scp_romfw/config_clock.c +++ b/product/tc0/scp_romfw/config_clock.c @@ -21,27 +21,33 @@ #include <fwk_module_idx.h> static const struct fwk_element clock_dev_desc_table[] = { - [CLOCK_IDX_INTERCONNECT] = { - .name = "Interconnect", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, - CLOCK_PIK_IDX_INTERCONNECT), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CLOCK), - .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MSYS_ROM), + [CLOCK_IDX_INTERCONNECT] = + { + .name = "Interconnect", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + CLOCK_PIK_IDX_INTERCONNECT), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CLOCK), + .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MSYS_ROM), - }), - }, - [CLOCK_IDX_CPU_GROUP0] = { - .name = "CPU_GROUP0", - .data = &((struct mod_clock_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP0), - .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MSYS_ROM), - }), - }, + }), + }, + [CLOCK_IDX_CPU_GROUP0] = + { + .name = "CPU_GROUP0", + .data = &((struct mod_clock_dev_config){ + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MSYS_ROM), + }), + }, { 0 }, /* Termination description. */ }; diff --git a/product/tc0/scp_romfw/config_css_clock.c b/product/tc0/scp_romfw/config_css_clock.c index 540568a1..554f1c02 100644 --- a/product/tc0/scp_romfw/config_css_clock.c +++ b/product/tc0/scp_romfw/config_css_clock.c @@ -75,30 +75,34 @@ static const fwk_id_t member_table_cpu_group_0[] = { }; static const struct fwk_element css_clock_element_table[] = { - [CLOCK_CSS_IDX_CPU_GROUP0] = { - .name = "CPU_GROUP_0", - .data = &((struct mod_css_clock_dev_config) { - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), - .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, - .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU0), - .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_0, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), - .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 2271 * FWK_MHZ, - .modulation_supported = true, - }), - }, + [CLOCK_CSS_IDX_CPU_GROUP0] = + { + .name = "CPU_GROUP_0", + .data = &((struct mod_css_clock_dev_config){ + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + .clock_switching_source = + MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU0), + .pll_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_0, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), + .member_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2271 * FWK_MHZ, + .modulation_supported = true, + }), + }, [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ }; -static const struct fwk_element *css_clock_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) { return css_clock_element_table; } diff --git a/product/tc0/scp_romfw/config_gtimer.c b/product/tc0/scp_romfw/config_gtimer.c index e35e4792..8f83fb51 100644 --- a/product/tc0/scp_romfw/config_gtimer.c +++ b/product/tc0/scp_romfw/config_gtimer.c @@ -20,17 +20,15 @@ * Generic timer driver config */ static const struct fwk_element gtimer_dev_table[] = { - [0] = { - .name = "REFCLK", - .data = &((struct mod_gtimer_dev_config) { - .hw_timer = SCP_REFCLK_CNTBASE0_BASE, - .hw_counter = SCP_REFCLK_CNTCTL_BASE, - .control = SCP_REFCLK_CNTCONTROL_BASE, - .frequency = CLOCK_RATE_REFCLK, - .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_INTERCONNECT) - }) - }, + [0] = { .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config){ + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) }) }, [1] = { 0 }, }; diff --git a/product/tc0/scp_romfw/config_msys_rom.c b/product/tc0/scp_romfw/config_msys_rom.c index 6b0ef6b9..c8489929 100644 --- a/product/tc0/scp_romfw/config_msys_rom.c +++ b/product/tc0/scp_romfw/config_msys_rom.c @@ -14,7 +14,7 @@ #include <fwk_module_idx.h> const struct fwk_module_config config_msys_rom = { - .data = &((struct msys_rom_config) { + .data = &((struct msys_rom_config){ .ap_context_base = SCP_AP_CONTEXT_BASE, .ap_context_size = SCP_AP_CONTEXT_SIZE, .id_primary_cluster = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 1), diff --git a/product/tc0/scp_romfw/config_pik_clock.c b/product/tc0/scp_romfw/config_pik_clock.c index af9c829b..ee847f4d 100644 --- a/product/tc0/scp_romfw/config_pik_clock.c +++ b/product/tc0/scp_romfw/config_pik_clock.c @@ -82,97 +82,109 @@ static const struct mod_pik_clock_rate rate_table_uartclk[] = { }, }; -static const struct fwk_element pik_clock_element_table[] = { +static const struct fwk_element + pik_clock_element_table[] = + { - [CLOCK_PIK_IDX_CLUS0_CPU0] = { - .name = "CLUS0_CPU0", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), - }), - }, - [CLOCK_PIK_IDX_INTERCONNECT] = { - .name = "INTERCONNECT", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->INTCLK_CTRL, - .divext_reg = &SYSTEM_PIK_PTR->INTCLK_DIV1, - .rate_table = rate_table_sys_intclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_SCP] = { - .name = "SCP", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SCP_PIK_PTR->CORECLK_CTRL, - .divsys_reg = &SCP_PIK_PTR->CORECLK_DIV1, - .rate_table = rate_table_scp, - .rate_count = FWK_ARRAY_SIZE(rate_table_scp), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_GIC] = { - .name = "GIC", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, - .rate_table = rate_table_gicclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_PCLKSCP] = { - .name = "PCLKSCP", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, - .rate_table = rate_table_pclkscp, - .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_SYSPERCLK] = { - .name = "SYSPERCLK", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, - .rate_table = rate_table_sysperclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_UARTCLK] = { - .name = "UARTCLK", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, - .rate_table = rate_table_uartclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ -}; + [CLOCK_PIK_IDX_CLUS0_CPU0] = + { + .name = "CLUS0_CPU0", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL, + .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV, + .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), + }), + }, + [CLOCK_PIK_IDX_INTERCONNECT] = + { + .name = "INTERCONNECT", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->INTCLK_CTRL, + .divext_reg = &SYSTEM_PIK_PTR->INTCLK_DIV1, + .rate_table = rate_table_sys_intclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SCP] = + { + .name = "SCP", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SCP_PIK_PTR->CORECLK_CTRL, + .divsys_reg = &SCP_PIK_PTR->CORECLK_DIV1, + .rate_table = rate_table_scp, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_GIC] = + { + .name = "GIC", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, + .rate_table = rate_table_gicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_PCLKSCP] = + { + .name = "PCLKSCP", + .data = &((struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, + .rate_table = rate_table_pclkscp, + .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SYSPERCLK] = + { + .name = "SYSPERCLK", + .data = + &( + (struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, + .rate_table = rate_table_sysperclk, + .rate_count = + FWK_ARRAY_SIZE(rate_table_sysperclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_UARTCLK] = + { + .name = "UARTCLK", + .data = &( + (struct mod_pik_clock_dev_config){ + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, + .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, + .rate_table = rate_table_uartclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ + }; -static const struct fwk_element *pik_clock_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) { return pik_clock_element_table; } diff --git a/product/tc0/scp_romfw/config_pl011.c b/product/tc0/scp_romfw/config_pl011.c index cb9d1396..72bd9d77 100644 --- a/product/tc0/scp_romfw/config_pl011.c +++ b/product/tc0/scp_romfw/config_pl011.c @@ -16,16 +16,17 @@ const struct fwk_module_config config_pl011 = { .elements = FWK_MODULE_STATIC_ELEMENTS({ - [0] = { - .name = "uart", - .data = - &(struct mod_pl011_element_cfg){ - .reg_base = SCP_UART_BASE, - .baud_rate_bps = 115200, - .clock_rate_hz = 24 * FWK_MHZ, - .clock_id = FWK_ID_NONE_INIT, - }, - }, + [0] = + { + .name = "uart", + .data = + &(struct mod_pl011_element_cfg){ + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + }, + }, [1] = { 0 }, }), diff --git a/product/tc0/scp_romfw/config_ppu_v1.c b/product/tc0/scp_romfw/config_ppu_v1.c index 0251a8dd..949fd6b4 100644 --- a/product/tc0/scp_romfw/config_ppu_v1.c +++ b/product/tc0/scp_romfw/config_ppu_v1.c @@ -6,8 +6,8 @@ */ #include "config_power_domain.h" -#include "tc0_core.h" #include "scp_css_mmap.h" +#include "tc0_core.h" #include <mod_cmn_booker.h> #include <mod_msys_rom.h> @@ -31,14 +31,13 @@ /* Maximum PPU cluster name size including the null terminator */ #define PPU_CLUS_NAME_SIZE 6 - /* Lookup table for translating cluster indicies into CMN_BOOKER node IDs */ -static const unsigned int cluster_idx_to_node_id[] = {68}; +static const unsigned int cluster_idx_to_node_id[] = { 68 }; static struct fwk_element ppu_v1_system_element_table[] = { { .name = "SYS0", - .data = &((struct mod_ppu_v1_pd_config) { + .data = &((struct mod_ppu_v1_pd_config){ .pd_type = MOD_PD_TYPE_SYSTEM, .ppu.reg_base = SCP_PPU_SYS0_BASE, .observer_id = FWK_ID_NONE_INIT, @@ -47,7 +46,7 @@ static struct fwk_element ppu_v1_system_element_table[] = { }, { .name = "SYS1", - .data = &((struct mod_ppu_v1_pd_config) { + .data = &((struct mod_ppu_v1_pd_config){ .pd_type = MOD_PD_TYPE_SYSTEM, .ppu.reg_base = SCP_PPU_SYS1_BASE, .observer_id = FWK_ID_NONE_INIT, @@ -70,8 +69,8 @@ static const struct fwk_element *tc0_ppu_v1_get_element_table( * + Number of system power domain descriptors * + 1 terminator descriptor */ - element_table = fwk_mm_calloc(2 + - FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, + element_table = fwk_mm_calloc( + 2 + FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, sizeof(struct fwk_element)); if (element_table == NULL) return NULL; @@ -95,11 +94,10 @@ static const struct fwk_element *tc0_ppu_v1_get_element_table( pd_config->pd_type = MOD_PD_TYPE_CORE; pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(0, 0); pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->cluster_id = - FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, 1); + pd_config->cluster_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, 1); pd_config->observer_id = FWK_ID_NONE; - //pd_config for cluster0 + // pd_config for cluster0 element = &element_table[1]; pd_config = &pd_config_table[1]; @@ -116,14 +114,14 @@ static const struct fwk_element *tc0_ppu_v1_get_element_table( pd_config->ppu.irq = FWK_INTERRUPT_NONE; pd_config->observer_id = fwk_module_id_cmn_booker; - pd_config->observer_api = FWK_ID_API(FWK_MODULE_IDX_CMN_BOOKER, - MOD_CMN_BOOKER_API_IDX_PPU_OBSERVER); - pd_config->post_ppu_on_param = - (void *)&cluster_idx_to_node_id[0]; - - memcpy(&element_table[2], - ppu_v1_system_element_table, - sizeof(ppu_v1_system_element_table)); + pd_config->observer_api = FWK_ID_API( + FWK_MODULE_IDX_CMN_BOOKER, MOD_CMN_BOOKER_API_IDX_PPU_OBSERVER); + pd_config->post_ppu_on_param = (void *)&cluster_idx_to_node_id[0]; + + memcpy( + &element_table[2], + ppu_v1_system_element_table, + sizeof(ppu_v1_system_element_table)); return element_table; } diff --git a/product/tc0/scp_romfw/config_sds.c b/product/tc0/scp_romfw/config_sds.c index 46d22e5b..fdfb9fef 100644 --- a/product/tc0/scp_romfw/config_sds.c +++ b/product/tc0/scp_romfw/config_sds.c @@ -6,9 +6,9 @@ */ #include "clock_soc.h" -#include "tc0_sds.h" #include "scp_pik.h" #include "scp_software_mmap.h" +#include "tc0_sds.h" #include <mod_sds.h> @@ -25,27 +25,29 @@ static const uint32_t feature_flags = 0x00000000; static const struct mod_sds_region_desc sds_module_regions[] = { - [TC0_SDS_REGION_SECURE] = { - .base = (void*)SCP_SDS_MEM_BASE, - .size = SCP_SDS_MEM_SIZE, - }, + [TC0_SDS_REGION_SECURE] = + { + .base = (void *)SCP_SDS_MEM_BASE, + .size = SCP_SDS_MEM_SIZE, + }, }; -static_assert(FWK_ARRAY_SIZE(sds_module_regions) == TC0_SDS_REGION_COUNT, - "Mismatch between number of SDS regions and number of regions " - "provided by the SDS configuration."); +static_assert( + FWK_ARRAY_SIZE(sds_module_regions) == TC0_SDS_REGION_COUNT, + "Mismatch between number of SDS regions and number of regions " + "provided by the SDS configuration."); const struct mod_sds_config sds_module_config = { .regions = sds_module_regions, .region_count = TC0_SDS_REGION_COUNT, - .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_INTERCONNECT) + .clock_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT) }; static struct fwk_element sds_element_table[] = { { .name = "CPU Info", - .data = &((struct mod_sds_structure_desc) { + .data = &((struct mod_sds_structure_desc){ .id = TC0_SDS_CPU_INFO, .size = TC0_SDS_CPU_INFO_SIZE, .region_id = TC0_SDS_REGION_SECURE, @@ -54,7 +56,7 @@ static struct fwk_element sds_element_table[] = { }, { .name = "Feature Availability", - .data = &((struct mod_sds_structure_desc) { + .data = &((struct mod_sds_structure_desc){ .id = TC0_SDS_FEATURE_AVAILABILITY, .size = TC0_SDS_FEATURE_AVAILABILITY_SIZE, .payload = &feature_flags, @@ -64,7 +66,7 @@ static struct fwk_element sds_element_table[] = { }, { .name = "Bootloader", - .data = &((struct mod_sds_structure_desc) { + .data = &((struct mod_sds_structure_desc){ .id = TC0_SDS_BOOTLOADER, .size = TC0_SDS_BOOTLOADER_SIZE, .region_id = TC0_SDS_REGION_SECURE, @@ -74,11 +76,10 @@ static struct fwk_element sds_element_table[] = { { 0 }, /* Termination description. */ }; -static_assert(SCP_SDS_MEM_SIZE > - TC0_SDS_CPU_INFO_SIZE + - TC0_SDS_FEATURE_AVAILABILITY_SIZE + - TC0_SDS_BOOTLOADER_SIZE, - "SDS structures too large for SDS SRAM.\n"); +static_assert( + SCP_SDS_MEM_SIZE > TC0_SDS_CPU_INFO_SIZE + + TC0_SDS_FEATURE_AVAILABILITY_SIZE + TC0_SDS_BOOTLOADER_SIZE, + "SDS structures too large for SDS SRAM.\n"); static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) { diff --git a/product/tc0/scp_romfw/config_system_pll.c b/product/tc0/scp_romfw/config_system_pll.c index 12aca89b..192514bd 100644 --- a/product/tc0/scp_romfw/config_system_pll.c +++ b/product/tc0/scp_romfw/config_system_pll.c @@ -17,47 +17,50 @@ #include <fwk_module.h> static const struct fwk_element system_pll_element_table[] = { - [CLOCK_PLL_IDX_CPU0] = { - .name = "CPU_PLL_0", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_CPU0, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), - .initial_rate = 1750 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_SYS] = { - .name = "SYS_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_SYSPLL, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_INTERCONNECT] = { - .name = "INT_PLL", - .data = &((struct mod_system_pll_dev_config) { - .control_reg = (void *)SCP_PLL_INTERCONNECT, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, + [CLOCK_PLL_IDX_CPU0] = + { + .name = "CPU_PLL_0", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_CPU0, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), + .initial_rate = 1750 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_SYS] = + { + .name = "SYS_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_SYSPLL, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_INTERCONNECT] = + { + .name = "INT_PLL", + .data = &((struct mod_system_pll_dev_config){ + .control_reg = (void *)SCP_PLL_INTERCONNECT, + .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ }; -static const struct fwk_element *system_pll_get_element_table - (fwk_id_t module_id) +static const struct fwk_element *system_pll_get_element_table( + fwk_id_t module_id) { return system_pll_element_table; } diff --git a/product/tc0/scp_romfw/config_timer.c b/product/tc0/scp_romfw/config_timer.c index 87be05fd..746e6b29 100644 --- a/product/tc0/scp_romfw/config_timer.c +++ b/product/tc0/scp_romfw/config_timer.c @@ -18,14 +18,15 @@ * Timer HAL config */ static const struct fwk_element timer_dev_table[] = { - [0] = { - .name = "REFCLK", - .data = &((struct mod_timer_dev_config) { - .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), - .timer_irq = TIMREFCLK_IRQ, - }), - .sub_element_count = 8, /* Number of alarms */ - }, + [0] = + { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config){ + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = TIMREFCLK_IRQ, + }), + .sub_element_count = 8, /* Number of alarms */ + }, [1] = { 0 }, }; |