rcar/module: add rcar mstp_clock module and config data

Change-Id: I979fecb8b71fb7a1f962574d8bc6f439e7bfb68d
Signed-off-by: Tsutomu Muroya <tsutomu.muroya.jy@bp.renesas.com>
Signed-off-by: Nicolas Royer <nroyer@baylibre.com>

4 files changed, 1406 insertions, 0 deletions

diff --git a/product/rcar/module/rcar_mstp_clock/include/mod_rcar_mstp_clock.h b/product/rcar/module/rcar_mstp_clock/include/mod_rcar_mstp_clock.h
new file mode 100644
index 00000000..099e5e26
--- /dev/null
+++ b/product/rcar/module/rcar_mstp_clock/include/mod_rcar_mstp_clock.h
@@ -0,0 +1,104 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MOD_RCAR_MSTP_CLOCK_H
+#define MOD_RCAR_MSTP_CLOCK_H
+
+#include <rcar_mmap.h>
+
+#include <mod_clock.h>
+#include <mod_rcar_clock.h>
+
+#include <fwk_element.h>
+
+#include <stdint.h>
+
+/*!
+ * \addtogroup GroupRCARModule RCAR Product Modules
+ * @{
+ */
+
+/*!
+ * \defgroup GroupRCARMstpClock MSTP Clock
+ * @{
+ */
+
+/*!
+ * \brief Subsystem clock device configuration.
+ */
+struct mod_rcar_mstp_clock_dev_config {
+    /*! Pointer to the clock's control register. */
+    volatile uint32_t const control_reg;
+
+    /*! enable / disable bit position. */
+    volatile uint32_t const bit;
+
+    /*! If true, the driver will provide a default clock supply. */
+    const bool defer_initialization;
+};
+
+/*!
+ * @cond
+ */
+
+/* Device context */
+struct rcar_mstp_clock_dev_ctx {
+    bool initialized;
+    uint64_t current_rate;
+    enum mod_clock_state current_state;
+    const struct mod_rcar_mstp_clock_dev_config *config;
+    struct mod_rcar_clock_drv_api *api;
+};
+
+struct mod_rcar_mstp_clock_init {
+    volatile uint32_t const smstpcr_init[12];
+};
+
+/* Module context */
+struct rcar_mstp_clock_ctx {
+    struct rcar_mstp_clock_dev_ctx *dev_ctx_table;
+    unsigned int dev_count;
+    const struct mod_rcar_mstp_clock_init *mstp_init;
+};
+
+/* Module Stop Status Register offsets */
+static const uint16_t mstpsr[] = {
+    0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C,
+    0x1C0, 0x1C4, 0x9A0, 0x9A4, 0x9A8, 0x9AC,
+};
+
+/* System Module Stop Control Register offsets */
+static const uint16_t smstpcr[] = {
+    0x130, 0x134, 0x138, 0x13C, 0x140, 0x144,
+    0x148, 0x14C, 0x990, 0x994, 0x998, 0x99C,
+};
+
+/* System Module Stop Control Register Number */
+#define CPG_SMSTPCR1 1
+#define CPG_SMSTPCR2 2
+#define CPG_SMSTPCR3 3
+#define CPG_SMSTPCR4 4
+#define CPG_SMSTPCR5 5
+#define CPG_SMSTPCR6 6
+#define CPG_SMSTPCR7 7
+#define CPG_SMSTPCR8 8
+#define CPG_SMSTPCR9 9
+#define CPG_SMSTPCR10 10
+
+/*!
+ * @endcond
+ */
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#endif /* MOD_RCAR_MSTP_CLOCK_H */
diff --git a/product/rcar/module/rcar_mstp_clock/src/Makefile b/product/rcar/module/rcar_mstp_clock/src/Makefile
new file mode 100644
index 00000000..fe4acb10
--- /dev/null
+++ b/product/rcar/module/rcar_mstp_clock/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Renesas SCP/MCP Software
+# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := RCAR SD Clock Driver
+BS_LIB_SOURCES := mod_rcar_mstp_clock.c
+
+include $(BS_DIR)/lib.mk
diff --git a/product/rcar/module/rcar_mstp_clock/src/mod_rcar_mstp_clock.c b/product/rcar/module/rcar_mstp_clock/src/mod_rcar_mstp_clock.c
new file mode 100644
index 00000000..36d3e8b6
--- /dev/null
+++ b/product/rcar/module/rcar_mstp_clock/src/mod_rcar_mstp_clock.c
@@ -0,0 +1,210 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <clock_mstp_devices.h>
+#include <mmio.h>
+
+#include <mod_clock.h>
+#include <mod_rcar_clock.h>
+#include <mod_rcar_mstp_clock.h>
+
+#include <fwk_assert.h>
+#include <fwk_element.h>
+#include <fwk_mm.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <fwk_status.h>
+
+#include <stdint.h>
+
+static struct rcar_mstp_clock_ctx module_ctx;
+
+/*
+ * Static helper functions
+ */
+static int mstp_clock_set_state(
+    fwk_id_t dev_id,
+    enum mod_clock_state target_state)
+{
+    struct rcar_mstp_clock_dev_ctx *ctx;
+    uint32_t value;
+    int i;
+
+    ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id);
+
+    value = mmio_read_32(CPG_BASE + smstpcr[ctx->config->control_reg]);
+    if (MOD_CLOCK_STATE_RUNNING == target_state)
+        value &= ~(BIT(ctx->config->bit));
+    else
+        value |= BIT(ctx->config->bit);
+
+    mmio_write_32((CPG_BASE + smstpcr[ctx->config->control_reg]), value);
+
+    if (MOD_CLOCK_STATE_RUNNING == target_state) {
+        for (i = 1000; i > 0; --i) {
+            if (!(mmio_read_32(CPG_BASE + mstpsr[ctx->config->control_reg]) &
+                  BIT(ctx->config->bit)))
+                break;
+        }
+
+        if (!i)
+            return FWK_E_TIMEOUT;
+    }
+
+    ctx->current_state = target_state;
+    return FWK_SUCCESS;
+}
+
+static int mstp_clock_get_state(fwk_id_t dev_id, enum mod_clock_state *state)
+{
+    struct rcar_mstp_clock_dev_ctx *ctx;
+
+    ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(dev_id);
+    *state = ctx->current_state;
+    return FWK_SUCCESS;
+}
+
+static void mstp_clock_hw_initial_set_state(
+    fwk_id_t element_id,
+    struct rcar_mstp_clock_dev_ctx *ctx)
+{
+    /* Maintain clock supply at startup. */
+    if (module_ctx.mstp_init->smstpcr_init[ctx->config->control_reg] &
+        BIT(ctx->config->bit))
+        ctx->current_state = MOD_CLOCK_STATE_STOPPED;
+    else
+        ctx->current_state = MOD_CLOCK_STATE_RUNNING;
+
+    /* If true, the driver will provide a default clock supply. */
+    if (ctx->config->defer_initialization)
+        mstp_clock_set_state(element_id, MOD_CLOCK_STATE_RUNNING);
+}
+
+static int mstp_clock_resume(void)
+{
+    fwk_id_t element_id =
+        FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLK_ID_MSTP_START);
+    uint32_t mstp_id;
+    struct rcar_mstp_clock_dev_ctx *ctx;
+
+    for (mstp_id = CLK_ID_MSTP_START; mstp_id < CLK_ID_MSTP_END; mstp_id++) {
+        element_id.element.element_idx = mstp_id;
+        ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(element_id);
+        mstp_clock_hw_initial_set_state(element_id, ctx);
+    }
+    return FWK_SUCCESS;
+}
+
+static int mstp_clock_set_rate(
+    fwk_id_t dev_id,
+    uint64_t rate,
+    enum mod_clock_round_mode round_mode)
+{
+    return FWK_E_PARAM;
+}
+
+static int mstp_clock_get_rate(fwk_id_t dev_id, uint64_t *rate)
+{
+    return FWK_E_PARAM;
+}
+
+static int mstp_clock_get_rate_from_index(
+    fwk_id_t dev_id,
+    unsigned int rate_index,
+    uint64_t *rate)
+{
+    return FWK_E_PARAM;
+}
+
+static int mstp_clock_get_range(fwk_id_t dev_id, struct mod_clock_range *range)
+{
+    return FWK_E_PARAM;
+}
+
+static const struct mod_rcar_clock_drv_api api_clock = {
+    .set_state = mstp_clock_set_state,
+    .get_state = mstp_clock_get_state,
+    .resume = mstp_clock_resume,
+    .set_rate = mstp_clock_set_rate,
+    .get_rate = mstp_clock_get_rate,
+    .get_rate_from_index = mstp_clock_get_rate_from_index,
+    .get_range = mstp_clock_get_range,
+};
+
+/*
+ * Framework handler functions
+ */
+
+static int mstp_clock_init(
+    fwk_id_t module_id,
+    unsigned int element_count,
+    const void *data)
+{
+    const struct mod_rcar_mstp_clock_init *mstp_init = data;
+
+    module_ctx.dev_count = element_count;
+
+    if (element_count == 0)
+        return FWK_SUCCESS;
+
+    if (mstp_init == NULL)
+        return FWK_E_PARAM;
+
+    module_ctx.mstp_init = mstp_init;
+    module_ctx.dev_ctx_table =
+        fwk_mm_calloc(element_count, sizeof(struct rcar_mstp_clock_dev_ctx));
+    if (module_ctx.dev_ctx_table == NULL)
+        return FWK_E_NOMEM;
+
+    return FWK_SUCCESS;
+}
+
+static int mstp_clock_element_init(
+    fwk_id_t element_id,
+    unsigned int sub_element_count,
+    const void *data)
+{
+    struct rcar_mstp_clock_dev_ctx *ctx;
+    const struct mod_rcar_mstp_clock_dev_config *dev_config = data;
+
+    if (!fwk_module_is_valid_element_id(element_id))
+        return FWK_E_PARAM;
+
+    ctx = module_ctx.dev_ctx_table + fwk_id_get_element_idx(element_id);
+    ctx->config = dev_config;
+    ctx->initialized = true;
+
+    return FWK_SUCCESS;
+}
+
+static int mstp_clock_process_bind_request(
+    fwk_id_t source_id,
+    fwk_id_t target_id,
+    fwk_id_t api_id,
+    const void **api)
+{
+    *api = &api_clock;
+    return FWK_SUCCESS;
+}
+
+static int mstp_clock_start(fwk_id_t id)
+{
+    int ret = FWK_SUCCESS;
+    ret = mstp_clock_resume();
+    return ret;
+}
+
+const struct fwk_module module_rcar_mstp_clock = {
+    .name = "MSTP Clock Driver",
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .api_count = MOD_RCAR_CLOCK_API_COUNT,
+    .event_count = 0,
+    .init = mstp_clock_init,
+    .element_init = mstp_clock_element_init,
+    .process_bind_request = mstp_clock_process_bind_request,
+    .start = mstp_clock_start,
+};
diff --git a/product/rcar/scp_ramfw/config_rcar_mstp_clock.c b/product/rcar/scp_ramfw/config_rcar_mstp_clock.c
new file mode 100644
index 00000000..970709ef
--- /dev/null
+++ b/product/rcar/scp_ramfw/config_rcar_mstp_clock.c
@@ -0,0 +1,1081 @@
+/*
+ * Renesas SCP/MCP Software
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <clock_sd_devices.h>
+#include <system_clock.h>
+
+#include <mod_rcar_mstp_clock.h>
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+
+static const struct fwk_element pik_clock_element_table[] = {
+    {
+        .name = "fdp1-1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR1,
+            .bit = 18,
+        }),
+    },
+    {
+        .name = "fdp1-0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR1,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "scif5",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 2,
+        }),
+    },
+    {
+        .name = "scif4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 3,
+        }),
+    },
+    {
+        .name = "scif3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 4,
+        }),
+    },
+    {
+        .name = "scif1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 6,
+        }),
+    },
+    {
+        .name = "scif0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 7,
+        }),
+    },
+    {
+        .name = "msiof3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "msiof2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 9,
+        }),
+    },
+    {
+        .name = "msiof1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "msiof0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "sys-dmac2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 17,
+        }),
+    },
+    {
+        .name = "sys-dmac1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 18,
+        }),
+    },
+    {
+        .name = "sys-dmac0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "sceg-pub",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR2,
+            .bit = 29,
+        }),
+    },
+    {
+        .name = "cmt3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 0,
+        }),
+    },
+    {
+        .name = "cmt2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 1,
+        }),
+    },
+    {
+        .name = "cmt1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 2,
+        }),
+    },
+    {
+        .name = "cmt0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 3,
+        }),
+    },
+    {
+        .name = "tpu0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 4,
+        }),
+    },
+    {
+        .name = "scif2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "sdif3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "sdif2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 12,
+        }),
+    },
+    {
+        .name = "sdif1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 13,
+        }),
+    },
+    {
+        .name = "sdif0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 14,
+        }),
+    },
+    {
+        .name = "pcie1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 18,
+        }),
+    },
+    {
+        .name = "pcie0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "usb-dmac30",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 26,
+        }),
+    },
+    {
+        .name = "usb3-if0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 28,
+        }),
+    },
+    {
+        .name = "usb-dmac31",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 29,
+        }),
+    },
+    {
+        .name = "usb-dmac0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 30,
+        }),
+    },
+    {
+        .name = "usb-dmac1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR3,
+            .bit = 31,
+        }),
+    },
+    {
+        .name = "rwdt",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR4,
+            .bit = 2,
+        }),
+    },
+    {
+        .name = "intc-ex",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR4,
+            .bit = 7,
+        }),
+    },
+    {
+        .name = "intc-ap",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR4,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "audmac1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 1,
+        }),
+    },
+    {
+        .name = "audmac0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 2,
+        }),
+    },
+    {
+        .name = "drif31",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "drif30",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 9,
+        }),
+    },
+    {
+        .name = "drif21",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "drif20",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "drif11",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 12,
+        }),
+    },
+    {
+        .name = "drif10",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 13,
+        }),
+    },
+    {
+        .name = "drif01",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 14,
+        }),
+    },
+    {
+        .name = "drif00",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 15,
+        }),
+    },
+    {
+        .name = "hscif4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 16,
+        }),
+    },
+    {
+        .name = "hscif3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 17,
+        }),
+    },
+    {
+        .name = "hscif2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 18,
+        }),
+    },
+    {
+        .name = "hscif1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "hscif0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 20,
+        }),
+    },
+    {
+        .name = "thermal",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 22,
+            .defer_initialization = true,
+        }),
+    },
+    {
+        .name = "pwm",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR5,
+            .bit = 23,
+        }),
+    },
+    {
+        .name = "fcpvd2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 1,
+        }),
+    },
+    {
+        .name = "fcpvd1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 2,
+        }),
+    },
+    {
+        .name = "fcpvd0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 3,
+        }),
+    },
+    {
+        .name = "fcpvb1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 6,
+        }),
+    },
+    {
+        .name = "fcpvb0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 7,
+        }),
+    },
+    {
+        .name = "fcpvi1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "fcpvi0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "fcpf1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 14,
+        }),
+    },
+    {
+        .name = "fcpf0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 15,
+        }),
+    },
+    {
+        .name = "fcpcs",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "vspd2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 21,
+        }),
+    },
+    {
+        .name = "vspd1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 22,
+        }),
+    },
+    {
+        .name = "vspd0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 23,
+        }),
+    },
+    {
+        .name = "vspbc",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 24,
+        }),
+    },
+    {
+        .name = "vspbd",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 26,
+        }),
+    },
+    {
+        .name = "vspi1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 30,
+        }),
+    },
+    {
+        .name = "vspi0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR6,
+            .bit = 31,
+        }),
+    },
+    {
+        .name = "ehci3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 0,
+        }),
+    },
+    {
+        .name = "ehci2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 1,
+        }),
+    },
+    {
+        .name = "ehci1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 2,
+        }),
+    },
+    {
+        .name = "ehci0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 3,
+        }),
+    },
+    {
+        .name = "hsusb",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 4,
+        }),
+    },
+    {
+        .name = "hsusb3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 5,
+        }),
+    },
+    {
+        .name = "cmm3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "cmm2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 9,
+        }),
+    },
+    {
+        .name = "cmm1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "cmm0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "csi20",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 14,
+        }),
+    },
+    {
+        .name = "csi41",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 15,
+        }),
+    },
+    {
+        .name = "csi40",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 16,
+        }),
+    },
+    {
+        .name = "du3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 21,
+        }),
+    },
+    {
+        .name = "du2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 22,
+        }),
+    },
+    {
+        .name = "du1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 23,
+        }),
+    },
+    {
+        .name = "du0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 24,
+        }),
+    },
+    {
+        .name = "lvds",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 27,
+        }),
+    },
+    {
+        .name = "hdmi1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 28,
+        }),
+    },
+    {
+        .name = "hdmi0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR7,
+            .bit = 29,
+        }),
+    },
+    {
+        .name = "vin7",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 4,
+        }),
+    },
+    {
+        .name = "vin6",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 5,
+        }),
+    },
+    {
+        .name = "vin5",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 6,
+        }),
+    },
+    {
+        .name = "vin4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 7,
+        }),
+    },
+    {
+        .name = "vin3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "vin2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 9,
+        }),
+    },
+    {
+        .name = "vin1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "vin0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "etheravb",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 12,
+        }),
+    },
+    {
+        .name = "sata0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 15,
+        }),
+    },
+    {
+        .name = "imr3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 20,
+        }),
+    },
+    {
+        .name = "imr2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 21,
+        }),
+    },
+    {
+        .name = "imr1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 22,
+        }),
+    },
+    {
+        .name = "imr0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR8,
+            .bit = 23,
+        }),
+    },
+    {
+        .name = "gpio7",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 5,
+        }),
+    },
+    {
+        .name = "gpio6",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 6,
+        }),
+    },
+    {
+        .name = "gpio5",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 7,
+        }),
+    },
+    {
+        .name = "gpio4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "gpio3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 9,
+        }),
+    },
+    {
+        .name = "gpio2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "gpio1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "gpio0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 12,
+        }),
+    },
+    {
+        .name = "can-fd",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 14,
+        }),
+    },
+    {
+        .name = "can-if1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 15,
+        }),
+    },
+    {
+        .name = "can-if0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 16,
+        }),
+    },
+    {
+        .name = "i2c6",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 18,
+        }),
+    },
+    {
+        .name = "i2c5",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "i2c-dvfs",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 26,
+        }),
+    },
+    {
+        .name = "i2c4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 27,
+        }),
+    },
+    {
+        .name = "i2c3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 28,
+        }),
+    },
+    {
+        .name = "i2c2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 29,
+        }),
+    },
+    {
+        .name = "i2c1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 30,
+        }),
+    },
+    {
+        .name = "i2c0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR9,
+            .bit = 31,
+        }),
+    },
+    {
+        .name = "ssi-all",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 5,
+        }),
+    },
+    {
+        .name = "ssi9",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 6,
+        }),
+    },
+    {
+        .name = "ssi8",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 7,
+        }),
+    },
+    {
+        .name = "ssi7",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 8,
+        }),
+    },
+    {
+        .name = "ssi6",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 9,
+        }),
+    },
+    {
+        .name = "ssi5",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 10,
+        }),
+    },
+    {
+        .name = "ssi4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 11,
+        }),
+    },
+    {
+        .name = "ssi3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 12,
+        }),
+    },
+    {
+        .name = "ssi2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 13,
+        }),
+    },
+    {
+        .name = "ssi1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 14,
+        }),
+    },
+    {
+        .name = "ssi0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 15,
+        }),
+    },
+    {
+        .name = "scu-all",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 17,
+        }),
+    },
+    {
+        .name = "scu-dvc1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 18,
+        }),
+    },
+    {
+        .name = "scu-dvc0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 19,
+        }),
+    },
+    {
+        .name = "scu-ctu1-mix1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 20,
+        }),
+    },
+    {
+        .name = "scu-ctu0-mix0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 21,
+        }),
+    },
+    {
+        .name = "scu-src9",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 22,
+        }),
+    },
+    {
+        .name = "scu-src8",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 23,
+        }),
+    },
+    {
+        .name = "scu-src7",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 24,
+        }),
+    },
+    {
+        .name = "scu-src6",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 25,
+        }),
+    },
+    {
+        .name = "scu-src5",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 26,
+        }),
+    },
+    {
+        .name = "scu-src4",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 27,
+        }),
+    },
+    {
+        .name = "scu-src3",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 28,
+        }),
+    },
+    {
+        .name = "scu-src2",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 29,
+        }),
+    },
+    {
+        .name = "scu-src1",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 30,
+        }),
+    },
+    {
+        .name = "scu-src0",
+        .data = &((struct mod_rcar_mstp_clock_dev_config){
+            .control_reg = CPG_SMSTPCR10,
+            .bit = 31,
+        }),
+    },
+    { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id)
+{
+    return pik_clock_element_table;
+}
+
+/* TFA mstp clock default value. */
+struct fwk_module_config config_rcar_mstp_clock = {
+    .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table),
+    .data = &((struct mod_rcar_mstp_clock_init){
+        .smstpcr_init = { 0x00210000,
+                          0xFFFFFFFF,
+                          0x040E2FDC,
+                          0xFFFFFBDF,
+                          0x80000004,
+                          0xC3FFFFFF,
+                          0xFFFFFFFF,
+                          0xFFFFFFFF,
+                          0x01F1FFF5,
+                          0xFFFFFFFF,
+                          0xFFFEFFE0,
+                          0x000000B7 },
+    }),
+};