diff options
| author | Aditya Angadi <aditya.angadi@arm.com> | 2020-11-04 14:17:00 +0530 |
|---|---|---|
| committer | Thomas Abraham <thomas.abraham@arm.com> | 2020-11-28 01:48:28 +0530 |
| commit | 029440da65148fcc3a9d02967001adab3dbe8055 (patch) | |
| tree | fe938205379cb9a017625dca02cc4fc3f2c37b93 | |
| parent | 11d30407a17919deb6aec54c8443b18772e6dc40 (diff) | |
product/rdn2: add SCP PIK register space declaration
SCP PIK includes registers for various system configuration and status.
SCP PIK is first one to come out of reset and it generates all the reset
conrols for SCP. Add the register space declaration for SCP PIK and the
subsequent base address from element management peripheral space.
Change-Id: Ic4c61d07875092d045b1e97b01b74811ffb1500b
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
| -rw-r--r-- | product/rdn2/include/scp_css_mmap.h | 2 | ||||
| -rw-r--r-- | product/rdn2/include/scp_mmap.h | 1 | ||||
| -rw-r--r-- | product/rdn2/include/scp_pik.h | 98 |
3 files changed, 101 insertions, 0 deletions
diff --git a/product/rdn2/include/scp_css_mmap.h b/product/rdn2/include/scp_css_mmap.h index fe9e2fe0..66842766 100644 --- a/product/rdn2/include/scp_css_mmap.h +++ b/product/rdn2/include/scp_css_mmap.h @@ -14,4 +14,6 @@ #define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) +#define SCP_PIK_SCP_BASE (SCP_PIK_BASE) + #endif /* SCP_CSS_MMAP_H */ diff --git a/product/rdn2/include/scp_mmap.h b/product/rdn2/include/scp_mmap.h index e9aeb39f..3bf67a15 100644 --- a/product/rdn2/include/scp_mmap.h +++ b/product/rdn2/include/scp_mmap.h @@ -13,6 +13,7 @@ #define SCP_SOC_EXPANSION1_BASE 0x01000000 #define SCP_DTC_RAM_BASE 0x20000000 #define SCP_PERIPHERAL_BASE 0x44000000 +#define SCP_PIK_BASE 0x50000000 #define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000 #endif /* SCP_MMAP_H */ diff --git a/product/rdn2/include/scp_pik.h b/product/rdn2/include/scp_pik.h new file mode 100644 index 00000000..15e1c839 --- /dev/null +++ b/product/rdn2/include/scp_pik.h @@ -0,0 +1,98 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP PIK registers + */ + +#ifndef SCP_PIK_H +#define SCP_PIK_H + +#include "scp_css_mmap.h" + +#include <fwk_macros.h> + +#include <stdint.h> + +/*! + * \brief SCP PIK register definitions + */ +struct pik_scp_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0xA10 - 0x828]; + FWK_R uint32_t PLL_STATUS[17]; + uint8_t RESERVED8[0xA60 - 0xA54]; + FWK_R uint32_t CONS_MMUTCU_INT_STATUS; + FWK_R uint32_t CONS_MMUTCU_INT_CLR; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; + FWK_R uint32_t CONS_MMUTBU_INT_CLR0; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; + FWK_R uint32_t CONS_MMUTBU_INT_CLR1; + FWK_RW uint32_t CONS_MMUTBU_INT_STATUS2; + FWK_RW uint32_t CONS_MMUTBU_INT_CLR2; + FWK_RW uint32_t CONS_MMUTBU_INT_STATUS3; + FWK_RW uint32_t CONS_MMUTBU_INT_CLR3; + FWK_RW uint32_t CONS_MMUTBU_INT_STATUS4; + FWK_RW uint32_t CONS_MMUTBU_INT_CLR4; + FWK_RW uint32_t CONS_MMUTBU_INT_STATUS5; + FWK_RW uint32_t CONS_MMUTBU_INT_CLR5; + uint8_t RESERVED9[0xB20 - 0xA98]; + FWK_R uint32_t CPU_PPU_INT_STATUS[4]; + uint8_t RESERVED10[0xB40 - 0xB30]; + FWK_R uint32_t CLUS_PPU_INT_STATUS[4]; + uint8_t RESERVED11[0xB80 - 0xB50]; + FWK_R uint32_t TIMER_INT_STATUS[8]; + FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; + uint8_t RESERVED12[0xBC0 - 0xBA0]; + FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; + FWK_R uint32_t CONS_CLUS_SCF_INT_STATUSx[4]; + uint8_t RESERVED13[0xFC0 - 0xC10]; + FWK_R uint32_t POWER_CONTROL_CONFIG; + uint8_t RESERVED14[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) +#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) +#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) +#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) + +#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) + +/* Pointer to SCP PIK */ +#define SCP_PIK_PTR ((struct pik_scp_reg *) SCP_PIK_SCP_BASE) + +#endif /* SCP_PIK_H */ |