n1sdp: add the SRIOV and acs override and removing PRI dependency on SVAN1SDP-2020.03.26

Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

4 files changed, 264 insertions, 56 deletions

diff --git a/linux/0001-TMP-iommu-arm-smmu-v3-Ignore-IOPF-capabilities.patch b/linux/0001-TMP-iommu-arm-smmu-v3-Ignore-IOPF-capabilities.patch
new file mode 100644
index 0000000..e1ff4a5
--- /dev/null
+++ b/linux/0001-TMP-iommu-arm-smmu-v3-Ignore-IOPF-capabilities.patch
@@ -0,0 +1,46 @@
+From 4ebcbe09471d6b6b18fce42993489bed3801f10c Mon Sep 17 00:00:00 2001
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Date: Fri, 24 Jan 2020 10:17:14 +0100
+Subject: [PATCH 1/4] TMP: iommu/arm-smmu-v3: Ignore IOPF capabilities
+
+Don't mandate PRI or stall to enable SVA. Some devices have their own
+method for managing I/O page faults when they notice a translation
+request that fails.
+
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+---
+ drivers/iommu/arm-smmu-v3.c | 18 +++++++++++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
+index fed6a9d5867e..a8d7d6ccbb21 100644
+--- a/drivers/iommu/arm-smmu-v3.c
++++ b/drivers/iommu/arm-smmu-v3.c
+@@ -3276,7 +3276,23 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master)
+ 
+ static bool arm_smmu_iopf_supported(struct arm_smmu_master *master)
+ {
+-	return master->stall_enabled || master->pri_supported;
++	/* return master->stall_enabled || master->pri_supported; */
++
++	/*
++	 * FIXME: this temporary hack allows enabling SVA for any endpoint even
++	 * when they don't have PRI/stall.
++	 *
++	 * To implement this more cleanly, we need a third method, complementing
++	 * stall_enabled and pri_supported, to enable IOPF. A bit that says
++	 * "this device's page faults are handled out of band", called for
++	 * example master->oob_iopf. How to set it?  It can easily be a firmware
++	 * quirk, but that does not suffice in my opinion. We need to know that
++	 * there is software ready to handle these page faults. The device
++	 * driver owning this endpoint could for example call
++	 * iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_OOB_IOPF), before
++	 * enabling IOMMU_DEV_FEAT_SVA.
++	 */
++	return true;
+ }
+ 
+ static void arm_smmu_enable_ats(struct arm_smmu_master *master)
+-- 
+2.25.0
+
diff --git a/linux/0002-pci_quirk-add-acs-override-for-PCI-devices.patch b/linux/0002-pci_quirk-add-acs-override-for-PCI-devices.patch
new file mode 100644
index 0000000..a66083a
--- /dev/null
+++ b/linux/0002-pci_quirk-add-acs-override-for-PCI-devices.patch
@@ -0,0 +1,156 @@
+From 224e4adc6bc6a23f5deb3e1ebea03a85e3cad606 Mon Sep 17 00:00:00 2001
+From: Manoj Kumar <manoj.kumar3@arm.com>
+Date: Mon, 3 Feb 2020 10:11:19 +0000
+Subject: [PATCH 2/4] pci_quirk: add acs override for PCI devices
+
+Patch taken from:
+https://gitlab.com/Queuecumber/linux-acs-override/raw/master/workspaces/5.4/acso.patch
+
+Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
+---
+ .../admin-guide/kernel-parameters.txt         |   9 ++
+ drivers/pci/quirks.c                          | 101 ++++++++++++++++++
+ 2 files changed, 110 insertions(+)
+
+diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
+index 8d7932502edc..f2be8337e98c 100644
+--- a/Documentation/admin-guide/kernel-parameters.txt
++++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -3423,6 +3423,15 @@
+ 		nomsi		[MSI] If the PCI_MSI kernel config parameter is
+ 				enabled, this kernel boot option can be used to
+ 				disable the use of MSI interrupts system-wide.
++		pcie_acs_override =
++					[PCIE] Override missing PCIe ACS support for:
++				downstream
++					All downstream ports - full ACS capabilities
++				multfunction
++					All multifunction devices - multifunction ACS subset
++				id:nnnn:nnnn
++					Specfic device - full ACS capabilities
++					Specified as vid:did (vendor/device ID) in hex
+ 		noioapicquirk	[APIC] Disable all boot interrupt quirks.
+ 				Safety option to keep boot IRQs enabled. This
+ 				should never be necessary.
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index d134e12aab9d..9067bc7833be 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -3494,6 +3494,106 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
+ 	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
+ }
+ 
++static bool acs_on_downstream;
++static bool acs_on_multifunction;
++
++#define NUM_ACS_IDS 16
++struct acs_on_id {
++	unsigned short vendor;
++	unsigned short device;
++};
++static struct acs_on_id acs_on_ids[NUM_ACS_IDS];
++static u8 max_acs_id;
++
++static __init int pcie_acs_override_setup(char *p)
++{
++	if (!p)
++		return -EINVAL;
++
++	while (*p) {
++		if (!strncmp(p, "downstream", 10))
++			acs_on_downstream = true;
++		if (!strncmp(p, "multifunction", 13))
++			acs_on_multifunction = true;
++		if (!strncmp(p, "id:", 3)) {
++			char opt[5];
++			int ret;
++			long val;
++
++			if (max_acs_id >= NUM_ACS_IDS - 1) {
++				pr_warn("Out of PCIe ACS override slots (%d)\n",
++						NUM_ACS_IDS);
++				goto next;
++			}
++
++			p += 3;
++			snprintf(opt, 5, "%s", p);
++			ret = kstrtol(opt, 16, &val);
++			if (ret) {
++				pr_warn("PCIe ACS ID parse error %d\n", ret);
++				goto next;
++			}
++			acs_on_ids[max_acs_id].vendor = val;
++
++			p += strcspn(p, ":");
++			if (*p != ':') {
++				pr_warn("PCIe ACS invalid ID\n");
++				goto next;
++			}
++
++			p++;
++			snprintf(opt, 5, "%s", p);
++			ret = kstrtol(opt, 16, &val);
++			if (ret) {
++				pr_warn("PCIe ACS ID parse error %d\n", ret);
++				goto next;
++			}
++			acs_on_ids[max_acs_id].device = val;
++			max_acs_id++;
++		}
++next:
++		p += strcspn(p, ",");
++		if (*p == ',')
++			p++;
++	}
++
++	if (acs_on_downstream || acs_on_multifunction || max_acs_id)
++		pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");
++
++	return 0;
++}
++early_param("pcie_acs_override", pcie_acs_override_setup);
++
++static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)
++{
++	int i;
++
++	/* Never override ACS for legacy devices or devices with ACS caps */
++	if (!pci_is_pcie(dev) ||
++		pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))
++			return -ENOTTY;
++
++	for (i = 0; i < max_acs_id; i++)
++		if (acs_on_ids[i].vendor == dev->vendor &&
++			acs_on_ids[i].device == dev->device)
++				return 1;
++
++	switch (pci_pcie_type(dev)) {
++	case PCI_EXP_TYPE_DOWNSTREAM:
++	case PCI_EXP_TYPE_ROOT_PORT:
++		if (acs_on_downstream)
++			return 1;
++		break;
++	case PCI_EXP_TYPE_ENDPOINT:
++	case PCI_EXP_TYPE_UPSTREAM:
++	case PCI_EXP_TYPE_LEG_END:
++	case PCI_EXP_TYPE_RC_END:
++		if (acs_on_multifunction && dev->multifunction)
++			return 1;
++	}
++
++	return -ENOTTY;
++}
+ /*
+  * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
+  * The device will throw a Link Down error on AER-capable systems and
+@@ -4674,6 +4774,7 @@ static const struct pci_dev_acs_enabled {
+ 	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
+ 	/* Amazon Annapurna Labs */
+ 	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
++   { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
+ 	{ 0 }
+ };
+ 
+-- 
+2.25.0
+
diff --git a/linux/pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch b/linux/0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch
index cc8adc6..d827e9d 100755..100644
--- a/linux/pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch
+++ b/linux/0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch
@@ -1,55 +1,7 @@
-From patchwork Mon Dec  9 16:06:38 2019
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-To: Bjorn Helgaas <bhelgaas@google.com>,
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
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-Cc: "Rafael J . Wysocki" <rjw@rjwysocki.net>,
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-Subject: [PATCH] pcie: Add quirk for the Arm Neoverse N1SDP platform
-Date: Mon,  9 Dec 2019 16:06:38 +0000
-Message-Id: <20191209160638.141431-1-andre.przywara@arm.com>
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-
+From 813f6c6015c75caf25553cd2e36361bac9151145 Mon Sep 17 00:00:00 2001
 From: Deepak Pandey <Deepak.Pandey@arm.com>
+Date: Mon, 9 Dec 2019 16:06:38 +0000
+Subject: [PATCH 3/4] pcie: Add quirk for the Arm Neoverse N1SDP platform
 
 The Arm N1SDP SoC suffers from some PCIe integration issues, most
 prominently config space accesses to not existing BDFs being answered
@@ -83,7 +35,7 @@ Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  create mode 100644 drivers/pci/controller/pcie-n1sdp.c
 
 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index 6a83ba2aea3e..58124ef5070b 100644
+index 619a892148fb..56f00e82a4c4 100644
 --- a/arch/arm64/configs/defconfig
 +++ b/arch/arm64/configs/defconfig
 @@ -177,6 +177,7 @@ CONFIG_NET_9P=y
@@ -113,10 +65,10 @@ index 6b347d9920cc..7a2b41b9ab57 100644
  
  static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
 diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
-index c77069c8ee5d..45700d32f02e 100644
+index 70e078238899..03860176e339 100644
 --- a/drivers/pci/controller/Kconfig
 +++ b/drivers/pci/controller/Kconfig
-@@ -37,6 +37,17 @@ config PCI_FTPCI100
+@@ -65,6 +65,17 @@ config PCI_FTPCI100
  	depends on OF
  	default ARCH_GEMINI
  
@@ -135,10 +87,10 @@ index c77069c8ee5d..45700d32f02e 100644
  	bool "NVIDIA Tegra PCIe controller"
  	depends on ARCH_TEGRA || COMPILE_TEST
 diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
-index 3d4f597f15ce..5f47fefbd67d 100644
+index a2a22c9d91af..7ea98c5a04ec 100644
 --- a/drivers/pci/controller/Makefile
 +++ b/drivers/pci/controller/Makefile
-@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+@@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
  obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
  obj-$(CONFIG_VMD) += vmd.o
@@ -361,3 +313,6 @@ index a73164c85e78..03cdea69f4e8 100644
  #endif
  
  #ifdef CONFIG_PCI_HOST_COMMON
+-- 
+2.25.0
+
diff --git a/linux/0004-n1sdp-update-n1sdp-pci-quirk-for-SR-IOV-support.patch b/linux/0004-n1sdp-update-n1sdp-pci-quirk-for-SR-IOV-support.patch
new file mode 100644
index 0000000..6fb2dac
--- /dev/null
+++ b/linux/0004-n1sdp-update-n1sdp-pci-quirk-for-SR-IOV-support.patch
@@ -0,0 +1,51 @@
+From 7bcc0412428050b0ab1fd70cbb4aaead5ac3c0e5 Mon Sep 17 00:00:00 2001
+From: Manoj Kumar <manoj.kumar3@arm.com>
+Date: Wed, 29 Jan 2020 17:21:39 +0000
+Subject: [PATCH 4/4] n1sdp: update n1sdp pci quirk for SR-IOV support
+
+VFs are not probing the vendor ID first, which is otherwise
+the gate keeper for undiscovered devices. So any accesses using
+a config space offset greater than 0 must be coming for an
+already discovered device or from a VF that has just been created.
+
+Also if Linux already has a struct pci_dev* for a given BDF,
+this device is safe to access.
+
+Skip the firmware table in these cases and allow accesses to
+those devices. That enables SR-IOV support on the N1SDP board.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/pci/controller/pcie-n1sdp.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
+index 620ab221466c..04c0de043817 100644
+--- a/drivers/pci/controller/pcie-n1sdp.c
++++ b/drivers/pci/controller/pcie-n1sdp.c
+@@ -61,6 +61,7 @@ static void __iomem *pci_n1sdp_map_bus(struct pci_bus *bus, unsigned int devfn,
+ 	unsigned int segment = bus->domain_nr;
+ 	unsigned int bdf_addr;
+ 	unsigned int table_count, i;
++	struct pci_dev *dev;
+ 
+ 	if (segment >= MAX_SEGMENTS ||
+ 	    busn < cfg->busr.start || busn > cfg->busr.end)
+@@ -70,6 +71,14 @@ static void __iomem *pci_n1sdp_map_bus(struct pci_bus *bus, unsigned int devfn,
+ 	if (busn == 0 && devfn == 0)
+ 		return rc_remapped_addr[segment] + where;
+ 
++	dev = pci_get_domain_bus_and_slot(segment, busn, devfn);
++	if (dev && dev->is_virtfn)
++		return pci_ecam_map_bus(bus, devfn, where);
++
++	/* Accesses beyond the vendor ID always go to existing devices. */
++	if (where > 0)
++		return pci_ecam_map_bus(bus, devfn, where);
++
+ 	busn -= cfg->busr.start;
+ 	bdf_addr = (busn << cfg->ops->bus_shift) + (devfn << devfn_shift);
+ 	table_count = pcie_discovery_data[segment]->nr_bdfs;
+-- 
+2.25.0
+