diff options
author | Ryan Harkin <ryan.harkin@linaro.org> | 2017-08-09 16:49:54 +0100 |
---|---|---|
committer | Ryan Harkin <ryan.harkin@linaro.org> | 2017-08-09 16:49:54 +0100 |
commit | d370796fcf675ad6433c5f6e19a6cf8292640f2e (patch) | |
tree | 76f7126ebe0157deecc93367f1769c8c3f8f2c7c | |
parent | 780c621cf8bfad5e7e1f8fd7fc71b27a6da10502 (diff) | |
parent | 8c1c62338852fa8cb1476042b17bda391835b73b (diff) |
Merge branch '4.4-armlt-fvp' into lsk-4.4-armltlsk-4.4-armlt-20170809lsk-4.4-armlt
-rw-r--r-- | arch/arm/boot/dts/Makefile | 1 | ||||
l--------- | arch/arm/boot/dts/fvp-base-aemv8a-aemv8a-t1.dts | 1 | ||||
l--------- | arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dtsi | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/arm/Makefile | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a-t1.dts | 41 | ||||
-rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts | 227 | ||||
-rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dtsi | 226 |
7 files changed, 275 insertions, 224 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c0b1035279f8..3fa1c677d306 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,7 @@ dtb-$(CONFIG_ARCH_VERSATILE) += \ versatile-pb.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += \ fvp-base-aemv8a-aemv8a.dtb \ + fvp-base-aemv8a-aemv8a-t1.dtb \ juno.dtb \ juno-r1.dtb \ juno-r2.dtb \ diff --git a/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a-t1.dts b/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a-t1.dts new file mode 120000 index 000000000000..dbf3dd47ea72 --- /dev/null +++ b/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a-t1.dts @@ -0,0 +1 @@ +../../../arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a-t1.dts
\ No newline at end of file diff --git a/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dtsi b/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dtsi new file mode 120000 index 000000000000..839612c10555 --- /dev/null +++ b/arch/arm/boot/dts/fvp-base-aemv8a-aemv8a.dtsi @@ -0,0 +1 @@ +../../../arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dtsi
\ No newline at end of file diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 7531001f6321..341edec915b0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -1,5 +1,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-aemv8a-aemv8a.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-aemv8a-aemv8a.dtb fvp-base-aemv8a-aemv8a-t1.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb diff --git a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a-t1.dts b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a-t1.dts new file mode 100644 index 000000000000..6d9e46e9202d --- /dev/null +++ b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a-t1.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +#include "fvp-base-aemv8a-aemv8a.dtsi" + +&CPU0_0 { + reg = <0x0 0x0>; +}; + +&CPU0_1 { + reg = <0x0 0x100>; +}; + +&CPU0_2 { + reg = <0x0 0x200>; +}; + +&CPU0_3 { + reg = <0x0 0x300>; +}; + +&CPU1_0 { + reg = <0x0 0x10000>; +}; + +&CPU1_1 { + reg = <0x0 0x10100>; +}; + +&CPU1_2 { + reg = <0x0 0x10200>; +}; + +&CPU1_3 { + reg = <0x0 0x10300>; +}; diff --git a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts index c88dc9a62585..a12c1c1d9f8c 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dts @@ -1,228 +1,9 @@ /* - * ARM Ltd. Fixed Virtual Platform (FVP) Base model with dual cluster - * Architecture Envelope Model (AEM) v8-A CPUs + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "FVP_Base_AEMv8A-AEMv8A"; - compatible = "arm,fvp-base,aemv8a-aemv8a", "arm,fvp-base"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &bp_serial0; - serial1 = &bp_serial1; - serial2 = &bp_serial2; - serial3 = &bp_serial3; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0_0>; - }; - core1 { - cpu = <&CPU0_1>; - }; - core2 { - cpu = <&CPU0_2>; - }; - core3 { - cpu = <&CPU0_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU1_0>; - }; - core1 { - cpu = <&CPU1_1>; - }; - core2 { - cpu = <&CPU1_2>; - }; - core3 { - cpu = <&CPU1_3>; - }; - }; - }; - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - CPU0_0: cpu@0 { - compatible = "arm,armv8"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU0_1: cpu@1 { - compatible = "arm,armv8"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU0_2: cpu@2 { - compatible = "arm,armv8"; - reg = <0x0 0x2>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU0_3: cpu@3 { - compatible = "arm,armv8"; - reg = <0x0 0x3>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU1_0: cpu@100 { - compatible = "arm,armv8"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU1_1: cpu@101 { - compatible = "arm,armv8"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU1_2: cpu@102 { - compatible = "arm,armv8"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU1_3: cpu@103 { - compatible = "arm,armv8"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CLUSTER0_L2: l2-cache0 { - compatible = "cache"; - }; - - CLUSTER1_L2: l2-cache1 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CPU0_0>, - <&CPU0_1>, - <&CPU0_2>, - <&CPU0_3>, - <&CPU1_0>, - <&CPU1_1>, - <&CPU1_2>, - <&CPU1_3>; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0x0 0x10000>, - <0x0 0x2f100000 0x0 0x100000>, - <0x0 0x2c000000 0x0 0x2000>, - <0x0 0x2c010000 0x0 0x2000>, - <0x0 0x2c02f000 0x0 0x2000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2f020000 0x0 0x20000>; - }; - }; - - #include "fvp-base.dtsi" -}; - -&hdlcd { - status = "disabled"; -}; - +#include "fvp-base-aemv8a-aemv8a.dtsi" diff --git a/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dtsi b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dtsi new file mode 100644 index 000000000000..13608d82982c --- /dev/null +++ b/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dtsi @@ -0,0 +1,226 @@ +/* + * ARM Ltd. Fixed Virtual Platform (FVP) Base model with dual cluster + * Architecture Envelope Model (AEM) v8-A CPUs + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "FVP_Base_AEMv8A-AEMv8A"; + compatible = "arm,fvp-base,aemv8a-aemv8a", "arm,fvp-base"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &bp_serial0; + serial1 = &bp_serial1; + serial2 = &bp_serial2; + serial3 = &bp_serial3; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0_0>; + }; + core1 { + cpu = <&CPU0_1>; + }; + core2 { + cpu = <&CPU0_2>; + }; + core3 { + cpu = <&CPU0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU1_0>; + }; + core1 { + cpu = <&CPU1_1>; + }; + core2 { + cpu = <&CPU1_2>; + }; + core3 { + cpu = <&CPU1_3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + }; + }; + + CPU0_0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU0_1: cpu@1 { + compatible = "arm,armv8"; + reg = <0x0 0x1>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU0_2: cpu@2 { + compatible = "arm,armv8"; + reg = <0x0 0x2>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU0_3: cpu@3 { + compatible = "arm,armv8"; + reg = <0x0 0x3>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_0: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_1: cpu@101 { + compatible = "arm,armv8"; + reg = <0x0 0x101>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_2: cpu@102 { + compatible = "arm,armv8"; + reg = <0x0 0x102>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1_3: cpu@103 { + compatible = "arm,armv8"; + reg = <0x0 0x103>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CLUSTER0_L2: l2-cache0 { + compatible = "cache"; + }; + + CLUSTER1_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU0_0>, + <&CPU0_1>, + <&CPU0_2>, + <&CPU0_3>, + <&CPU1_0>, + <&CPU1_1>, + <&CPU1_2>, + <&CPU1_3>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0x0 0x10000>, + <0x0 0x2f100000 0x0 0x100000>, + <0x0 0x2c000000 0x0 0x2000>, + <0x0 0x2c010000 0x0 0x2000>, + <0x0 0x2c02f000 0x0 0x2000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x2f020000 0x0 0x20000>; + }; + }; + + #include "fvp-base.dtsi" +}; + +&hdlcd { + status = "disabled"; +}; + |