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2016-08-30BaseTools: UpdateImageSize include Image auth info for FMP Auth capsuleYonghong Zhu
Per UEFI spec UpdateImageSize may or may not include Firmware Image Authentication information. so for FMP auth capsule, UpdateImageSize should include the Image auth info. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-23BaseTools/GenFw: ignore dynamic RELA sectionsArd Biesheuvel
When building PIE (ET_DYN) executables, an additional RELA section is emitted (in addition to the per-section .rela.text and .rela.data sections) that is intended to be resolved at runtime by a ET_DYN compatible loader. At the moment, due to the fact that we don't support GOT based relocations, this dynamic RELA section only contains relocations that are redundant, i.e., each R_xxx_RELATIVE relocation it contains duplicates a R_xxx_xx64 relocation appearing in .rela.text or .rela.data, and so we can simply ignore this section (and we already ignore it in practice due to the fact that it points to the NULL section, which has the SHF_ALLOC bit cleared). For example, Section Headers: [Nr] Name Type Address Offset Size EntSize Flags Link Info Align [ 0] NULL 0000000000000000 00000000 0000000000000000 0000000000000000 0 0 0 [ 1] .text PROGBITS 0000000000000240 000000c0 000000000000427c 0000000000000008 AX 0 0 64 [ 2] .rela.text RELA 0000000000000000 00009310 0000000000001bf0 0000000000000018 I 7 1 8 [ 3] .data PROGBITS 00000000000044c0 00004340 00000000000046d0 0000000000000000 WA 0 0 64 [ 4] .rela.data RELA 0000000000000000 0000af00 0000000000000600 0000000000000018 I 7 3 8 [ 5] .rela RELA 0000000000008bc0 00008a10 0000000000000600 0000000000000018 0 0 8 [ 6] .shstrtab STRTAB 0000000000000000 0000b500 0000000000000037 0000000000000000 0 0 1 [ 7] .symtab SYMTAB 0000000000000000 00009010 0000000000000210 0000000000000018 8 17 8 [ 8] .strtab STRTAB 0000000000000000 00009220 00000000000000eb 0000000000000000 0 0 1 Relocation section '.rela.data' at offset 0xaf00 contains 64 entries: Offset Info Type Sym. Value Sym. Name + Addend 000000004800 000100000001 R_X86_64_64 0000000000000240 .text + 3f5b 000000004808 000100000001 R_X86_64_64 0000000000000240 .text + 3f63 000000004810 000100000001 R_X86_64_64 0000000000000240 .text + 3f79 000000004818 000100000001 R_X86_64_64 0000000000000240 .text + 3f90 000000004820 000100000001 R_X86_64_64 0000000000000240 .text + 3fa6 ... Relocation section '.rela' at offset 0x8a10 contains 64 entries: Offset Info Type Sym. Value Sym. Name + Addend 000000004800 000000000008 R_X86_64_RELATIVE 419b 000000004808 000000000008 R_X86_64_RELATIVE 41a3 000000004810 000000000008 R_X86_64_RELATIVE 41b9 000000004818 000000000008 R_X86_64_RELATIVE 41d0 000000004820 000000000008 R_X86_64_RELATIVE 41e6 000000004828 000000000008 R_X86_64_RELATIVE 41ff ... Note that GOT based relocations result in entries that *only* appear in the dynamic .rela section and not in .rela.text or .rela.data. This means two things if we intend to add support for GOT based relocations: - we must check that a dynamic RELA section exists; - we must filter out duplicates between .rela and .rela.xxx, to prevent emitting duplicate fixups into the PE/COFF .reloc section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-23BaseTools GnuMakefile: Update GCC Flags to the specific one with BUILD_ prefixLiming Gao
To avoid the conflict with the default GCC flag name, BUILD_ prefix is added. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-23BaseTools GNU Makefile: Add the missing rules for cpp source fileLiming Gao
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-23BaseTools: update BinaryFiles.txt file to add Pkcs7Sign ToolYonghong Zhu
add Pkcs7Sign.exe and related pem file into BinaryFiles.txt for build server to automatically build the binary win32 files. Cc: Liming Gao <liming.gao@intel.com> CC: Erik Bjorge <erik.c.bjorge@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
2016-08-23BaseTools: add capsule image header for auth FMP capsule fileYonghong Zhu
in last commit 91ae29, it missed to add the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER for the auth FMP capsule. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-23BaseTools/UserManuals: update with new report bug mail addressYonghong Zhu
The .rtf files in BaseTools/UserManuals still tell users to Report bugs to sourceforge mail address. Since we no longer use the sourceforge mailing lists we should update it. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-22BaseTools/GccBase.lds: don't copy RELA section to PE/COFFArd Biesheuvel
The CLANG38 toolchain creates a PIE binary at link time. This is necessary since the LTO code generation may otherwise result in code that cannot execute correctly when loaded above 2 GB. PIE executables contain a RELA section consisting of dynamic relocation entries that are intended for consumption by the loader at runtime. For this reason, it has the SHF_ALLOC attribute set by default, and will be identified by GenFw as a section that needs to be copied into the PE/COFF binary, resulting in waste of space since the PE/COFF loader does not use this data at all. So mark the RELA section as informational: this will prevent the linker from setting the SHF_ALLOC attribute, causing GenFw to ignore it. DxeCore.efi before: Detected 'X64' type PE/COFF image consisting of 3 sections Section alignment: 0x40 File alignment: 0x40 Section '.text' @ 0x00000240 File offset: 0x240 Virtual size: 0x21000 Raw size: 0x21000 Section '.data' @ 0x00021240 File offset: 0x21240 Virtual size: 0x3640 Raw size: 0x3640 Section '.reloc' @ 0x00024880 File offset: 0x24880 Virtual size: 0x280 Raw size: 0x280 DxeCore.efi after: Detected 'X64' type PE/COFF image consisting of 3 sections Section alignment: 0x40 File alignment: 0x40 Section '.text' @ 0x00000240 File offset: 0x240 Virtual size: 0x1f440 Raw size: 0x1f440 Section '.data' @ 0x0001f680 File offset: 0x1f680 Virtual size: 0x3640 Raw size: 0x3640 Section '.reloc' @ 0x00022cc0 File offset: 0x22cc0 Virtual size: 0x280 Raw size: 0x280 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-22BaseTools PeCoffLib: Fix the issue to get RelocationsStripped from TE imageLiming Gao
If PE image has no relocation section, and has not set RELOCS_STRIPPED, after it is converted to TE image, GenFw will set its relocation section VirtualAddress to non-zero address, and keep Size value as Zero. MdePkg BasePeCoffLib applied this rule to get RelocationsStripped attribute. But, it is missing in BaseTools BasePeCoffLib. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-19BaseTools: Fix a bug use 'COMMON' as CodeBase in BuildOptions sectionYonghong Zhu
Current BaseTools query the BuildOptions not cover the case that use 'COMMON' as CodeBase, while DSC spec allow this usage. This Patch add support for such 'common.DXE_RUNTIME_DRIVER' as the Scope2 in the query Condition. Cc: Liming Gao <liming.gao@intel.com> Cc: Kurt Kennett <Kurt.Kennett@microsoft.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-19BaseTools: FMP capsule add the support to generate auth infoYonghong Zhu
Current BaseTools cannot generate EFI_FIRMWARE_IMAGE_AUTHENTICATION for FMP capsule. this patch fix it by FDF spec's update to add the definition for CERTIFICATE_GUID and MONOTONIC_COUNT. BaseTools call the tool by CERTIFICATE_GUID to generate the certdata and fill the header info. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-19BaseTools: Rsa2048Sha256Sign add new option to support Monotonic countYonghong Zhu
the EFI_FIRMWARE_IMAGE_AUTHENTICATION struct require the AuthInfo which is a signature across the image data and the Monotonic Count value, so we add the new option to support Monotonic count. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-19BaseTools: Add the PKCS7 toolYonghong Zhu
Provide the PKCS7 Tool to support the CertType - EFI_CERT_TYPE_PKCS7_GUID, then user can use this tool to add EFI_FIRMWARE_IMAGE_AUTHENTICATION for a binary. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-19BaseTools-CLANG38: Add -O3 in DLINK2 flagShi, Steven
CLANG38 build fail after CC_FLAG is added in the link rule. This failure is because the CLANG38 enable the LTO through LLVMgold.so linker plugin, but the LLVMgold.so plugin cannot accept the clang -Oz CC flag as build option. After CC_FLAG is added in the link rule, the LLVMgold.so plugin reports linking error. LLVMgold.so only accept -O0 ~ -O3, and you can see it in the LLVM gold plugin source code in below: http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_380/final/tools/gold/ gold-plugin.cpp line173: if (opt[1] < '0' || opt[1] > '3') message(LDPL_FATAL, "Optimization level must be between 0 and 3"); Add -O3 in the *_CLANG38_*_DLINK2_FLAGS to override the -Oz flag in *_CLANG38_*_CC_FLAGS to pass LLVMgold.so linking. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Steven Shi <steven.shi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-19BaseTools: check CONF_PATH env to get the configure filesYonghong Zhu
Add CONF_PATH env check. First priority is user set the conf dir by --conf option, then the CONF_PATH env, the last one is the standard WORKSPACE(PACKAGE_PATH)/Conf. Also print the conf path directory in the build log. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-14BaseTools/GenFv: Account for rebase of FV section containing VTF fileLeo Duran
Account for rebase of FV section containing VTF file on IA32/IA64. This supports cases where the reset vector may not be set at 0xFFFFFFF0. For example, FV section defined as: [FV.FvSecPei] FvBaseAddress = $(FV_BOOT_BASE) FvForceRebase = TRUE Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-12BaseTools RVCT: ignore various RVC diagnosticsArd Biesheuvel
This updates the RVCT CC flags so various diagnostics that trigger warnings-as-errors are silenced. In particular, RVCT complains about missing newlines at the end of source files, mixing of enums and int values and return statements followed by a break, all of which occur in the Tianocore codebase, but none of which are actual errors in the code. So just silence them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-12BaseTools ARM AARCH64: drop redundant compiler argumentsArd Biesheuvel
The ARM and AARCH64 CC_FLAGS definitions include both GCC_ALL_CC_FLAGS and GCC44_ALL_CC_FLAGS, resulting in many of the compiler arguments being passed twice. Since the CLANG35 definitions do not refer to GCC44_ALL_CC_FLAGS, drop the reference for GCCx as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-12BaseTools ARM AARCH64: pass CC flags to linker for XIP modules as wellArd Biesheuvel
Commit 478f50990a ("BaseTools GCC: add the compiler flags to the linker command line") added the compiler flags to the linker command line, which is required for LTO to function correctly, since it involves code generation at link time. This patch failed to update the build rules for XIP modules on AARCH64, which not only requires the ordinary CC flags but also the XIP CC flags to prevent the LTO backend to, e.g., emit code that does not adhere to the strict alignment rules we impose for code that may execute with the MMU off. So update the XIP link rules as well. Since AARCH64 and ARM are not supported by any toolchains in the GCCLD build rule family, drop the reference to GCCLD while we're at it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-12BaseTool/VfrCompile: Remove reset button opcode in CheckQuestionOpCodeDandan Bi
"EFI_IFR_RESET_BUTTON_OP" is a statement, not a question, so remove it from function CheckQuestionOpCode. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-08-10BaseTools-Conf:Introduce CLANG38 new toolchain for x86Shi, Steven
This adds support for LLVM 3.8.x in LTO mode for IA32 and X64. CLANG38 enable LLVM Link Time Optimization (LTO) and code size optimization flag (-Oz) by default for aggressive code size improvement. CLANG38 X64 code is small code model + PIE. CLANG LTO needs PIE in link flags to generate PIE code correctly, otherwise the PIE is not really enabled. (e.g. OvmfPkgX64 will hang in 64bits SEC at high address because of small model code displacement overflow). Test pass platforms: OVMF (OvmfPkgIa32.dsc, OvmfPkgX64.dsc and OvmfPkgIa32X64.dsc). Test compiler and linker version: LLVM 3.8, GNU ld 2.26. Example steps to use the CLANG38 tool chain to build OVMF platform: 1. Download and extract the llvm 3.8.0 Pre-Built Binaries from http://www.llvm.org/releases/ (e.g. http://www.llvm.org/releases/ 3.8.0/clang+llvm-3.8.0-x86_64-linux-gnu-ubuntu-16.04.tar.xz and extract it as ~/clang38). 2. Copy LLVMgold.so from https://github.com/shijunjing/edk2/blob/ llvm/BaseTools/Bin/LLVMgold.so to above clang lib folder (e.g. ~/clang38/lib/LLVMgold.so) 3. Install new version linker with plugin support (e.g. ld 2.26 in GNU Binutils 2.26 or Ubuntu16.04) $ cd edk2 $ git checkout llvm $ export CLANG38_BIN=path/to/your/clang38/ (e.g. export CLANG38_BIN=~/clang38/bin/) $ source edksetup.sh $ make -C BaseTools/Source/C $ build -t CLANG38 -a X64 -p OvmfPkg/OvmfPkgX64.dsc -n 5 -b DEBUG -DDEBUG_ON_SERIAL_PORT $ cd edk2/Build/OvmfX64/DEBUG_CLANG38/FV $ qemu-system-x86_64.exe -bios OVMF.fd -serial file:serial.log -m 4096 -hda fat:. If you want, you can build and install GNU Binutils 2.26 as below steps in Ubuntu: Download binutils-2.26 source code from http://ftp.gnu.org/gnu/binutils/ and extract it to ~/binutils-2.26 $sudo apt-get install bison $sudo apt-get install flex Install other necessary binutils build tools if missing $ mkdir build $ cd build $ ../binutils-2.26/configure --enable-gold --enable-plugins --disable-werror --prefix=/usr $ make -j 5 $ sudo make install If you want, you can build LLVMgold.so as below steps Download llvm-3.8.0 source code from http://www.llvm.org/releases/ 3.8.0/llvm-3.8.0.src.tar.xz and extract it to ~/llvm-3.8.0.src Download clang3.8.0 source code from http://www.llvm.org/releases/ 3.8.0/cfe-3.8.0.src.tar.xz and extract it to ~/llvm-3.8.0.src/tools/clang Refer http://clang.llvm.org/get_started.html to Install other necessary clang build tools if missing $ mkdir llvm38build $ cd llvm38build If your GNU Binutils 2.26 is in /home/jshi19/binutils-2.26, $ cmake ../llvm-3.8.0.src -G "Unix Makefiles" -DCMAKE_BUILD_TYPE="Release" -DLLVM_TARGETS_TO_BUILD="X86" -DCMAKE_VERBOSE_MAKEFILE=ON -DCMAKE_CXX_COMPILER="/usr/bin/g++" -DCMAKE_C_COMPILER="/usr/bin/gcc" -DLLVM_BINUTILS_INCDIR=/home/jshi19/binutils-2.26/include $ make -j 5 LLVMgold The LLVMgold.so is in ~/llvm38build/lib/LLVMgold.so Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Steven Shi <steven.shi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-10BaseTools-Conf:Remove short dash in ar flag for LLVMShi, Steven
Both binutils ar and LLVM ar support "cr", but LLVM ar doens't support add "-" in the flags, and llvm-ar cannot accept "-cr". So remove the short dash "-" to make llvm archives work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Steven Shi <steven.shi@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-09BaseTools ARM: impose strict alignment only for XIP modulesArd Biesheuvel
Given that we only support ARMv7 and up in Tianocore (due to the fact that the PI spec mandates that the PEI services table pointer be stored in the TPIDRURW register, which is not available on earlier CPUs), we can assume that any code executing with the MMU on may perform unaligned accesses (since the AArch32 bindings in the UEFI spec stipulate that unaligned accesses should be allowed if supported by the CPU) So relax the alignment restrictions to XIP modules only, i.e., BASE, SEC, PEI_CORE and PEIM type modules, exactly like we do for AARCH64 already. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-09BaseTools CLANG35: add missing XIP flags for AARCH64Ard Biesheuvel
When building for AARCH64, code that may execute with the MMU off should not perform unaligned accesses, which is why we set -mstrict-align for BASE, SEC, PEI_CORE and PEIM modules when building with GCCx. However, this setting is missing from CLANG35 so set it there as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-09BaseTools/UPT: Fix a install issueHess Chen
Fix a corner case issue of installing a module without any files which causes installing UNI file failure Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hess Chen <hesheng.chen@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-08BaseTools X64: fold PLT relocations into simple relative referencesArd Biesheuvel
For X64/GCC, we use position independent code with hidden visibility to inform the compiler that symbol references are never resolved at runtime, which removes the need for PLTs and GOTs. However, in some cases, GCC has been reported to still emit PLT based relocations, which we need to handle in the ELF to PE/COFF perform by GenFw. Unlike GOT based relocations, which are non-trivial to handle since the indirections in the code can not be fixed up easily (although relocation types exist for X64 that annotate relocation targets as suitable for relaxation), PLT relocations simply point to jump targets, and we can relax such relocations by resolving them using the symbol directly rather than via a PLT entry that does nothing more than tail call the function we already know it is going to call (since all symbol references are resolved in the same module). So handle R_X86_64_PLT32 as a R_X86_64_PC32 relocation. Suggested-by: Steven Shi <steven.shi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-08BaseTools/VfrCompile: Add two new option for VfrCompileDandan Bi
1.--autodefault option VfrCompile will generate default opcodes for questions if some default are missing. 2 --checkdefault option VfrCompile will check whether every question has no default or has all default. If not, will generate an error to let user know the question misses default. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-08BaseTool/VfrCompile: Add missing question opcodeDandan Bi
The function CheckQuestionOpCode is to check whether the opcode is question opcode, but it misses two question opcodes: 'EFI_IFR_REF_OP' and 'EFI_IFR_RESET_BUTTON'. Now add them. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-08BaseTools: Fix the bug when use FILE_GUID override the module in DSCYonghong Zhu
In last commit 2502b73, it doesn't cover the case that in the DSC file use FILE_GUID to override the module. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-08BaseTools: Allow string token identifier to use lower case lettersYonghong Zhu
This patch is to align the code behavior with UNI spec that string token identifier can use upper case and lower case letters. Cc: Liming Gao <liming.gao@intel.com> Cc: Felix <Felixp@ami.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-05BaseTools GCC/ARM: add -fno-builtin to CC flagsArd Biesheuvel
Avoid build errors when including OpensslLib, which may throw undefined reference errors for builtin functions if -fno-builtin is not specified (and it is already set for IA32, X64 and AARCH64) So set it for ARM as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-03BaseTools GCC: add the compiler flags to the linker command lineArd Biesheuvel
Now that we invoke GCC as the linker for the GCC toolchain family, we can pass the CC flags to the linker as well. This is only required for LTO (which may involve code generation during the link stage), but does not interfere with non-LTO builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-03BaseTools GCC5: disable warnings-as-errors for nowArd Biesheuvel
GCC5 runs in LTO mode, which means it may generate code from an intermediate representation during the link stage, at which time additional diagnostics are run that may emit warnings. Some of these warnings seem to be spurious, e.g., the following warning which is emitted when building OVMF for IA32 or ArmVirtQemu for ARM (but not for X64 resp. AARCH64) .../MdeModulePkg/Library/UefiHiiLib/HiiLib.c: In function 'HiiCreateGuidOpCode.constprop': .../MdeModulePkg/Library/UefiHiiLib/HiiLib.c:3228:10: error: function may return address of local variable [-Werror=return-local-addr] return (UINT8 *)OpCodePointer; ^ .../MdeModulePkg/Library/UefiHiiLib/HiiLib.c:3208:17: note: declared here EFI_IFR_GUID OpCode; ^ lto1: all warnings being treated as errors lto-wrapper: fatal error: gcc returned 1 exit status So before adding the contents of CC_FLAGS to the linker command line, defuse the default '-Werror' by adding '-Wno-error' to DLINK2_FLAGS for GCC5. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-03BaseTools GCC: move -c compiler flag to build rulesArd Biesheuvel
In order to be able to share the compiler flags with the linker (which is required for LTO since it involves the linker doing code generation based on the LTO bytecode), move the -c GCC argument to the build rules, and drop it from the GCC CC_FLAGS definitions in tools_def. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-03BaseTool/Upt: Avoid UNI file name conflictHess Chen
When creating a UNI file if there is a name conflict, add an index from 0 to the file name Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hess Chen <hesheng.chen@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-03BaseTool/UPT: Not expand macro for UserExtensionHess Chen
All MACRO values defined by the DEFINE statements n any section (except [Userextensions] sections other than TianoCore."ExtraFiles) of the INF or DEC file must be expanded before processing of the file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hess Chen <hesheng.chen@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-03BaseTool/Upt: Add support for PrivateHess Chen
Support new syntax in package DEC file as below: [Includes.Common.Private] [Ppis.Common.Private] [Guids.Common.Private] [Protocols.Common.Private] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hess Chen <hesheng.chen@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-03BaseTool/UPT: Add Test InstallHess Chen
Add a new function to test if a DIST file list one by one to see if they can meet the requirement of Dependency. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hess Chen <hesheng.chen@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-02BaseTools: Keep the Pcd order in the Asbuilt Inf is same with SourceYonghong Zhu
The original behavior is that in the Asbuilt inf Pcd's order is base on the Pcd's offset. Now we change the order to keep it is same with the Pcd order in the source inf file. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-02BaseTools AARCH64: override XIP module linker alignment to 32 bytesArd Biesheuvel
Now that GenFw converts small code model ADRP instructions to ADR on the fly, we can reduce the alignment for XIP modules, where large alignment values may cause considerable waste of flash space due to excessive padding. This limits the module size to 1 MB, but this is not a concern in practice. So set the XIP section alignment to 0x20 for DEBUG_GCC49, DEBUG_GCC5 and *_CLANG35, all of which use the small code model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-02BaseTools/GenFw AARCH64: convert ADRP to ADR instructions if binary size ↵Ard Biesheuvel
allows it The ADRP instruction in the AArch64 ISA requires the link time and load time offsets of a binary to be equal modulo 4 KB. The reason is that this instruction always produces a multiple of 4 KB, and relies on a subsequent ADD or LDR instruction to set the offset into the page. The resulting symbol reference only produces the correct value if the symbol in question resides at that exact offset into the page, and so loading the binary at arbitrary offsets is not possible. Due to the various levels of padding when packing FVs into FVs into FDs, this alignment is very costly for XIP code, and so we would like to relax this alignment requirement if possible. Given that symbols that are sufficiently close (within 1 MB) of the reference can also be reached using an ADR instruction which does not suffer from this alignment issue, let's replace ADRP instructions with ADR after linking if the offset can be encoded in this instruction's immediate field. Note that this only makes sense if the section alignment is < 4 KB. Otherwise, replacing the ADRP has no benefit, considering that the subsequent ADD or LDR instruction is retained, and that micro-architectures are more likely to be optimized for ADRP/ADD pairs (i.e., via micro op fusing) than for ADR/ADD pairs, which are non-typical. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-02BaseTools GCC: introduce GCC5 toolchain to support GCC v5.x in LTO modeArd Biesheuvel
This adds support for GCC 5.x in LTO mode for IA32, X64, ARM and AARCH64. Due to the fact that the GCC project switched to a new numbering scheme where the first digit is now incremented for every major release, the new toolchain is simply called 'GCC5', and is intended to support all GCC v5.x releases. Since IA32 and X64 enable compiler optimizations (-Os) for both DEBUG and RELEASE builds, LTO support is equally enabled for both targets. On ARM and AARCH64, DEBUG builds are not optimized, and so the LTO optimizations are only enabled for RELEASE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-02BaseTools GCC: drop GNU notes section from EFI imageArd Biesheuvel
Recent versions of GNU ld automatically emit a .notes section into the ELF binary containing a build id. Since this is an allocatable section by default, it will be identified by GenFw as a section that requires PE/COFF conversion, which may cause sections to be moved around unexpectedly. So retain the section, but tag it as INFO, which tells the linker that it should not be accounted for in the binary's memory layout. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-02BaseTools GCC: use 'gcc' as the linker command for GCC44 and laterArd Biesheuvel
To accommodate upcoming GCCx toolchain versions that require 'gcc' to be used as the linker in order to support LTO, switch GCC44 and later (including CLANG35) to a new DLINK build rule that invokes 'gcc' as the linker instead of 'ld'. Since gcc expects its command line arguments in a different format, and expects arguments that it needs to pass to the linker to be prefixed with '-Wl,', this involves changes to most of the DLINK_FLAGS definitions in tools_def.template, as well as some changes to module .INF files that set their own linker options. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-02BaseTools UNIXGCC ELFGCC CYGGCC: clone GCC build rule family into GCCLDArd Biesheuvel
Before we can make non-backward compatible changes to the GCC build rules regarding the use of the 'gcc' binary as the linker, clone the existing GCC build rules into a 'GCCLD' build rule family, and move the legacy toolchains UNIXGCC, CYGGCC, CYGGCCxASL and ELFGCC over to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-02BaseTools CLANG35: drop problematic use-movt and save-temps optionsArd Biesheuvel
Some versions of Clang fail on every input file when using the -save-temps options, and produces the following heplful error message: <unknown>:0: error: Undefined temporary symbol Simply dropping the option for CLANG35 is the simplest way around this, since the value of storing .i and .s files is dubious anyway. Also, drop the arm-use-movt option, which does not appear to be supported anymore by recent versions of clang. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2016-07-29BaseTools/Ecc: GUID checkpointHess Chen
Fix a bug of checking duplicate GUID Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hess Chen <hesheng.chen@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-07-29BaseTools: Add build info for binary modules that only list in FDF fileYonghong Zhu
If the binary module is list in the FDF file but not list in the DSC file, current build report would not include these binary module's info in the report "Module section". The patch fix this issue. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-07-29BaseTools: Correct ReadMe.txt file with CRLF line endingLiming Gao
Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-07-27BaseTools: report error if source module INF is only list in FDF fileYonghong Zhu
If source module INF is not listed in DSC, it will not be built. And it is listed in FDF, GenFds will fail to find its build output. To reminder user this issue early, build tool should report failure to user in early phase. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
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