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/** @file
Copyright (c) 2018 - 2019, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __N1SDP_PLATFORM_H__
#define __N1SDP_PLATFORM_H__
/***********************************************************************************
// Platform Memory Map
************************************************************************************/
// Onchip Peripherals - UART0
#define N1SDP_UART0_BASE 0x2A400000
#define N1SDP_UART0_SZ 0x00010000
// OnChip Peripherals - UART1
#define N1SDP_UART1_BASE 0x2A410000
#define N1SDP_UART1_SZ 0x00010000
// Onchip Peripherals - Generic Watchdog
#define N1SDP_GENERIC_WDOG_BASE 0x2A440000
#define N1SDP_GENERIC_WDOG_SZ SIZE_128KB
// OnChip MHU
#define N1SDP_MHU_NS_BASE 0x45000000
#define N1SDP_MHU_NS_SIZE 0x00020000
// OnChip MailBox
#define N1SDP_MHU_NS_RAM_BASE 0x45200000
#define N1SDP_MHU_NS_RAM_SIZE 0x00020000
// Onchip Peripherals - GIC(600)
#define N1SDP_GIC_BASE 0x30000000
#define N1SDP_GICR_BASE 0x300C0000
#define N1SDP_GIC_SZ SIZE_256KB
#define N1SDP_GICR_SZ SIZE_1MB
// On-Chip non-secure SRAM
#define N1SDP_NON_SECURE_SRAM_BASE 0x06000000
#define N1SDP_NON_SECURE_SRAM_SZ SIZE_64KB
//AXI Expansion peripherals
#define N1SDP_EXP_PERIPH_BASE 0x1C000000
#define N1SDP_EXP_PERIPH_BASE_SZ 0x1300000
// Platform information structure base address
#define N1SDP_PLAT_INFO_STRUCT_BASE 0x06008000
// Extended memory size for CCIX
#define N1SDP_EXT_MEM_SIZE 0x200000000
#endif
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