1 files changed, 107 insertions, 0 deletions
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
new file mode 100644
index 00000000..33fb7ccc
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+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
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+## @file
+#  Component description file for the CN9130 Development Board (variant A)
+#
+#  Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+  # CP115 count
+  gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+
+  # MPP
+  gMarvellTokenSpaceGuid.PcdMppChipCount|2
+
+  # APN807 MPP
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+  # CP115 #0 MPP
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+  # I2C
+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+  gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+
+  # SPI
+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+  gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+  gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+  # ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+  # ComPhy0
+  # 0: PCIE0         5 Gbps
+  # 1: PCIE0         5 Gbps
+  # 2: PCIE0         5 Gbps
+  # 3: PCIE0         5 Gbps
+  # 4: SFI           10.31 Gbps
+  # 5: SATA1         5 Gbps
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+  # UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+  # MDIO
+  gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+  # PHY
+  gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+  # NET
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+
+  # NonDiscoverableDevices
+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+  # PCIE
+  gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
+
+  # RTC
+  gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+
+  # SoC Configuration Space
+  gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000
+
+  # Variable store
+  gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE