Platform/ARM/N1Sdp: add Ssdt, Iort and Mcfg tables

N1SDP support a  PCIe root complex and it can generate
PCIe ITS-MSI transactions. So the Ssdt, Iort and Mcfg ACPI
tables to desribe this topology to the linux kernel.

Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

4 files changed, 281 insertions, 0 deletions

diff --git a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
index ff047e86..62c1564d 100644
--- a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
+++ b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
@@ -25,8 +25,11 @@
   Dsdt.asl
   Fadt.aslc
   Gtdt.aslc
+  Iort.aslc
   Madt.aslc
+  Mcfg.aslc
   Spcr.aslc
+  Ssdt.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -48,3 +51,20 @@
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusCount
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMax
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMin
+  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoBase
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoMaxBase
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoSize
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoTranslation
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Translation
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Translation
diff --git a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Iort.aslc b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Iort.aslc
new file mode 100644
index 00000000..435117f3
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Iort.aslc
@@ -0,0 +1,107 @@
+/** @file
+*  I/O Remapping Table (Iort)
+*
+*  Copyright (c) 2018, ARM Ltd. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/Acpi60.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include "N1SdpAcpiHeader.h"
+
+#pragma pack(1)
+
+typedef struct
+{
+  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE       ItsNode;
+  UINT32                                   ItsIdentifiers;
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
+
+typedef struct
+{
+  EFI_ACPI_6_0_IO_REMAPPING_RC_NODE        RcNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE       RcIdMap;
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
+
+typedef struct
+{
+  EFI_ACPI_6_0_IO_REMAPPING_TABLE          Header;
+  ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE   ItsNode;
+  ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE    RcNode[1];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+#pragma pack ()
+
+ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
+{
+  // EFI_ACPI_6_0_IO_REMAPPING_TABLE
+  {
+     ARM_ACPI_HEADER  // EFI_ACPI_DESCRIPTION_HEADER
+     (
+       EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+       ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE,
+       EFI_ACPI_IO_REMAPPING_TABLE_REVISION
+     ),
+     2,  // NumNodes
+     sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE),  // NodeOffset
+     0,  // Reserved
+  },
+  // ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE
+  {
+    // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE
+    {
+      // EFI_ACPI_6_0_IO_REMAPPING_NODE
+      {
+        EFI_ACPI_IORT_TYPE_ITS_GROUP,  // Type
+        sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length
+        0,  // Revision
+        0,  // Reserved
+        0,  // NumIdMappings
+        0,  // IdReference
+      },
+      1,    // GIC ITS Identifiers
+    },
+    0,
+  },
+  // ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE-PCIe
+ { {
+    // EFI_ACPI_6_0_IO_REMAPPING_RC_NODE
+    {
+      // EFI_ACPI_6_0_IO_REMAPPING_NODE
+      {
+        EFI_ACPI_IORT_TYPE_ROOT_COMPLEX,  // Type
+        sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE),  // Length
+        0,  // Revision
+        0,  // Reserved
+        1,  // NumIdMappings
+        __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap),  // IdReference
+      },
+      1,  // CacheCoherent
+      0,  // AllocationHints
+      0,  // Reserved
+      0,  // MemoryAccessFlags
+      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,  // AtsAttribute
+      0x0,                                         // PciSegmentNumber
+    },
+    // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE
+    {
+      0x0000,  // InputBase
+      0xffff,  // NumIds
+      0x0000,  // OutputBase
+      __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode),  // OutputReference
+      0,  // Flags
+    },
+  }
+ }
+};
+
+VOID* CONST ReferenceAcpiTable = &Iort;
diff --git a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Mcfg.aslc b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Mcfg.aslc
new file mode 100644
index 00000000..afcfa80d
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Mcfg.aslc
@@ -0,0 +1,58 @@
+/** @file
+*  Memory mapped configuration space base address description table (MCFG)
+*
+*  Copyright (c) 2018, ARM Ltd. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <IndustryStandard/Acpi62.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <Library/PcdLib.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include "N1SdpAcpiHeader.h"
+#include "N1SdpPlatform.h"
+
+#pragma pack(1)
+typedef struct
+{
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[1];
+} EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+#pragma pack()
+
+EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+      EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
+    ),
+    EFI_ACPI_RESERVED_QWORD,  //Reserved
+  },
+  {
+    // PCIe ECAM
+    {
+      FixedPcdGet64 (PcdPcieExpressBaseAddress),             // Base Address
+      0x0,                                                   // Segment Group Number
+      FixedPcdGet32 (PcdPcieBusMin),                         // Start Bus Number
+      FixedPcdGet32 (PcdPcieBusMax),                         // End Bus Number
+      0x00000000,                                            // Reserved
+    },
+   }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Ssdt.asl b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Ssdt.asl
new file mode 100644
index 00000000..a85bb949
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/Ssdt.asl
@@ -0,0 +1,96 @@
+/** @file
+*  Secondary System Description Table (SSDT)
+*
+*  Copyright (c) 2018, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "N1SdpAcpiHeader.h"
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1SDP",
+                EFI_ACPI_ARM_OEM_REVISION)
+{
+  Scope (_SB) {
+    // PCI Root Complex
+    Device(PCI0) {
+      Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+      Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+      Name (_SEG, Zero)              // PCI Segment Group number
+      Name (_BBN, Zero)              // PCI Base Bus Number
+      Name (_CCA, 1)                 // Cache Coherency Attribute
+
+      // Root complex resources
+      Method (_CRS, 0, Serialized) {
+        Name (RBUF, ResourceTemplate () {
+          WordBusNumber (                                       // Bus numbers assigned to this root
+            ResourceProducer,
+            MinFixed,
+            MaxFixed,
+            PosDecode,
+            0,                                                  // AddressGranularity
+            FixedPcdGet32 (PcdPcieBusMin),                      // AddressMinimum - Minimum Bus Number
+            FixedPcdGet32 (PcdPcieBusMax),                      // AddressMaximum - Maximum Bus Number
+            0,                                                  // AddressTranslation - Set to 0
+            FixedPcdGet32 (PcdPcieBusCount)                     // RangeLength - Number of Busses
+          )
+
+          DWordMemory (                               // 32-bit BAR Windows
+            ResourceProducer,
+            PosDecode,
+            MinFixed,
+            MaxFixed,
+            Cacheable,
+            ReadWrite,
+            0x00000000,                               // Granularity
+            FixedPcdGet32 (PcdPcieMmio32Base),        // Min Base Address
+            FixedPcdGet32 (PcdPcieMmio32MaxBase),     // Max Base Address
+            FixedPcdGet32 (PcdPcieMmio32Translation), // Translate
+            FixedPcdGet32 (PcdPcieMmio32Size)         // Length
+          )
+
+          QWordMemory (                               // 64-bit BAR Windows
+            ResourceProducer,
+            PosDecode,
+            MinFixed,
+            MaxFixed,
+            Cacheable,
+            ReadWrite,
+            0x00000000,                               // Granularity
+            FixedPcdGet64 (PcdPcieMmio64Base),        // Min Base Address
+            FixedPcdGet64 (PcdPcieMmio64MaxBase),     // Max Base Address
+            FixedPcdGet64 (PcdPcieMmio64Translation), // Translate
+            FixedPcdGet64 (PcdPcieMmio64Size)         // Length
+          )
+
+          DWordIo (                                   // IO window
+            ResourceProducer,
+            MinFixed,
+            MaxFixed,
+            PosDecode,
+            EntireRange,
+            0x00000000,                               // Granularity
+            FixedPcdGet32 (PcdPcieIoBase),            // Min Base Address
+            FixedPcdGet32 (PcdPcieIoMaxBase),         // Max Base Address
+            FixedPcdGet32 (PcdPcieIoTranslation),     // Translate
+            FixedPcdGet32 (PcdPcieIoSize),            // Length
+            ,
+            ,
+            ,
+            TypeTranslation
+          )
+        }) // Name(RBUF)
+
+        Return (RBUF)
+      } // Method (_CRS)
+    }
+
+  }
+}