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authorHeyi Guo <heyi.guo@linaro.org>2018-01-23 11:59:05 +0800
committerLeif Lindholm <leif.lindholm@linaro.org>2018-02-07 15:37:06 +0000
commitfca814692cc20dd365f145e236311f6a4dd4bb66 (patch)
tree007bf246a1e63a920a8ffd346f3c5a18142bd13f /Platform/Hisilicon/D05/D05.fdf
parent0c9b1288c58cc9ef14e4fd4a9154a57a0ee9d16e (diff)
Hisilicon/D05: Add PPTT support
Add Processor Properties Topology Table, PPTT include Processor hierarchy node, Cache Type Structure and ID structure. PPTT is needed for lscpu command to show socket information correctly. https://bugs.linaro.org/show_bug.cgi?id=3206 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> Reveiwed-by: Jeremy Linton <jeremy.linton@arm.com>
Diffstat (limited to 'Platform/Hisilicon/D05/D05.fdf')
-rw-r--r--Platform/Hisilicon/D05/D05.fdf1
1 files changed, 1 insertions, 0 deletions
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 78ab0c89..97de4d22 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -241,6 +241,7 @@ READ_LOCK_STATUS = TRUE
INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+ INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#