diff options
| author | Ming Huang <ming.huang@linaro.org> | 2018-07-13 16:15:39 +0800 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-07-25 13:09:27 +0200 |
| commit | bec4d42d476b3c0e74563724879550c181bc7c0a (patch) | |
| tree | 23bfabda8e38e7a6b147cb0ce6be3a294596a528 /Platform/Hisilicon/D05/D05.dsc | |
| parent | 43681c899e4c11fd51782dc49b3a72d237f319ca (diff) | |
Hisilicon/D05/Pcie: optimize two pcie ports space
Optimize pcie space for promoting usage rate.Change regions order
of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion
can satisfy the requirement of larger address alignment.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'Platform/Hisilicon/D05/D05.dsc')
| -rw-r--r-- | Platform/Hisilicon/D05/D05.dsc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d9..4885a2a2 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -305,13 +305,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000
gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000
gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000
@@ -336,10 +336,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000
gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
+ gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000
gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
@@ -353,10 +353,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000
gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
+ gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000
gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
|