diff options
| author | Daniil Egranov <daniil.egranov@arm.com> | 2018-05-17 20:41:43 -0500 |
|---|---|---|
| committer | Thomas Abraham <thomas.abraham@arm.com> | 2020-04-15 21:22:49 +0530 |
| commit | fd10b408cc7c12868e2f964a7cac99fab7d04252 (patch) | |
| tree | 0ace5814ba1689f5f98fabeac50b7f47ca900823 /Platform/ARM/Drivers/StandaloneMmDmc620RasDriver/StandaloneMmDmc620RasDriver.h | |
| parent | c7990f105a92f08056b06ff8692de2f7790a7ee5 (diff) | |
RAS: Added StandaloneMM DMC620 RAS driver
The StandaloneMM RAS DMC driver implements:
- DMC RAS event handler
- ACPI CPER update procedure
- Error injection
https://jira.arm.com/browse/PLATFORMS-660
https://jira.arm.com/browse/PLATFORMS-772
Change-Id: I5fac64a899f2b73e43d4ba22717dd7b496dccda8
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
Diffstat (limited to 'Platform/ARM/Drivers/StandaloneMmDmc620RasDriver/StandaloneMmDmc620RasDriver.h')
| -rw-r--r-- | Platform/ARM/Drivers/StandaloneMmDmc620RasDriver/StandaloneMmDmc620RasDriver.h | 686 |
1 files changed, 686 insertions, 0 deletions
diff --git a/Platform/ARM/Drivers/StandaloneMmDmc620RasDriver/StandaloneMmDmc620RasDriver.h b/Platform/ARM/Drivers/StandaloneMmDmc620RasDriver/StandaloneMmDmc620RasDriver.h new file mode 100644 index 00000000..ab80fcd0 --- /dev/null +++ b/Platform/ARM/Drivers/StandaloneMmDmc620RasDriver/StandaloneMmDmc620RasDriver.h @@ -0,0 +1,686 @@ +/** @file
+*
+* Copyright (c) 2017-2018, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _DMC620_RAS_DRIVER_H_
+#define _DMC620_RAS_DRIVER_H_
+
+#include <Base.h>
+#include <Guid/MpInformation.h>
+
+#include <Library/ArmSvcLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CperLib.h>
+#include <Library/DebugLib.h>
+
+#include <Pi/PiSmmCis.h>
+
+#include <Protocol/DebugSupport.h> // for EFI_SYSTEM_CONTEXT
+#include <Protocol/MmConfiguration.h>
+#include <Protocol/RasErrorSourceInfo.h>
+#include <Protocol/MmCpu.h>
+
+#include <Guid/Cper.h>
+#include <IndustryStandard/Acpi.h>
+
+/* DMC-620 base address */
+#define MEMORY_CONTROLLER_BASE 0x4E000000
+
+/* DMC-620 config commands and states */
+#define STATE_MASK 0x7
+#define CONFIG_STATE 0x0 /* Enter the CONFIG architectural state */
+#define LOW_POWER_STATE 0x1 /* Enter the LOW_POWER architectural state */
+#define PAUSED_STATE 0x2 /* Enter the PAUSED architectural state */
+#define READY_STATE 0x3 /* Enter the READY architectural state */
+#define EXECUTE 0x4 /* Performs any directCmd operations */
+#define EXECUTE_DRAIN 0x5 /* Performs any directCmd operations after first draining the controller*/
+#define ABORT_CLR 0x6 /* Enter the RECOVER architectural state */
+
+/* DNC-620 RAS features */
+#define ED_FE_ENABLED 0x2 /* Indicates if error detection is enabled */
+#define DE_FE_ENABLED 0x8 /* Indicates if errors on writes are deferred */
+#define UI_FE_ENABLED 0x20 /* Indicates if uncorrected error recovery interrupt is enabled */
+#define FI_FE_ENABLED 0x80 /* Indicates if fault handling interrupt is enabled */
+#define UE_FE_ENABLED 0x200 /* Indicates if uncorrected error reporting is enabled */
+#define CFI_FE_ENABLED 0x800 /* Indicates if corrected fault handling interrupt is enabled */
+
+/* DMC-620 RAS Control 0 */
+#define ED_ENABLE 0x1 /* ECC detection on reads */
+#define DE_ENABLE 0x2 /* Defer on reads */
+#define UI_ENABLE 0x4 /* Uncorrectable error recovery interrupt */
+#define FI_INT_ENABLE 0x8 /* ECC FHI Interrupt */
+#define CFI_INT_ENABLE 0x100 /* CFI interrupt */
+
+/* DMC-620 RAS Control 1 */
+#define ECC_PROTECTION_SECDED 0x1 /* ECC protection */
+#define ECC_PROTECTION_SYMBOL 0x2 /* ECC protection */
+#define WB_ENABLE 0x4 /* Program to enable or disable write-back of ECC corrected data */
+#define RETRY_ENABLE 0x8 /* Program to enable or disable retry of ECC uncorrectable data operations */
+#define RMW_ENABLE 0x10 /* Enable read-modify-write operations */
+#define WDE_ENABLE 0x20 /* Write Defer Enable */
+#define CPI_ENABLE 0x40 /* Ignore parity bits from CHI */
+#define CDI_ENABLE 0x80 /* Ignore poison or defer indication from CHI */
+
+#define ECC_NO 0x0 /* No DRAM ECC */
+#define ECC_SECDED 0x1 /* SECDED ECC */
+#define ECC_SYMBOL 0x2 /* Symbol ECC */
+
+#define DMC620_ACCESS_ADDRESS_COUNT 8
+
+/* DMC-620 RAS Status */
+#define ERR_STATUS_ECC_ERR_SRAM 0x6 /* Indicates the type of error SRAM or SDRAM */
+#define ERR_STATUS_ECC_ERR_SDRAM 0xC /* Indicates the type of error SRAM or SDRAM */
+#define ERR_STATUS_ECC_ERR_DBP 0xA /* DBP error passed in from chi interface */
+#define ERR_STATUS_IERR 0xFF00 /* Indicates which rank counter has overflowed */
+#define ERR_STATUS_UI_CT_UER 0x300000 /* Recoverable (uninfected containable) error */
+#define ERR_STATUS_PN 0x400000 /* Poison was detected */
+#define ERR_STATUS_DE 0x800000 /* An uncorrectable ECC error was detected and deferred */
+#define ERR_STATUS_CE_TRANSIENT 0x1000000 /* An non-overflowing error was detected and syndrome for the error has been captured */
+#define ERR_STATUS_CE_CORRECTED 0x2000000 /* Reserved */
+#define ERR_STATUS_CE_PERSISTENT 0x3000000 /* An error counter belonging to this record has overflowed asserting a CFH interrupt */
+#define ERR_STATUS_MV 0x4000000 /* Miscellaneous Registers Valid */
+#define ERR_STATUS_OF 0x8000000 /* This bit is directly tied to the errc counter(s) of this record */
+#define ERR_STATUS_V 0x40000000 /* This register is valid and at least one error has been recorded */
+#define ERR_STATUS_AV 0x80000000 /* Indicates that the ERRXADDR register for this record contains a physical address */
+
+#define ERR_STATUS_RANK_BIT 8 /* Error rank bit position */
+
+#define RAS_DMC620_ERROR_GHES_TYPE_V1 0x9 /* GHESv1 type identifier */
+#define RAS_DMC620_ERROR_GHES_TYPE_V2 0xA /* GHESv2 type identifier */
+#define RAS_DMC620_ERROR_SOURCE_TOTAL 2 /* Number of error sources supported by the driver */
+#define RAS_DMC620_ERROR_SOURCE_START_EVENT 804 /* First event number */
+#define RAS_DMC620_ERROR_CPER_RECORD_SIZE 0x1000 /* Size of CPER record associated with each error source */
+#define RAS_DMC620_ERROR_ADDRESS_SPACE 0x0 /* Type of address space: System memory address space */
+#define RAS_DMC620_ERROR_REGISTER_WIDTH_BIT 0x40 /* Size of access register */
+#define RAS_DMC620_ERROR_REGISTER_OFFSET_BIT 0x0 /* Bit offset of access register */
+#define RAS_DMC620_ERROR_ACCESS_SIZE 0x4 /* Address space access size */
+#define RAS_DMC620_ERROR_ACK_REGISTER_SIZE 0x8 /* Size of GHESv2 acknowledgment register */
+
+/* DMC-620 error injection */
+#define TST_MODE_ENABLE 0x1 /* Enable test mode */
+typedef enum {
+ SINGLE_BIT_INJECT = 0x2, /* Inject single-bit error */
+ DOUBLE_BIT_INJECT = 0x6 /* Inject double-bit error */
+} ERR_INJECT_TYPE;
+
+/* DMC Error Record Types */
+typedef enum {
+ DRAM_ECC_CORRECTED_FH = 0x1, /* DRAM ECC reporting through a CFH interrupt */
+ DRAM_ECC_FH = 0x2, /* DRAM ECC reporting through an FH interrupt */
+ CHI_FH = 0x3, /* CHI DBP reporting through an FH interrupt */
+ SRAM_ECC_CORRECTED_FH = 0x4, /* SRAM ECC reporting through a CFH interrupt */
+ SRAM_ECC_FH = 0x5, /* SRAM ECC reporting through an FH interrupt */
+ DMC_ERROR_RECOVERY = 0x6 /* DMC reporting through an ER interrupt */
+} ERR_RECORD_TABLE_TYPE;
+
+#pragma pack(1)
+
+/* Access address next registers */
+typedef struct DMC620_ADDRESS_NEXT {
+ UINT32 Min_31_00;
+ UINT32 Min_43_32;
+ UINT32 Max_31_00;
+ UINT32 Max_43_32;
+} DMC620_ADDRESS_NEXT_TYPE;
+
+/* Access address next registers */
+typedef struct DMC620_ADDRESS_NOW {
+ UINT32 Min_31_00;
+ UINT32 Min_43_32;
+ UINT32 Max_31_00;
+ UINT32 Max_43_32;
+} DMC620_ADDRESS_NOW_TYPE;
+
+/* PMU payload information operation register */
+typedef struct DMC620_PMC_COUNTER {
+ UINT32 Mask_31_00;
+ UINT32 Mask_63_32;
+ UINT32 Match_31_00;
+ UINT32 Match_63_32;
+ UINT32 Control;
+ UINT32 Reserved0;
+ UINT32 SnapshotValue_31_00;
+ UINT32 Reserved1;
+ UINT32 Value_31_00;
+ UINT32 Reserved2;
+} DMC620_PMC_COUNTER_TYPE;
+
+/* DMC-620 register definitions */
+typedef struct DMC620_REGS {
+ UINT32 MemcStatus; /* DMC status */
+ UINT32 MemcConfig; /* DMC configuration data */
+ UINT32 MemcCmd; /* Change the state of DMC, or execute queued manager operations */
+ UINT32 Reserved1; /* Reserved */
+ UINT32 AddressControlNext; /* Configures the DRAM address parameters */
+ UINT32 DecodeControlNext; /* Configures how the DRAM address is decoded from the system address */
+ UINT32 FormatControl; /* Configures the memory burst access parameters */
+ UINT32 AddressMapNext; /* Configures the system address mapping options */
+ UINT32 LowPowerControlNext; /* Configures the low-power features */
+ UINT32 Reserved2; /* Reserved */
+ UINT32 TurnaroundControlNext; /* Configures arbitration between read and write and rank to rank traffic on the DRAM bus */
+ UINT32 HitTurnaroundControlNext; /* Configures the settings for preventing starvation of non-hits in the presence of in-row hit streams */
+ UINT32 QosClassControlNext; /* Configures the priority class for each QoS encoding */
+ UINT32 EscalationControlNext; /* Configures the settings for escalating the priority of entries in the queue */
+ UINT32 QvControl_31_00_Next; /* Configures the priority settings for each QoS encoding */
+ UINT32 QvControl_63_32_Next; /* Configures the priority settings for each QoS encoding */
+ UINT32 RtControl_31_00_Next; /* Configures the timeout settings for each QoS encoding */
+ UINT32 RtControl_63_32_Next; /* Configures the timeout settings for each QoS encoding */
+ UINT32 TimeoutControlNext; /* Configures the prescaler applied to timeout values */
+ UINT32 CreditControlNext; /* Configures the settings for preventing starvation of CHI protocol retries */
+ UINT32 WritePriorityControl_31_00_Next; /* Configures the priority settings for write requests within the DMC */
+ UINT32 WritePriorityControl_63_32_Next; /* Configures the priority settings for write requests within the DMC */
+ UINT32 QueueThresholdControl_31_00_Next; /* Configures the threshold settings for requests in the DMC */
+ UINT32 QueueThresholdControl_63_32_Next; /* Configures the threshold settings for requests in the DMC */
+ UINT32 AddressShutter_31_00_Next; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_63_32_Next; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_95_64_Next; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_127_96_Next; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_159_128_Next; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_191_160_Next; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 MemoryAddressMax_31_00_Next; /* Configures the address space control for the DMC default region */
+ UINT32 MemoryAddressMax_43_32_Next; /* Configures the address space control for the DMC default region */
+ DMC620_ADDRESS_NEXT_TYPE AccessAddressNext[DMC620_ACCESS_ADDRESS_COUNT]; /*!< Configures the address space control for address regions */
+ UINT32 ChannelStatus; /* Holds the current status of the memory channel */
+ UINT32 ChannelStatus_63_32; /* Holds the current status of the memory channel */
+ UINT32 DirectAddr; /* Sets the direct command address field for direct commands */
+ UINT32 DirectCmd; /* Generates direct commands from the manager */
+ UINT32 DciReplayTypeNext; /* Configures the behavior of the DMC if a DRAM or PHY error is received when executing a direct command */
+ UINT32 DirectControlNext; /* Represents the training configuration of the DMC executed by a direct command */
+ UINT32 DciStrb; /* Configures the write data strobe values used during direct_cmd WRITE operations */
+ UINT32 DciData; /* Read returns read data received a result of a READ command. Write sets the data to be used for direct_cmd WRITE commands */
+ UINT32 RefreshControlNext; /* Configures the type of refresh commands issued by the DMC */
+ UINT32 Reserved3; /* Reserved */
+ UINT32 MemoryTypeNext; /* Configures the attached memory type */
+ UINT32 Reserved4; /* Reserved */
+ UINT32 FeatureConfig; /* Control register for DMC features */
+ UINT32 Reserved5; /* Reserved */
+ UINT32 NibbleFailed_031_000; /* Inform the DMC that nibble has failed */
+ UINT32 NibbleFailed_063_032; /* Inform the DMC that nibble has failed */
+ UINT32 NibbleFailed_095_064; /* Inform the DMC that nibble has failed */
+ UINT32 NibbleFailed_127_096; /* Inform the DMC that nibble has failed */
+ UINT32 QueueAllocateControl_031_000; /* Inform the DMC that a queue (RAM) entry has failed, where 0 means failed and not included for allocation */
+ UINT32 QueueAllocateControl_063_032; /* Inform the DMC that a queue (RAM) entry has failed, where 0 means failed and not included for allocation */
+ UINT32 QueueAllocateControl_095_064; /* Inform the DMC that a queue (RAM) entry has failed, where 0 means failed and not included for allocation */
+ UINT32 QueueAllocateControl_127_096; /* Inform the DMC that a queue (RAM) entry has failed, where 0 means failed and not included for allocation */
+ UINT8 Reserved6[0x16c - 0x158]; /* Reserved */
+ UINT32 LinkErrCount; /* Counter register for link errors. The counter increments on detection of a new link error (dfi_alert_n or dfi_err) */
+ UINT32 ScrubControl0Next; /* Scrub engine channel control register */
+ UINT32 ScrubAddressMin0Next; /* Configures the address space control for the scrub engine channel */
+ UINT32 ScrubAddressMax0Next; /* Configures the address space control for the scrub engine channel */
+ UINT32 ScrubAddressCurrent0; /* Current the address space for the scrub engine channel */
+ UINT32 ScrubControl1Next; /* Scrub engine channel control register */
+ UINT32 ScrubAddressMin1Next; /* Configures the address space control for the scrub engine channel */
+ UINT32 ScrubAddressMax1Next; /* Configures the address space control for the scrub engine channel */
+ UINT32 ScrubAddressCurrent1; /* Current the address space for the scrub engine channel */
+ UINT8 Reserved7[0x1a0 - 0x190]; /* Reserved */
+ UINT32 CsRemapControl_31_00_Next; /* Control register for CS remap */
+ UINT32 CsRemapControl_63_32_Next; /* Control register for CS remap */
+ UINT32 CsRemapControl_95_64_Next; /* Control register for CS remap */
+ UINT32 CsRemapControl_127_96_Next; /* Control register for CS remap */
+ UINT32 CidRemapControl_31_00_Next; /* Control register for dfi_CID remap */
+ UINT32 CidRemapControl_63_32_Next; /* Control register for dfi_CID remap */
+ UINT8 Reserved8[0x1c0 - 0x1b8]; /* Reserved */
+ UINT32 CkeRemapControlNext; /* Control register for CKE remap */
+ UINT32 RstRemapControlNext; /* Control register for RST remap */
+ UINT32 CkRemapControlNext; /* Control register for CK remap */
+ UINT32 Reserved9; /* Reserved */
+ UINT32 PowerGroupControl_31_00_Next; /* Power Group Control register for power managing ranks together */
+ UINT32 PowerGroupControl_63_32_Next; /* Power Group Control register for power managing ranks together */
+ UINT32 PowerGroupControl_95_64_Next; /* Power Group Control register for power managing ranks together */
+ UINT32 PowerGroupControl_127_96_Next; /* Power Group Control register for power managing ranks together */
+ UINT32 PhyRdwrdataCsMask_31_00; /* Maps a logical rank to the physical rank phy_rd/wrdata_cs output pins */
+ UINT32 PhyRdwrdataCsMask_63_32; /* Maps a logical rank to the physical rank phy_rd/wrdata_cs output pins */
+ UINT32 PhyRequestCsRemap; /* Maps PHY traning request from a physical chip select to DMC internal logical chip select */
+ UINT32 Reserved10; /* Reserved */
+ UINT32 FeatureControlNext; /* Control register for DMC features */
+ UINT32 MuxControlNext; /* Control muxing options */
+ UINT32 RankRemapControlNext; /* Control register for rank remap */
+ UINT32 Reserved11; /* Reserved */
+ UINT32 TRefiNext; /* Configures the refresh interval timing parameter */
+ UINT32 TRfcNext; /* Configures the tRFC timing parameter */
+ UINT32 TMrrNext; /* Configures the tMRR timing parameter */
+ UINT32 TMrwNext; /* Configures the tMRW timing parameter */
+ UINT8 Reserved12[0x218 - 0x210]; /* Reserved */
+ UINT32 TRcdNext; /* Configures the tRCD timing parameter */
+ UINT32 TRasNext; /* Configures the tRAS timing parameter */
+ UINT32 TRpNext; /* Configures the tRP timing parameter */
+ UINT32 TRpallNext; /* Configures the tRPALL timing parameter */
+ UINT32 TRrdNext; /* Configures the tRRD timing parameter */
+ UINT32 TActWindowNext; /* Configures the tFAW and tMAWi timing parameter */
+ UINT32 Reserved13; /* Reserved */
+ UINT32 TRtrNext; /* Configures the read-to-read timing parameter */
+ UINT32 TRtwNext; /* Configures the read-to-write timing parameter */
+ UINT32 TRtpNext; /* Configures the read-to-precharge timing parameter */
+ UINT32 Reserved14; /* Reserved */
+ UINT32 TWrNext; /* Configures the tWR timing parameter */
+ UINT32 TWtrNext; /* Configures the write-to-read timing parameter */
+ UINT32 TWtwNext; /* Configures the write-to-write timing parameter */
+ UINT32 Reserved15; /* Reserved */
+ UINT32 TXmpdNext; /* Configures the command delay between exiting Maximum Power Down and a subsequent command to that rank */
+ UINT32 TEpNext; /* Configures the enter power-down timing parameter */
+ UINT32 TXpNext; /* Configures the exit power-down timing parameter for operations that do not require a DLL (tXP), and those that do (tXPDLL) */
+ UINT32 TEsrNext; /* Configures the enter self-refresh timing parameter */
+ UINT32 TXsrNext; /* Configures the exit self-refresh timing parameter */
+ UINT32 TEsrckNext; /* Configures the delay between entering self-refresh and disabling the DRAM clock */
+ UINT32 TCkxsrNext; /* Configures the delay between DRAM clock enable and exiting self-refresh */
+ UINT32 TCmdNext; /* Configures command signaling timing */
+ UINT32 TParityNext; /* Parity latencies t_parinlat and t_completion */
+ UINT32 TZqcsNext; /* Configures the delay to apply following a ZQC-Short calibration command */
+ UINT32 TRwOdtClrNext; /* Timing parameter applies extra guard-band between the last issued rd/wr command and potential ZQC, SREF, and MES commands */
+ UINT8 Reserved16[0x300 - 0x280]; /* Reserved */
+ UINT32 TRddataEnNext; /* Determines the time between a READ command commencing on the DFI interface, and the assertion of the dfi_read_en signal */
+ UINT32 TPhyrdlatNext; /* Determines the maximum possible time between the assertion of the dfi_read_en signal, and the assertion of the dfi_rddata_valid signal by the PHY */
+ UINT32 TPhywrlatNext; /* Determines the time between a WRITE command commencing on the DFI interface, and the assertion of the dfi_wrdata_en, dfi_wrdata_cs and dfi_wrdata signals */
+ UINT32 Reserved17; /* Reserved */
+ UINT32 RdlvlControlNext; /* Determines the DMC behavior during read training operations */
+ UINT32 RdlvlMrsNext; /* Determines the Mode Register command to use to place the DRAM into a training mode for read training */
+ UINT32 TRdlvlEnNext; /* Configures the t_rdlvl_en timing parameter */
+ UINT32 TRdlvlRrNext; /* Configures the t_rdlvl_rr timing parameter */
+ UINT32 WrlvlControlNext; /* Determines the DMC behavior during write training operations */
+ UINT32 WrlvlMrsNext; /* Determines the Mode Register command that the DMC must use to put the DRAM into a training mode for write levelling */
+ UINT32 TWrlvlEnNext; /* Configures the t_wrlvl_en timing parameter */
+ UINT32 TWrlvlWwNext; /* Configures the t_wrlvl_ww timing parameter */
+ UINT32 Reserved18; /* Reserved */
+ UINT32 TrainingWrlvlSliceStatus; /* Shows slice information relating to the wrlvl training request status of DMC */
+ UINT32 TrainingRdlvlSliceStatus; /* Shows slice information relating to the rdlvl training request status of DMC */
+ UINT32 TrainingRdlvlGateSliceStatus; /* Shows slice information relating to the rdlvl gate training request status of DMC */
+ UINT32 TrainingWdqlvlSliceStatus; /* Shows slice information relating to the WrDQ training request status of DMC */
+ UINT32 TrainingWdqlvlSliceResult; /* Shows per slice result from the PHY in response to the WrDQ training request to the DMC */
+ UINT32 PhyPowerControlNext; /* Configures the low-power requests made to the PHY for the different channel states */
+ UINT32 TLprespNext; /* Configures the minimum cycle delay to apply for PHY low-power handshakes */
+ UINT32 PhyUpdateControlNext; /* Configures the update mechanism to use in response to PHY training requests */
+ UINT32 TOdthNext; /* Configures the ODTH8 timing parameter */
+ UINT32 OdtTimingNext; /* Configures the ODT on and off timing */
+ UINT32 Reserved19; /* Reserved */
+ UINT32 OdtWrControl_31_00_Next; /* Configures the ODT on and off settings for active and inactive ranks during writes */
+ UINT32 OdtWrControl_63_32_Next; /* Configures the ODT on and off settings for active and inactive ranks during writes */
+ UINT32 OdtRdControl_31_00_Next; /* Configures the ODT on and off settings for active and inactive ranks during writes */
+ UINT32 OdtRdControl_63_32_Next; /* Configures the ODT on and off settings for active and inactive ranks during writes */
+ UINT32 TemperatureReadout; /* Holds the status of the temperature information */
+ UINT32 Reserved20; /* Reserved */
+ UINT32 TrainingStatus; /* Shows information relating to the update request status */
+ UINT32 TrainingStatus_63_32; /* Shows information relating to the update request status */
+ UINT32 DqMapControl_15_00_Next; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_31_16_Next; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_47_32_Next; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_63_48_Next; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_71_64_Next; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 Reserved21; /* Reserved */
+ UINT32 RankStatus; /* Shows the current status of geardown, MPD and CAL */
+ UINT32 ModeChangeStatus; /* Shows the current status of the sequence that is currently being processed */
+ UINT8 Reserved22[0x3b0 - 0x3a0]; /* Reserved */
+ UINT32 OdtCpControl_31_00_Next; /* Determines which of the 8 dfi_odt[7:0] output signals are connected to a logically address rank */
+ UINT32 OdtCpControl_63_32_Next; /* Determines which of the 8 dfi_odt[7:0] output signals are driven during a write a DRAM */
+ UINT8 Reserved23[0x400 - 0x3b8]; /* Reserved */
+ UINT32 UserStatus; /* Shows the value of the input user_status signals */
+ UINT32 Reserved24; /* Reserved */
+ UINT32 UserConfig0Next; /* Drives the output user_config0 signal */
+ UINT32 UserConfig1Next; /* Drives the output user_config1 signal */
+ UINT32 UserConfig2; /* Drives the output user_config2 signal */
+ UINT32 UserConfig3; /* Drives the output user_config3 signal */
+ UINT8 Reserved25[0x500 - 0x418]; /* Reserved */
+ UINT32 InterruptControl; /* Configures interrupt behavior */
+ UINT32 Reserved26; /* Reserved */
+ UINT32 InterruptClr; /* Clear interrupts */
+ UINT32 Reserved27; /* Reserved */
+ UINT32 InterruptStatus; /* Status register for interrupts (pre-mask) */
+ UINT8 Reserved28[0x538 - 0x514]; /* Reserved */
+ UINT32 FailedAccessIntInfo_31_00; /* Shows information relating to the interrupt */
+ UINT32 FailedAccessIntInfo_63_32; /* Shows information relating to the interrupt */
+ UINT32 FailedProgIntInfo_31_00; /* Shows information relating to the interrupt */
+ UINT32 FailedProgIntInfo_63_32; /* Shows information relating to the interrupt */
+ UINT32 LinkErrIntInfo_31_00; /* Shows information relating to the interrupt */
+ UINT32 LinkErrIntInfo_63_32; /* Shows information relating to the interrupt */
+ UINT32 ArchFsmIntInfo_31_00; /* Shows information relating to the interrupt */
+ UINT32 ArchFsmIntInfo_63_32; /* Shows information relating to the interrupt */
+ UINT8 Reserved29[0x610 - 0x558]; /* Reserved */
+ UINT32 TDbTrainRespNext; /* Configures the t_db_train_resp timing parameter for DB-DRAM Training */
+ UINT32 TLvlDisconnectNext; /* Configures the t_lvl timing parameter for all DFI training interfaces */
+ UINT8 Reserved30[0x620 - 0x618]; /* Reserved */
+ UINT32 WdqlvlControlNext; /* Determines the DMC behavior during write-DQ training operations */
+ UINT32 WdqlvlVrefdqTrainMrsNext; /* Determines the Mode register command to use to place the DRAM into a VrefDQ training mode */
+ UINT32 WdqlvlAddress_31_00_Next; /* Programs the row and column address that is used in WrDQ training */
+ UINT32 WdqlvlAddress_63_32_Next; /* Programs the address that is used in WrDQ training */
+ UINT32 TWdqlvlEnNext; /* Configures the t_wdqlvl_en timing parameters */
+ UINT32 TWdqlvlWwNext; /* Configures the t_wdqlvl_ww timing parameters */
+ UINT32 TWdqlvlRwNext; /* Configures the t_wdqlvl_rw timing parameters */
+ UINT32 TrainingWdqlvlSliceResp; /* Shows per slice response from the PHY in response to the WrDQ training request to DMC */
+ UINT32 TrainingRdlvlSliceResp; /* Shows per slice response from the PHY in response to the rdlvl training request to DMC */
+ UINT8 Reserved31[0x654 - 0x644]; /* Reserved */
+ UINT32 PhymstrControlNext; /* Determines the DMC behavior during write training operations */
+ UINT8 Reserved32[0x700 - 0x658]; /* Reserved */
+ UINT32 Err0Fr; /* This record defines which are common to all RAS error records in this section */
+ UINT32 Reserved33; /* Reserved */
+ UINT32 Err0Ctlr0; /* This register is the global control regsiter for the DMC RAS functions */
+ UINT32 Err0Ctlr1; /* This register is the global control regsiter for the DMC RAS functions */
+ UINT32 Err0Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT8 Reserved34[0x740 - 0x714]; /* Reserved */
+ UINT32 Err1Fr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved35; /* Reserved */
+ UINT32 Err1Ctlr; /* This register is reserved */
+ UINT32 Reserved36; /* Reserved */
+ UINT32 Err1Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved37; /* Reserved */
+ UINT32 Err1Addr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 Err1Addr1; /* Contains the physical address MSB's associated with the error */
+ UINT32 Err1Misc0; /* This register gives the Physical Rank, Row, and Column of the last error detected before an interrupt is asserted */
+ UINT32 Err1Misc1; /* This register gives the Physical Rank, Logical Rank, and failed nobble location the last error detected before an interrupt is asserted */
+ UINT32 Err1Misc2; /* DRAM correctable Error Counter Access restrictions */
+ UINT32 Err1Misc3; /* DRAM correctable Error Counter Access restrictions */
+ UINT32 Err1Misc4; /* DRAM correctable Error Counter Access restrictions */
+ UINT32 Err1Misc5; /* DRAM correctable Error Counter Access restrictions */
+ UINT8 Reserved38[0x780 - 0x778]; /* Reserved */
+ UINT32 Err2Fr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved39; /* Reserved */
+ UINT32 Err2Ctlr; /* This register is reserved */
+ UINT32 Reserved40; /* Reserved */
+ UINT32 Err2Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved41; /* Reserved */
+ UINT32 Err2Addr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 Err2Addr1; /* Contains the physical address MSB's associated with the error */
+ UINT32 Err2Misc0; /* This register gives the Physical Rank, Row, and Column of the last error detected before an interrupt is asserted */
+ UINT32 Err2Misc1; /* This register gives the bank and logical rank of the first error detected since the last clear */
+ UINT32 Err2Misc2; /* DRAM uncorrectable Error Counter Access restrictions */
+ UINT32 Err2Misc3; /* DRAM uncorrectable Error Counter Access restrictions */
+ UINT32 Err2Misc4; /* DRAM uncorrectable Error Counter Access restrictions */
+ UINT32 Err2Misc5; /* DRAM uncorrectable Error Counter Access restrictions */
+ UINT8 Reserved42[0x7c0 - 0x7b8]; /* Reserved */
+ UINT32 Err3Fr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved43; /* Reserved */
+ UINT32 Err3Ctlr; /* This register is reserved */
+ UINT32 Reserved44; /* Reserved */
+ UINT32 Err3Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved45; /* Reserved */
+ UINT32 Err3Addr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 Err3Addr1; /* Contains the physical address MSB's associated with the error */
+ UINT8 Reserved46[0x800 - 0x7e0]; /* Reserved */
+ UINT32 Err4Fr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved47; /* Reserved */
+ UINT32 Err4Ctlr; /* This register is reserved */
+ UINT32 Reserved48; /* Reserved */
+ UINT32 Err4Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved49; /* Reserved */
+ UINT32 Err4Addr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 Err4Addr1; /* Contains the physical address MSB's associated with the error */
+ UINT32 Err4Misc0; /* This register gives the Physical Rank, Row, and Column of the last error detected before an interrupt is asserted */
+ UINT32 Err4Misc1; /* This register gives the bank and logical rank of the first error detected since the last clear */
+ UINT32 Err4Misc2; /* RAM correctable Error Counter Access restrictions */
+ UINT8 Reserved50[0x840 - 0x82c]; /* Reserved */
+ UINT32 Err5Fr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved51; /* Reserved */
+ UINT32 Err5Ctlr; /* This register is reserved */
+ UINT32 Reserved52; /* Reserved */
+ UINT32 Err5Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved53; /* Reserved */
+ UINT32 Err5Addr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 Err5Addr1; /* Contains the physical address MSB's associated with the error */
+ UINT32 Err5Misc0; /* This register gives the bank and logical rank of the first error detected since the last clear */
+ UINT32 Err5Misc1; /* This register gives the bank and logical rank of the first error detected since the last clear */
+ UINT32 Err5Misc2; /* RAM correctable Error Counter Access restrictions */
+ UINT8 Reserved54[0x880 - 0x86c]; /* Reserved */
+ UINT32 Err6Fr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved55; /* Reserved */
+ UINT32 Err6Ctlr; /* This register is reserved */
+ UINT32 Reserved56; /* Reserved */
+ UINT32 Err6Status; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved57; /* Reserved */
+ UINT32 Err6Addr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 Err6Addr1; /* Contains the physical address MSB's associated with the error */
+ UINT32 Err6Misc0; /* This register gives the Physical Rank, Row, and Column of the first error detected since last cleared*/
+ UINT32 Err6Misc1; /* This register gives the bank and logical rank of the first error detected since the last clear */
+ UINT8 Reserved58[0x920 - 0x8a8]; /* Reserved */
+ UINT32 Errgsr; /* This register shows the status of all the DMC error records */
+ UINT8 Reserved59[0xa00 - 0x924]; /* Reserved */
+ UINT32 PmuSnapshotReq; /* Generates PMU snapshot request Access restrictions */
+ UINT32 PmuSnapshotAck; /* Indicates PMU snapshot acknowledge Access restrictions */
+ UINT32 PmuOverflowStatusClkdiv2; /* Indicates which clkdiv2 counters have overflowed Access restrictions */
+ UINT32 PmuOverflowStatusClk; /* Indicates which clk domain counters have overflowed Access restrictions */
+ DMC620_PMC_COUNTER_TYPE pmcClkdiv2Count[8];
+ DMC620_PMC_COUNTER_TYPE pmcClkCount[2];
+ UINT8 Reserved60[0xe00 - 0xba0]; /* Reserved */
+ UINT32 IntegCfg; /* Integration test register to enable integration test mode */
+ UINT32 Reserved61; /* Reserved */
+ UINT32 IntegOutputs; /* Drives the value of outputs when in integration test mode */
+ UINT8 Reserved62[0x1010 - 0xe0c]; /* Reserved */
+ UINT32 AddressControlNow; /* Configures the DRAM address parameters */
+ UINT32 DecodeControlNow; /* Configures how the DRAM address is decoded from the system address */
+ UINT32 Reserved63; /* Reserved */
+ UINT32 AddressMapNow; /* Configures the system address mapping options */
+ UINT32 LowPowerControlNow; /* Configures the low-power features */
+ UINT32 Reserved64; /* Reserved */
+ UINT32 TurnaroundControlNow; /* Configures the settings for arbitration between read and write and rank to rank traffic on the DRAM bus */
+ UINT32 HitTurnaroundControlNow; /* Configures the settings for preventing starvation of non-hits in the presence of in-row hit streams */
+ UINT32 QosClassControlNow; /* Configures the priority class for each QoS encoding */
+ UINT32 EscalationControlNow; /* Configures the settings for escalating the priority of entries in the queu */
+ UINT32 QvControl_31_00_Now; /* Configures the priority settings for each QoS encoding */
+ UINT32 QvControl_63_32_Now; /* Configures the priority settings for each QoS encoding */
+ UINT32 RtControl_31_00_Now; /* Configures the timeout settings for each QoS encoding */
+ UINT32 RtControl_63_32_Now; /* Configures the timeout settings for each QoS encoding */
+ UINT32 TimeoutControlNow; /* Configures the prescaler applied to timeout values */
+ UINT32 CreditControlNow; /* Configures the settings for preventing starvation of CHI protocol retries */
+ UINT32 WritePriorityControl_31_00_Now; /* Configures the priority settings for write requests */
+ UINT32 WritePriorityControl_63_32_Now; /* Configures the priority settings for write requests */
+ UINT32 QueueThresholdControl_31_00_Now; /* Configures the threshold settings for requests in the DMC */
+ UINT32 QueueThresholdControl_63_32_Now; /* Configures the threshold settings for requests in the DMC */
+ UINT32 AddressShutter_31_00_Now; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_63_32_Now; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_95_64_Now; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_127_96_Now; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_159_128_Now; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 AddressShutter_191_160_Now; /* Configures the address shuttering due to channel striping in the interconnect*/
+ UINT32 MemoryAddressMax_31_00_Now; /* Configures the address space control for the DMC default region */
+ UINT32 MemoryAddressMax_43_32_Now; /* Configures the address space control for the DMC default region */
+ DMC620_ADDRESS_NOW_TYPE AccessAddressNow[DMC620_ACCESS_ADDRESS_COUNT]; /*!< Configures the address space control for DMC regions */
+ UINT8 Reserved65[0x1110 - 0x1100]; /* Reserved */
+ UINT32 DciReplayTypeNow; /* Configures the behavior of the DMC if a DRAM or PHY error is received when executing a direct command */
+ UINT32 DirectControlNow; /* Represents the training configuration of the DMC executed by a direct command */
+ UINT8 Reserved66[0x1120 - 0x1118]; /* Reserved */
+ UINT32 RefreshControlNow; /* Configures the type of refresh commands issued by the DMC */
+ UINT32 Reserved67; /* Reserved */
+ UINT32 MemoryTypeNow; /* Configures the DMC for the attached memory type */
+ UINT8 Reserved68[0x1170 - 0x112c]; /* Reserved */
+ UINT32 ScrubControl0Now; /* Scrub engine channel control register */
+ UINT32 ScrubAddressMin0Now; /* Configures the address space control for the scrub engine channel */
+ UINT32 ScrubAddressMax0Now; /* Configures the address space control for the scrub engine channel */
+ UINT32 Reserved69; /* Reserved */
+ UINT32 ScrubControl1Now; /* Scrub engine channel control register */
+ UINT32 ScrubAddressMin1Now; /* Configures the address space control for the scrub engine channel */
+ UINT32 ScrubAddressMax1Now; /* Configures the address space control for the scrub engine channel */
+ UINT8 Reserved70[0x11a0 - 0x118c]; /* Reserved */
+ UINT32 CsRemapControl_31_00_Now; /* Control register for CS remap */
+ UINT32 CsRemapControl_63_32_Now; /* Control register for CS remap */
+ UINT32 CsRemapControl_95_64_Now; /* Control register for CS remap */
+ UINT32 CsRemapControl_127_96_Now; /* Control register for CS remap */
+ UINT32 CidRemapControl_31_00_Now; /* Control register for CID remap */
+ UINT32 CidRemapControl_63_32_Now; /* Control register for CID remap */
+ UINT8 Reserved71[0x11c0 - 0x11b8]; /* Reserved */
+ UINT32 CkeRemapControl_31_00_Now; /* Control register for CKE remap */
+ UINT32 RstRemapControl_31_00_Now; /* Control register for RST remap */
+ UINT32 CkRemapControl_31_00_Now; /* Control register for CK remap */
+ UINT32 PowerGroupControl_31_00_Now; /* Power Group Control register for power managing ranks together */
+ UINT32 PowerGroupControl_63_32_Now; /* Power Group Control register for power managing ranks together */
+ UINT32 PowerGroupControl_95_64_Now; /* Power Group Control register for power managing ranks together */
+ UINT32 PowerGroupControl_127_96_Now; /* Power Group Control register for power managing ranks together */
+ UINT8 Reserved72[0x11f0 - 0x11e0]; /* Reserved */
+ UINT32 FeatureControlNow; /* Control register for DMC features */
+ UINT32 MuxControlNow; /* Control muxing options for the DMC */
+ UINT32 RankRemapControlNow; /* Control register for rank remap */
+ UINT32 Reserved73; /* Reserved */
+ UINT32 TRefiNow; /* Configures the refresh interval timing parameter */
+ UINT32 TRfcNow; /* Configures the tRFC timing parameter */
+ UINT32 TMrrNow; /* Configures the tMRR timing parameter */
+ UINT32 TMrwNow; /* Configures the tMRW timing parameter */
+ UINT8 Reserved74[0x1218 - 0x1210]; /* Reserved */
+ UINT32 TRcdNow; /* Configures the tRCD timing parameter */
+ UINT32 TRasNow; /* Configures the tRAS timing parameter */
+ UINT32 TRpNow; /* Configures the tRP timing parameter */
+ UINT32 TRpallNow; /* Configures the tRPALL timing parameter */
+ UINT32 TRrdNow; /* Configures the tRRD timing parameter */
+ UINT32 TActWindowNow; /* Configures the tFAW and tMAWi timing parameter */
+ UINT32 Reserved75; /* Reserved */
+ UINT32 TRtrNow; /* Configures the read-to-read timing parameter */
+ UINT32 TRtwNow; /* Configures the read-to-write timing parameter */
+ UINT32 TRtpNow; /* Configures the read-to-precharge timing parameter */
+ UINT32 Reserved76; /* Reserved */
+ UINT32 TWrNow; /* Configures the tWR timing parameter */
+ UINT32 TWtrNow; /* Configures the tMRW timing parameter */
+ UINT32 TWtwNow; /* Configures the tMRW timing parameter */
+ UINT32 Reserved77; /* Reserved */
+ UINT32 TXmpdNow; /* Configures the command delay between exiting Maximum Power Down and a subsequent command to that rank */
+ UINT32 TEpNow; /* Configures the enter power-down timing parameter */
+ UINT32 TXpNow; /* Configures the exit power-down timing parameter */
+ UINT32 TEsrNow; /* Configures the enter self-refresh timing parameter */
+ UINT32 TXsrNow; /* Configures the exit self-refresh timing parameter */
+ UINT32 TEsrckNow; /* Configures the delay between entering self-refresh and disabling the DRAM clock */
+ UINT32 TCkxsrNow; /* CConfigures the delay between DRAM clock enable and exiting self-refresh */
+ UINT32 TCmdNow; /* Configures command signaling timing */
+ UINT32 TParityNow; /* Parity latencies t_parinlat and t_completion */
+ UINT32 TZqcsNow; /* Configures the delay to apply following a ZQC-Short calibration command */
+ UINT32 TRwOdtClrNow; /* Applies extra guard-band between the last issued rd/wr command and potential ZQC, SREF, and MRS comamnds */
+ UINT8 Reserved78[0x1300 - 0x1280]; /* Reserved */
+ UINT32 TRddataEnNow; /* Determines the time between a READ command commencing on the DFI interface, and the assertion of the dfi_read_en signal */
+ UINT32 TPhyrdlatNow; /* Determines the maximum possible time between the assertion of the dfi_read_en signal, and the assertion of the dfi_rddata_valid signal by the PHY */
+ UINT32 TPhywrlatNow; /* Determines the time between a WRITE command commencing on the DFI interface, and the assertion of the dfi_wrdata_en, dfi_wrdata_cs and dfi_wrdata signals */
+ UINT32 Reserved79; /* Reserved */
+ UINT32 RdlvlControlNow; /* Determines the DMC behavior during read training operations */
+ UINT32 RdlvlMrsNow; /* Determines the Mode Register command to use to place the DRAM into a training mode for read training */
+ UINT32 TRdlvlEnNow; /* Configures the t_rdlvl_en timing parameter */
+ UINT32 TRdlvlRrNow; /* Configures the t_rdlvl_rr timing parameter */
+ UINT32 WrlvlControlNow; /* Determines the DMC behavior during write training operations */
+ UINT32 WrlvlMrsNow; /* Determines the Mode Register command that the DMC must use to put the DRAM into a training mode for write levelling */
+ UINT32 TWrlvlEnNow; /* Configures the t_wrlvl_en timing parameter */
+ UINT32 TWrlvlWwNow; /* Configures the t_wrlvl_ww timing parameter */
+ UINT8 Reserved80[0x1348 - 0x1330]; /* Reserved */
+ UINT32 PhyPowerControlNow; /* Configures the low-power requests made to the PHY for the different channel states */
+ UINT32 TLprespNow; /* Configures the minimum cycle delay to apply for PHY low-power handshakes */
+ UINT32 PhyUpdateControlNow; /* Configures the update mechanism to use in response to PHY training requests */
+ UINT32 TOdthNow; /* Configures the ODTH8 timing parameter as timed from Write command registered with ODT high Access restrictions */
+ UINT32 OdtTimingNow; /* Configures the ODT on and off timing */
+ UINT32 Reserved81; /* Reserved */
+ UINT32 OdtWrControl_31_00_Now; /* Configures the ODT on and off settings for active and inactive ranks during writes */
+ UINT32 OdtWrControl_63_32_Now; /* Configures the ODT on and off settings for active and inactive ranks during writes */
+ UINT32 OdtRdControl_31_00_Now; /* Configures the ODT on and off settings for active and inactive ranks during reads */
+ UINT32 OdtRdControl_63_32_Now; /* Configures the ODT on and off settings for active and inactive ranks during reads */
+ UINT8 Reserved82[0x1380 - 0x1370]; /* Reserved */
+ UINT32 DqMapControl_15_00_Now; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_31_16_8_Now; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_47_32_Now; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_63_48_Now; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT32 DqMapControl_71_64_Now; /* Controls the DQ mapping compensation applied for CRC calculation */
+ UINT8 Reserved83[0x13b0 - 0x1394]; /* Reserved */
+ UINT32 OdtCpControl_31_00_Now; /* Determines which of the 8 dfi_odt[7:0] output signals are connected to a logically address rank */
+ UINT32 OdtCpControl_63_32_Now; /* Determines which of the 8 dfi_odt[7:0] output signals are driven during a write a DRAM */
+ UINT8 Reserved84[0x1408 - 0x13b8]; /* Reserved */
+ UINT32 UserConfig0Now; /* Drives the output user_config0 signal */
+ UINT32 UserConfig1Now; /* Drives the output user_config1 signal */
+ UINT8 Reserved85[0x1610 - 0x1410]; /* Reserved */
+ UINT32 TDbTrainRespNow; /* Configures the t_db_train_resp timing parameter for DB-DRAM Training */
+ UINT32 TLvlDisconnectNow; /* Configures the t_lvl timing parameter for all DFI training interfaces */
+ UINT8 Reserved86[0x1620 - 0x1618]; /* Reserved */
+ UINT32 WdqlvlControlNow; /* Determines the DMC behavior during write-DQ training operations */
+ UINT32 WdqlvlVrefdqTrainMrsNow; /* Determines the Mode register command to use to place the DRAM into a VrefDQ training mode */
+ UINT32 WdqlvlAddress_31_00_Now; /* Programs the row and column address that is used in WrDQ training */
+ UINT32 WdqlvlAddress_63_32_Now; /* Programs the address that is used in WrDQ training */
+ UINT32 TWdqlvlEnNow; /* Configures the t_wdqlvl_en timing parameters */
+ UINT32 TWdqlvlWwNow; /* Configures the t_wdqlvl_ww timing parameters */
+ UINT32 TWdqlvlRwNow; /* Configures the t_wdqlvl_rw timing parameters */
+ UINT8 Reserved87[0x1654 - 0x163c]; /* Reserved */
+ UINT32 PhymstrControlNow; /* Determines the DMC behavior during write training operations */
+ UINT8 Reserved88[0x1fd0 - 0x1658]; /* Reserved */
+ UINT32 PeriphId4; /* Peripheral ID register */
+ UINT8 Reserved89[0x1fe0 - 0x1fd4]; /* Reserved */
+ UINT32 PeriphId0; /* Peripheral ID register */
+ UINT32 PeriphId1; /* Peripheral ID register */
+ UINT32 PeriphId2; /* Peripheral ID register */
+ UINT32 PeriphId3; /* Peripheral ID register */
+ UINT32 ComponentId0; /* Component ID register */
+ UINT32 ComponentId1; /* Component ID register */
+ UINT32 ComponentId2; /* Component ID register */
+ UINT32 ComponentId3; /* Component ID register */
+} DMC620_REGS_TYPE;
+
+/* DMC-620 register definitions */
+typedef struct DMC620_ERR_REGS {
+ UINT32 ErrFr; /* Returns the same value programmed in the ERR0FR Global Control Record Feature Register */
+ UINT32 Reserved; /* Reserved */
+ UINT32 ErrCtlr; /* This register is reserved */
+ UINT32 Reserve1; /* Reserved */
+ UINT32 ErrStatus; /* This status register reports error type, status, and contains valid bits for extra syndrome registers */
+ UINT32 Reserved2; /* Reserved */
+ UINT32 ErrAddr0; /* Contains the physical address LSB's associated with the error */
+ UINT32 ErrAddr1; /* Contains the physical address MSB's associated with the error */
+ UINT32 ErrMisc0; /* This register gives the Physical Rank, Row, and Column of the last error detected before an interrupt is asserted */
+ UINT32 ErrMisc1; /* This register gives the Physical Rank, Logical Rank, and failed nobble location the last error detected before an interrupt is asserted */
+ UINT32 ErrMisc2; /* DRAM correctable Error Counter Access restrictions */
+ UINT32 ErrMisc3; /* DRAM correctable Error Counter Access restrictions */
+ UINT32 ErrMisc4; /* DRAM correctable Error Counter Access restrictions */
+ UINT32 ErrMisc5; /* DRAM correctable Error Counter Access restrictions */
+ UINT8 Reserved3[0x780 - 0x778]; /* Reserved */
+} DMC620_ERR_REGS_TYPE;
+
+#define DMC620_0 ((DMC620_REGS_TYPE *)(MEMORY_CONTROLLER_BASE + 0x00000000))
+#define DMC620_1 ((DMC620_REGS_TYPE *)(MEMORY_CONTROLLER_BASE + 0x00100000))
+#define DMC620_2 ((DMC620_REGS_TYPE *)(MEMORY_CONTROLLER_BASE + 0x00200000))
+#define DMC620_3 ((DMC620_REGS_TYPE *)(MEMORY_CONTROLLER_BASE + 0x00300000))
+
+EFI_STATUS
+Dmc620RasInitialize (
+ IN EFI_HANDLE mageHandle,
+ IN EFI_SMM_SYSTEM_TABLE2 *SystemTable
+ );
+
+EFI_STATUS
+EFIAPI
+Dmc620RasEventHandler (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *Context, OPTIONAL
+ IN OUT VOID *CommBuffer, OPTIONAL
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ );
+
+EFI_STATUS
+EFIAPI
+Dmc620ErrorInjectEventHandler (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *Context, OPTIONAL
+ IN OUT VOID *CommBuffer, OPTIONAL
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ );
+
+EFI_STATUS
+Dmc620RasSetCorrectableErrorThreshold (
+ IN volatile DMC620_ERR_REGS_TYPE *DmcRegs,
+ IN ERR_RECORD_TABLE_TYPE ErrRecType,
+ IN UINT32 ErrThreshold
+ );
+
+EFI_STATUS
+Dmc620Status (
+ IN volatile DMC620_REGS_TYPE *DmcCtrl
+ );
+
+VOID
+Dmc620DrainCmd (
+ IN volatile DMC620_REGS_TYPE *DmcCtrl
+ );
+
+EFI_STATUS
+EFIAPI
+Dmc620ErrorSourceInfoGet (
+ IN EFI_MM_RAS_ERROR_SOURCE_INFO_PROTOCOL *This,
+ OUT EFI_APEI_ERROR_SOURCE **Buffer,
+ OUT UINTN *ErrorSourceCount
+ );
+
+#endif /* _DMC620_RAS_DRIVER_H_ */
|