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2020-01-24use CramFS XIP file Magic in place of CPIORui Miguel Silva
Removing copying the rootfs to SRAM. Because the rootfs is a CramFS XIP filesystem stored in flash, there is no need to copy it to DDR. Change-Id: I706d709050ae98a9b07fc00bb97c1d824f9399e6 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-01-24add sdc-600 module for secure debugging supportTushar Khandelwal
This driver module add support for sdc-600 which enables secure debugging using Arm Coresight.There is one internal and external internal COM port for the communication between the debugger and debugged system. links: Advanced Communication channel: http://infocenter.arm.com/help/topic/com.arm.doc.subset.coresight.architecture/index.html SDC-600 : http://infocenter.arm.com/help/topic/com.arm.doc.101130_0002_02_en/coresight_sdc_600_technical_reference_manual_101130_0002_02_en.pdf Change-Id: I579b026500f4f38fc45186a033817fd7ca6e9798 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2020-01-07wait till enable/disable mpl takes effectAvinash Mehta
Arm recommends to wait for the associated RGN_ST.MPE_EN bit reflects the enabling/disabling of MPE Change-Id: I3c4d5373765a7ac1dd1bf23a9a96ce151aaac9d4 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07adding initialization api for mplAvinash Mehta
This change adds fc_init_mpl api to initialize the mpl and brings them to a known state as Arm recommends setting RGN_MPL register before enabling MPE. Change-Id: I6f9f204af54d3542db490ba47c8c55dd548cfb6d Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07clear rgn_size reg before programmingAvinash Mehta
This change clears the rgn_size register before programming it, as the reset value is rgn_size register is UNKNOWN and Arm recommends to set register to a known value before performing read-modify-write operations Change-Id: I6edadccfd33e1c331f9df1e086b091876e779989 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07disable mpe before programming regionsVishnu Banavath
This change disables the master permission entry before programming the regions as recommended by the firewall specification. Change-Id: Ic8c769cd16c17894c34bc0805e4191df0b6d2c0f Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07copy DTB and ROOTFS to DDR from Flash during bootVishnu Banavath
These changes copy DTB and ROOTFS to DDR from Flash Change-Id: Ief27faa2c3d989e1c2c6be234c42b89b859d8485 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07add support to access OCVM from boot processorVishnu Banavath
This change adds firewall policies to access OCVM(DDR) from boot processor. 1) boot processor can access 512MB of DDR through the host access region 2) memory attributes enabled in host_firewall_setup allows both secure and non-secure accesses from all masters Change-Id: Ia4c507510610784c6727170d8e634fc2cba6d69a Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07add enums for firewall component IDsAvinash Mehta
This change adds enum for secure enclave and host firewall comp IDs. Change-Id: I4abebb734422cc5d5ea2d3d0cb85dc8a22ee2318 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2020-01-07host_boot: change hardcoded value to a macro for ROOTFS SIZEVishnu Banavath
This change is to change the size of ROOTFS from a hardcoded value to a macro. Change-Id: Id654749befc9d3c2a1b635bef555db87067d0d39
2020-01-07firewall: reduce rootfs size to 2MBVishnu Banavath
As FPGA and FVP now have 8MB of flash and rootfs is less than 4MB. This change is to reduce rootfs size to 2MB Change-Id: Iced3a36561165983ba5afad1a95a262bda55d14c
2019-09-13change the initialization order of firewallCORSTONE-700-2019.09.23Avinash Mehta
Change-Id: I86f1feddab99374a1582bac6b5f070efc558b354 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-13add host firewall lock extention support and APIsAvinash Mehta
Change-Id: I29ff1eacddec5620be8b5e2a3149832e74b8bb68 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-13add host firewall protection extention supportAvinash Mehta
Change-Id: I34e31b8c95d907107f074459342cf6e06da305f8 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-13changing mpu settings for host window addressesAvinash Mehta
Change-Id: I619d9c3b1735a8d7ee4e78ce8dc7cc953a83bb32 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-13rewrite firewall IP driverAvinash Mehta
Restructured firewall driver code Added APIs for FC and FCTRL registers Added seperate firewall driver file Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Change-Id: Ie66ab96a7ea914b5ba7396e34b052d3b46b2f89e
2019-09-04moving all modules to single folderAvinash Mehta
moving contents of product/corstone-700/module to module folder Change-Id: I1b1dc32001929dcc082542ab0a1e3be613d47ffc Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-04change uart clock to 32 MHz as per FPGAAvinash Mehta
Change-Id: I47ac67dedd410368bb8eae8e3e22cf70735f5d0d Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-04wakeup core0 before brining it out of resetVishnu Banavath
Change-Id: I7687db08544cd00e3a3d3a1bcf2d12900d0b528c
2019-09-04disable boot-firmware FC1 bypass modeAvinash Mehta
Change-Id: If5d78a11fa511824f672c3da85a05f8e19004006 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-04clean-up as per coding style guideAvinash Mehta
Running check_spacing.py, check_tabs.py, check_style.py on the codebase and making required changes Change-Id: I2710243bc823e9c05b83fa3c2f80f1eeda7d98fd Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-09-04fix the wrong register write issueTushar Khandelwal
Change-Id: If67185e2d96b7baa1d7215982ebaf7ceef2b9ad9 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04use irq enum instead of variableTushar Khandelwal
Change-Id: I442b35334b1d262a76588eb389a4cccbccb1e314 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04enable combined receiver interrupt when using MHUv2.1Morten Borup Petersen
Change-Id: I1828b09ba1ce7c773fa477a1286dad71af9992af Signed-off-by: Morten Borup Petersen <morten.petersen@arm.com>
2019-09-04add Firewall IP support and program boot processor firewall.Manish Pandey
Corstone-700 has two Firewall IP's one with boot processor and other in Host System, both will be programmed in boot processor as it is root of trust. This patch introduces Firewall module and also the programming of SE Firewall translation of Host access regions. Following four Host regions are currently accessed from SE 1. Boot Instruction Register 2. Shared RAM 3. Execute in Place(XIP) Flash 4. Host peripheral regions Change-Id: Ice81cd119bddf3db9beca1cf6a12915b0e851479 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2019-09-04changes to test timer routing with the test appMorten Borup Petersen
This commit adds testing of the timer and interrupt router modules.The test may be started by receiving the enumerated command value on the Non Secure channel(MHU1). Change-Id: If0a69c7bed8f5bb16b878e725807e0837031ea11 Signed-off-by: Morten Borup Petersen <morten.petersen@arm.com>
2019-09-04add event handler moduleMorten Borup Petersen
This commit introduces a module for handling events which may be triggered when unit testing the platform. In this commit, support for handling commands received by the rpmsg driver is introduced. These commands tie into the MHU test application(s) running in the corstone-700 CI setup. Change-Id: I11b58fe10b6b87ce2c5122cb81c8ab2a67948600 Signed-off-by: Morten Borup Petersen <morten.petersen@arm.com>
2019-09-04use MHU channel lookup in rpmsg driverMorten Borup Petersen
this commit removes the hardcoded framework IDs for the boot firmware < = > HOST MHU 0 & 1 channels and replaces them with a call to the lookup function in the mhu driver. Change-Id: Ifc4ff8a7c607901bd7e221314f45d166ede178ae Signed-off-by: Morten Borup Petersen <morten.petersen@arm.com>
2019-09-04add MHU channel fwk id lookup based on destination addressMorten Borup Petersen
This commit implements lookup of a channel which is registered as a module element within the boot firmware framework. Based on the destination address (which is stored as the transmit address of an MHU channel), a framework ID can be built. Change-Id: I7df06b0c1bdf421172f99b5e1968af9842f8888f Signed-off-by: Morten Borup Petersen <morten.petersen@arm.com>
2019-09-04add interrupt router driverTushar Khandelwal
Change-Id: Ia49cc2db440b6203b176c686a2e1fb5a06d77349 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add generic timer and timer hal supportTushar Khandelwal
Change-Id: I830b68d6ce5136ba3bc34f5081579ee8788ddbb7 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add interrupt collator moduleMorten Borup Petersen
Change-Id: I8cda33045588d6b6fabf171ba8c9a07e48d8bee1 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add openamp and rpmsg client supportTushar Khandelwal
Change-Id: I17acb83977e699f6104558d2bdf2856e8fa9fb79 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add support for mhuv2Tushar Khandelwal
Change-Id: I5cd334904499fd2eb540aa10af847bca3c47fdcd Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add host boot moduleManish Pandey
this module will: 1. encode boot instruction regsiter (BIR) of Host Cortex A32 2. get infomation from fip parser to copy DTB and root file system in shared RAM 3. release Host from reset Change-Id: Id2211f5b6e92b969f1c839f7251008e974798c84 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2019-09-04add TF-A fip parser moduleTushar Khandelwal
this module parse TF-A fip generated as part of TF-A build. It will detect the number of images it contatin and information about the images by reading there UUID Change-Id: I2a6a3b4eb33350fdf2b0984294c347ce9ddf84c5 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add spitoc parser module in ramfw to find offset of TF-A FIPTushar Khandelwal
Change-Id: Ide06f1e95756de7be56fac865ef3295a1ddb25d6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add ramfw support using RTX RTOSTushar Khandelwal
this patch adds sipport for booting RTX RTOS in boot processors SRAM Change-Id: I8641839926bda1a0a8786a3958ca0c4a2b06315d Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add ram firmware loaderTushar Khandelwal
this module load ram firmware from flash after getting the offset from spitoc module.the firmware is loaded into boot processor SRAM Change-Id: I7f0ffc752d86c739355e4a3d90e79709556b17ca Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add spitoc parser moduleTushar Khandelwal
this module parse the SPI flash table of contents. this information is present on flash at 0x0 in the form of a binary called spitoc.bin created by using spitoccreater tool.It has file offset, size and flags of ram firmware and Host TF-A FIP image.This is then parsed by rom firmware to load ram firmware. Change-Id: If7ca74a9d43e6e2d12954f56c9854d247121a9b9 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add corstone700 rom firmware supportTushar Khandelwal
Change-Id: Ibd0d2ee8b6e5ac12ace0c5728316bca1d1968520 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add spitoc creator toolTushar Khandelwal
this tool creates a binary which has TF-A FIP's and boot processor's ram firmware information like (size, offset, header etc.) how to run: spitoc --seram <ram firmware binary> --offset <in KB> --fip <TF-A FIP> --offset <in KB> --out <spitoc.bin> Change-Id: Ibc1130e22d606874476cc29cea2f555ca735f417 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add pl011 uart driver and log moduleTushar Khandelwal
Change-Id: I601e20ba519f21bba968fb19af919ba5eab1d861 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2019-09-04add base firmware frameworktushar khandelwal
this commit adds support for architecture, nvic, framework and build tools Change-Id: I0583a0795b8c3dac63a31694b75096ba89374ac7 Signed-off-by: tushar khandelwal <tushar.khandelwal@arm.com>
2019-09-04add license.mdtushar khandelwal
Change-Id: I8d590d9ed85408edbcef7f5b7e306bbd7ca3896a Signed-off-by: tushar khandelwal <tushar.khandelwal@arm.com>
2019-05-14Initial commitRui Miguel Silva
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 12:26:53 +0000