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| author | Arnold Gabriel Benedict <arnoldgabriel.benedict@arm.com> | 2021-04-26 16:16:08 +0530 |
|---|---|---|
| committer | Khasim Syed Mohammed <khasim.mohammed@arm.com> | 2021-04-29 12:42:11 +0530 |
| commit | 0234f9e6299f9266944bbc5878269f860a6592e8 (patch) | |
| tree | 694bb49b61ae2af45f7eb56f4ae7820a1410b274 | |
| parent | 16d908e418ba6b6bb8d74689b884ac40abd9f381 (diff) | |
n1sdp: add documentation to enable L3 cache
Signed-off-by: Arnold Gabriel Benedict <arnoldgabriel.benedict@arm.com>
Change-Id: I56e9dc1cb3c964a66c12313268544353e1f987ff
| -rw-r--r-- | user-guide.rst | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/user-guide.rst b/user-guide.rst index 7245727..57cba17 100644 --- a/user-guide.rst +++ b/user-guide.rst @@ -373,6 +373,20 @@ Example command to switch to 300k_8c2.bin from the host PC:: $> sudo sed -i '/^;MBPMIC: 300k_8c2.bin/s/^;//g' /mnt/MB/HBI0316A/io_v123f.txt $> sudo umount /mnt +L3 Cache Enablement +################### + +By default, L3 cache is disabled for use. To enable/disable L3 cache support, follow these steps: + + 1. Run USB_ON command to mount the on-board microSD card on the host PC. + 2. Open the file "MB/HBI0316A/io_v123f.txt". + 3. For user to enable/disable L3 cache support, edit the SCC BOOT_GPR1 register in the following manner. + * To enable L3 cache, update the SOCCON with offset 0x1184 and set the value 0x00000001. The line should now read, + ``SOCCON: 0x1184 0x00000001 ; SoC SCC BOOT_GPR1`` + + * To disable L3 cache, update the SOCCON with offset 0x1184 and set the value 0x00000000. The line should now read, + ``SOCCON: 0x1184 0x00000000 ; SoC SCC BOOT_GPR1`` + 4. Save and close the file. Boot Poky on N1SDP ################## @@ -518,4 +532,4 @@ booting. ---------- -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2021, Arm Limited. All rights reserved.* |