| Age | Commit message (Collapse) | Author |
|---|
|
Because Xenon SD/MMC controller isn't fully compatible with SDHC, it
demands some quirks on generic driver during initialization, i.e.
limit bus width to 4, no voltage switch and hence disable highest
speed modes, etc. Moreover, Xenon-specific init sequence is required,
because it configures custom set of registers of Sd/Mmc PHY.
Two files containing Xenon-specific functions and defines were added.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
|
|
EFI_D_INFO, EFI_D_VERBOSE, EFI_D_WARN and EFI_D_ERROR are replaced
with currently recommended values.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Import SdMmcPciHcDxe stack from tianocore/edk2 tree at revision
a5991c8832c5: "IntelSiliconPkg: Add PCD for Graphics VBT FFS GUID".
Because Marvell Xenon SD/MMC controller isn't fully compatible with
SDHCI specification, it demands some quirks on generic driver during
initialization. In order to achieve that,
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe stack is imported and
adjusted correctly in following commit. Also in next patch's commit
message necessary changes to generic driver are listed.
Xenon SD/MMC controller is present on Marvell Armada70x0 SoCs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Pp2Dxe supports Marvell PP2 NIC. It comprise up to 3 ports in a single
unit (1x 10G and 2x 2.5G). Also parser and hardware buffer manager offload
engines support are enabled, as their usage is obligatory.
EFI_SIMPLE_NETWORK_PROTOCOL is implemented for configurable number
of interfaces via PCD.
This patch introduces also an OS-independent library with the
configuration routines of the PP2 NIC. It is obtained
from Marvell and adjusted to EDK2 coding style.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
I2c driver will now enumerate all devices from the PCD table without
assumption that this table ends with '\0' entry. This condition occurred
to be toolchain-dependent. Size of table will be gathered from PCD's size.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Removed unnecessary SetMem().
Replaced CopyMem() with direct copy of structure members.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
size
Corrected the Ethernet frame size to 1566 to cover the IPv6 case.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
This implements a PCI driver for the Renesas PD720201/PD720202 PCIe
XHCI controller, which in some cases requires a device firmware to be
uploaded by the system firmware in order to function.
By registering a UEFI driver with high dispatch priority, this driver
is able to access the device early, install the firmware, and then decline
the driver dispatch so that the device is fully functional when the real
XHCI driver gets to see it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The RX path in MarvellYukonDxe uses DMA buffers allocated via
EFI_PCI_IO_PROTOCOL::AllocateBuffer(), and copies the contents of each
into temporary buffers, whose contents are copied yet another time before
arriving at the caller of EFI_SIMPLE_NETWORK_PROTOCOL::Receive()
This is inefficient for two reasons:
- the streaming bus master DMA operations used for RX do not require the
use of buffers allocated via EFI_PCI_IO_PROTOCOL::AllocateBuffer(), which
may return uncached memory on platforms with non-coherent DMA
- EFI_PCI_IO_PROTOCOL::AllocateBuffer() performs page based allocations,
which means the UEFI memory map is modified for every packet received,
now that the improper reuse of DMA buffers has been fixed.
So drop the call to EFI_PCI_IO_PROTOCOL::AllocateBuffer(), and instead,
perform a pool allocation whose ownership is transferred from the RX ring
to the RX linked list, which removes the need for a copy.
Also, since pool allocations decay to page based allocations for sizes
that equal or exceed EFI_PAGE_SIZE, reduce MAX_SUPPORTED_PACKET_SIZE to
the Ethernet default of 1500 bytes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Alan Ott <alan@softiron.co.uk>
Tested-by: Alan Ott <alan@softiron.co.uk>
|
|
msk_rxeof() allocates a link object which contains a buffer. If the
buffer can't be allocated, make sure to free the link object.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
The Dual Address Cycle Attribute is necessary for bus mastering PCI devices
which are capable of generating 64-bit addresses. See the "Driver Writer's
Guide for UEFI 2.3.1" version 1.01, section 18.3.2.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Add support for 64-bit DMA transfers, since some 64-bit platforms don't
have the ability to generate DMA addresses which can fit in 32-bits.
This code came from the FreeBSD driver, the one from which this driver was
derived.
This patch makes this driver use 64-bit DMA in all cases, because it was
determined that there is no good way to test whether 64-bit DMA is
required.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Explicitly zero allocated memory for DMA receive buffers to help guard
against security issues.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
The Receive Queue uses system memory for each packet, not DMA memory,
so use the MSK_LINKED_SYSTEM_BUF items for this queue instead of
MSK_DMA_BUF items.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Change the receive buffers to be single-use only. This involves a few
changes that work together:
1. Change msk_newbuf() to not attempt to re-use or free a buffer,
2. Change msk_rxeof() free the buffer when it is done with it,
3. Store a temporary copy of the received data for passing to
the Receive Queue,
4. Call the required Flush() and Unmap() on the DMA buffer.
In addition this means failure to allocate a new buffer is a failure
of msk_rxeof().
Note that this change makes the driver work the way the FreeBSD driver
(from which this driver was derived) works, and this simply removes an
optimization (the code in msk_newbuf() which re-uses the buffers. This
removal of the optimization is done for two reasons:
1. The optimization failed to work for 64-bit DMA transfers;
2. The UEFI specification, version 2.6, section 13.4 requires calls to
Flush() and Unmap() before reading a DMA write buffer from the CPU,
which doesn't fit with the optimization as it existed.
Reverting back to the behavior as it was in the FreeBSD driver solves
number 1 and 2 above, and makes this driver more consistent with
something we know to be working. There is slightly more overhead, but
it is more consistent with the UEFI standard.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
[ardb: replaced struct assignment with gBS->CopyMem()]
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Remove the hard-coded page size and instead use EFI_SIZE_TO_PAGES()
to convert a number of bytes into a number of 4K EFI pages.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The model_name array is only used in DEBUG() calls, and will cause a
warning (or error depending on -Werror*) in RELEASE mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alan Ott <alan@softiron.co.uk>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The UEFI driver for Marvell Yukon NIC, tested as both AArch64 and EBC
on the ARM Juno platform.
For platform independent builds including EBC:
build -a <target_architecture> \
-p OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc \
-m OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf \
-b DEBUG -t <toolchain>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
[some OCD cleanup, delete special MAC-address setting code (for now)]
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
MvPhyDxe implements support for Marvell 1512 PHYs. MARVELL_PHY_PROTOCOL is
produced in order to provide Status and Initialize functions to network
controller drivers. This driver requires MARVELL_MDIO_PROTOCOL to
communicate with PHY device.
Several PCDs were added to enable PHY ids and connection types
configuration. These are described in attached documentation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
MDIO protocol allows PHY drivers to access their resources using SMI bus.
It consists of MARVELL_MDIO_READ and MARVELL_MDIO_WRITE functions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Lan91xDxe was incorrectly imported without CRLF line endings.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The patch is fixing the TX recycle buffer overflow.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The patch is fixing crash on ARP broadcast message when driver attempts
to access NULL memory address.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This patch add driver for managing Spi flash
It consumes MARVELL_SPI_FLASH_PROTOCOL and enables configuration
by PCD entries.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Spi master driver implements MARVELL_SPI_MASTER_PROTOCOL.
It configures and manages SPI controller.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
MvEeprom driver produces MARVELL_EEPROM_PROTOCOL, which can be used by
other drivers or applications. Working EFI_I2C_IO_PROTOCOL is required
by driver to operate.
EEPROM devices' addresses need to be fed via 'PcdEepromI2cAddresses'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
MvI2cDxe driver was adapted to generic UEFI I2C stack. Connection with
following interfaces was required:
- EFI_I2C_MASTER_PROTOCOL
- EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
- EFI_I2C_ENUMERATE_PROTOCOL
Driver exports configuration options via PCDs. Configurable options
include:
- PcdI2cSlaveAddresses - should contain a list of valid I2C devices'
addresses on bus
- PcdI2cBaseAddresses - physical address of I2C controller registers
- PcdI2cClockFrequency - I2c clock frequency on platform
Drivers of devices on I2C bus should never use EFI_I2C_MASTER_PROTOCOL
directly. Instead, these ought to utilise EFI_I2C_IO_PROTOCOL produced
by generic UEFI stack.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Modify ramdisk module to be an EDKII driver, to support RAM emulated
FAT32 file system, so that we can have file system even without real
persistent storage. Substantial coding-style fixes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Import EFI RAM disk module from EDK tool kit:
https://svn.code.sf.net/p/efi-toolkit/code/trunk/efi-toolkit/protocols/ramdisk/
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Imported from Linaro topic branch.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
|
