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The length field of GTDT table should be the whole length of
entire Generic Timer Description Table.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chenhui Sun <sunchenhui@huawei.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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D02 ACPI related files locate in Chips/Hisilicon/Pv660/Pv660Acpitables
D03 ACPI related files will be moved to
Chips/Hisilicon/Hi1610/Hi1610AcpiTables
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <Lefi.Lindholm@linaro.org>
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Set all ACPI tables' ID as below:
EFI_ACPI_ARM_OEM_ID HISI
EFI_ACPI_ARM_OEM_TABLE_ID HISI0660
EFI_ACPI_ARM_OEM_REVISION 0x00000000
EFI_ACPI_ARM_CREATOR_ID INTL
EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Note that D02 SATASSDT/SASSSDT tables are not updated because we need
different SSDT OEM TABLE ID uesed for UninstallACPI driver
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chenhui Sun <sunchenhui@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The UART on Hip05 soc is not 16550 compatible, use appropriate ACPI ID
for Hisi uart instead of APM one, and delete the wrong comments.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The register of Hilink needs to be configed, but the current procedure
does not do that. The temporary variable to be set to register is wrong,
it must be Local0 instead of Local1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Kejian Yan <yankejian@huawei.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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It is PORT_TP type if the service port is GE mode. It is wrong to
judge the port type by using if it is service port. Adding the media
type to know port type.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Kejian Yan <yankejian@huawei.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Refine serdes lib structure and modify the file which
using this lib accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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1. Rename Pv660.dsc.inc and Pv660.fdf.inc to Hisilicon and move it
to Hisilicon root path.
2. Modify D02/D03 dsc and fdf accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Modify OemGetSerdesParam interface to support D05, for it has 2 sockets
on the board, and each socket has 2 IO super clusters. The interface
is modified to support getting serdes parameter for both IO super clusters
(denoted as A and B) on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Peicong Li <lipeicong@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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com.asl: add reg-io-width and reg-shift package,
for kernel using to set com port.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Move away from ArmPkg's BaseMemoryLibStm, which is deprecated and about
to be removed. For SEC and PEI phases, move to the generic MdePkg version
instead, and for later phases, use the accelerated BaseMemoryLibOptDxe
implementation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The D02 and D03 platforms perform non-trivial operations in their PEI
phases, and on top of that, the definitions inside !ifdef EDK2_SKIP_PEICORE
blocks are very much out of date. So simply remove EDK2_SKIP_PEICORE and
everything that depends on it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Heyi Guo <heyi.guo@linaro.org>
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IoInitDxe uses the MemoryAllocationLib API, but does not declare it in
its .inf file. This will cause breakage when this dependency is no longer
fulfilled indirectly via another library, so make it explicit by adding it
to the .inf.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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According to the ACPI 6.0/6.1 spec, the physical base address of GICC,
GICD, GICR and GIC ITS is 64-bit. This patch is trying to fix the
original 32-bit width by using FixedPcdGet64() instead of FixedPcdGet32().
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Now that the page table manipulation code has been split off from ArmLib
into ArmMmuLib, we need a resolution for this new library class in all
platforms. For most platforms, this is simply a matter of adding a new
line
ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
to a common [LibraryClass] section.
For D02/D03, which were users of the special PEI_CORE/PEIM implementation
of ArmLib, we drop the reference to this special version from the
[LibraryClasses.PEI_CORE] section (since PEI core does use ArmLib but does
not use the MMU code), and replace the one in [LibraryClasses.PEIM] with
the new ArmMmuPeiLib.inf implementation, which is the new version that
takes care not to issue cache maintenance ops on NOR flash.
In two cases, existing out of tree users of ArmConfigureMmu() need to have
their .inf and #include section updated to add the ArmMmuLib reference.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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PlatformSasProtocol is added for init sas device as well as
transferring controller base address.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Enable Hisilicon D02 platform with features including:
SPI Flash driver
Address map library
Memory initialization PEIM
SEC setting up a simple EL3 exception vector
ARM Trusted Firmware
Early platform configuration PEIM
Other common drivers helping system to boot to UEFI shell
EBL binary
Ramdisk driver (created with 128MB ramdisk)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch contains common drivers and libraries for Hisilicon
platforms, used by the subsequent support for D02 and D03.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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