From 761bbcb74e4611414937ea480ba60bb970648755 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 24 Jan 2012 22:17:38 +0100 Subject: usb: ehci-fsl: set INCR8 mode for system bus interface on MPC512x Use INCR8 mode for system bus interface of the USB controller on MPC512x. This is a work-around for the AHB bus lock up problem observed on MPC512x when there is heavy simultaneous PATA write or network (FEC) activity. See also "12.4 The USB controller can issue transactions that lock up the AHB bus under certain conditions" in MPC5121e (M36P) Errata. Signed-off-by: Anatolij Gustschin Tested-by: Matthias Fuchs Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index e90344a17631..42414cd73571 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -316,7 +316,9 @@ static int ehci_fsl_setup(struct usb_hcd *hcd) struct ehci_hcd *ehci = hcd_to_ehci(hcd); int retval; struct fsl_usb2_platform_data *pdata; + struct device *dev; + dev = hcd->self.controller; pdata = hcd->self.controller->platform_data; ehci->big_endian_desc = pdata->big_endian_desc; ehci->big_endian_mmio = pdata->big_endian_mmio; @@ -346,6 +348,16 @@ static int ehci_fsl_setup(struct usb_hcd *hcd) ehci_reset(ehci); + if (of_device_is_compatible(dev->parent->of_node, + "fsl,mpc5121-usb2-dr")) { + /* + * set SBUSCFG:AHBBRST so that control msgs don't + * fail when doing heavy PATA writes. + */ + ehci_writel(ehci, SBUSCFG_INCR8, + hcd->regs + FSL_SOC_USB_SBUSCFG); + } + retval = ehci_fsl_reinit(ehci); return retval; } @@ -469,6 +481,8 @@ static int ehci_fsl_mpc512x_drv_resume(struct device *dev) ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, hcd->regs + FSL_SOC_USB_ISIPHYCTRL); + ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); + /* restore EHCI registers */ ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); -- cgit v1.2.3 From 4c954326823585bd014f36b2babd39c107c2bbb4 Mon Sep 17 00:00:00 2001 From: Pan Jiafei Date: Fri, 17 Feb 2012 13:57:16 +0800 Subject: USB: ehci-fsl: Turn on cache snooping on MPC8xxx If a MPC8xxx was being used, 'have_sysif_regs' should be set and it should setup cache snooping for all the 4GB space on both PPC32 and PPC64. Signed-off-by: Pan Jiafei Acked-by: Li Yang Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 10e008a730a5..cd30ea4416a6 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -252,21 +252,18 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) if (pdata->have_sysif_regs) { temp = in_be32(non_ehci + FSL_SOC_USB_CTRL); out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004); - out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b); - } - -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) - /* - * Turn on cache snooping hardware, since some PowerPC platforms - * wholly rely on hardware to deal with cache coherent - */ - /* Setup Snooping for all the 4GB space */ - /* SNOOP1 starts from 0x0, size 2G */ - out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB); - /* SNOOP2 starts from 0x80000000, size 2G */ - out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB); -#endif + /* + * Turn on cache snooping hardware, since some PowerPC platforms + * wholly rely on hardware to deal with cache coherent + */ + + /* Setup Snooping for all the 4GB space */ + /* SNOOP1 starts from 0x0, size 2G */ + out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB); + /* SNOOP2 starts from 0x80000000, size 2G */ + out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB); + } if ((pdata->operating_mode == FSL_USB2_DR_HOST) || (pdata->operating_mode == FSL_USB2_DR_OTG)) -- cgit v1.2.3 From 28c56ea1431421dec51b7b229369e991481453df Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 16 Feb 2012 18:02:20 +0800 Subject: powerpc/usb: fix bug of kernel hang when initializing usb If USB UTMI PHY is not enable, writing to portsc register will lead to kernel hang during boot up. Signed-off-by: Shengzhou Liu Reported-by: Benjamin Herrenschmidt Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index cd30ea4416a6..7a15c2235758 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -216,6 +216,8 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, unsigned int port_offset) { u32 portsc; + struct usb_hcd *hcd = ehci_to_hcd(ehci); + void __iomem *non_ehci = hcd->regs; portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); @@ -231,6 +233,8 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, portsc |= PORT_PTS_PTW; /* fall through */ case FSL_USB2_PHY_UTMI: + /* enable UTMI PHY */ + setbits32(non_ehci + FSL_SOC_USB_CTRL, CTRL_UTMI_PHY_EN); portsc |= PORT_PTS_UTMI; break; case FSL_USB2_PHY_NONE: -- cgit v1.2.3 From b96d3b08365f5a9603f50f3aadca6012f7eaffa1 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Mon, 13 Feb 2012 13:24:18 +0200 Subject: usb: Convert all users to new usb_phy Use the new usb_phy_* functions with transceiver operations instead of the old otg functions. Includes fixes from Sascha Hauer. Signed-off-by: Heikki Krogerus Acked-by: Sascha Hauer Acked-by: Pavankumar Kondeti Acked-by: Li Yang Acked-by: Alan Stern Reviewed-by: Marek Vasut Signed-off-by: Felipe Balbi --- drivers/usb/host/ehci-fsl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index b556a72264d1..481effdc7f54 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -142,7 +142,7 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver, if (pdata->operating_mode == FSL_USB2_DR_OTG) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); - ehci->transceiver = otg_get_transceiver(); + ehci->transceiver = usb_get_transceiver(); dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, transceiver=0x%p\n", hcd, ehci, ehci->transceiver); -- cgit v1.2.3 From 6e13c6505cdff9766d5268ffb8c972c1a2f996e6 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Mon, 13 Feb 2012 13:24:20 +0200 Subject: usb: otg: Convert all users to pass struct usb_otg for OTG functions This changes the otg functions so that they receive struct otg instead of struct usb_phy as parameter and converts all users of these functions to pass the otg member of their usb_phy. Includes fixes to IMX code from Sascha Hauer. [ balbi@ti.com : fixed a compile warning on ehci-mv.c ] Signed-off-by: Heikki Krogerus Acked-by: Sascha Hauer Acked-by: Igor Grinberg Acked-by: Pavankumar Kondeti Acked-by: Li Yang Acked-by: Alan Stern Reviewed-by: Marek Vasut Signed-off-by: Felipe Balbi --- drivers/usb/host/ehci-fsl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 481effdc7f54..4786ba5f2e6c 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -147,7 +147,7 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver, hcd, ehci, ehci->transceiver); if (ehci->transceiver) { - retval = otg_set_host(ehci->transceiver, + retval = otg_set_host(ehci->transceiver->otg, &ehci_to_hcd(ehci)->self); if (retval) { if (ehci->transceiver) @@ -194,7 +194,7 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd, struct ehci_hcd *ehci = hcd_to_ehci(hcd); if (ehci->transceiver) { - otg_set_host(ehci->transceiver, NULL); + otg_set_host(ehci->transceiver->otg, NULL); put_device(ehci->transceiver->dev); } -- cgit v1.2.3 From 79857e8e7b1ba740f8025b540f1e171c9a0a5d31 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Sat, 25 Feb 2012 23:56:30 +0800 Subject: powerpc/usb: fix usb CTRL_PHY_CLK_VALID breaks on some platform Fix checking of CTRL_PHY_CLK_VALID bit break on some platform on which there is not USB CTRL_PHY_CLK_VALID bit. - P1023/P3041/P5020 etc,have this bit - P3060/4080/PSC913x do have this bit, but not mentioned in RM. - P1022(perhaps and other) has no this bit Signed-off-by: Shengzhou Liu Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 7a15c2235758..e9d8a0cca47b 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -248,7 +248,11 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) struct usb_hcd *hcd = ehci_to_hcd(ehci); struct fsl_usb2_platform_data *pdata; void __iomem *non_ehci = hcd->regs; - u32 temp; + u32 temp, chip, rev, svr; + + svr = mfspr(SPRN_SVR); + chip = svr >> 16; + rev = (svr >> 4) & 0xf; pdata = hcd->self.controller->platform_data; @@ -274,12 +278,6 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); if (pdata->operating_mode == FSL_USB2_MPH_HOST) { - unsigned int chip, rev, svr; - - svr = mfspr(SPRN_SVR); - chip = svr >> 16; - rev = (svr >> 4) & 0xf; - /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) ehci->has_fsl_port_bug = 1; @@ -301,9 +299,15 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); } - if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) { - printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); - return -ENODEV; + /* There is no CTRL_PHY_CLK_VALID bit on some platforms, e.g. P1022 */ +#define SVR_P1022_N_ID 0x80E6 +#define SVR_P1022_S_ID 0x80EE + if (chip != SVR_P1022_N_ID && chip != SVR_P1022_S_ID) { + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & + CTRL_PHY_CLK_VALID)) { + printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); + return -ENODEV; + } } return 0; } -- cgit v1.2.3 From f7c96f59b4af72f51c7835ed073da820bc3786b3 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 29 Feb 2012 16:49:21 -0800 Subject: Revert "powerpc/usb: fix usb CTRL_PHY_CLK_VALID breaks on some platform" This reverts commit 79857e8e7b1ba740f8025b540f1e171c9a0a5d31. To quote Shengzhou Liu: I'm sorry, please don't apply this patch. It appears not only on P1022 platform. There will be more breaks on other platforms regarding CTRL_PHY_CLK_VALID bit. I will post a new patch with well compatibility on all platforms as soon as I get necessary confirmations. Cc: Shengzhou Liu Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) (limited to 'drivers/usb/host/ehci-fsl.c') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index e9d8a0cca47b..7a15c2235758 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -248,11 +248,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) struct usb_hcd *hcd = ehci_to_hcd(ehci); struct fsl_usb2_platform_data *pdata; void __iomem *non_ehci = hcd->regs; - u32 temp, chip, rev, svr; - - svr = mfspr(SPRN_SVR); - chip = svr >> 16; - rev = (svr >> 4) & 0xf; + u32 temp; pdata = hcd->self.controller->platform_data; @@ -278,6 +274,12 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); if (pdata->operating_mode == FSL_USB2_MPH_HOST) { + unsigned int chip, rev, svr; + + svr = mfspr(SPRN_SVR); + chip = svr >> 16; + rev = (svr >> 4) & 0xf; + /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) ehci->has_fsl_port_bug = 1; @@ -299,15 +301,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); } - /* There is no CTRL_PHY_CLK_VALID bit on some platforms, e.g. P1022 */ -#define SVR_P1022_N_ID 0x80E6 -#define SVR_P1022_S_ID 0x80EE - if (chip != SVR_P1022_N_ID && chip != SVR_P1022_S_ID) { - if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & - CTRL_PHY_CLK_VALID)) { - printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); - return -ENODEV; - } + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) { + printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); + return -ENODEV; } return 0; } -- cgit v1.2.3