From f5f1ad322aaba5df1a6dff02724ce9cdd2516a68 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 16 May 2014 13:42:21 -0700 Subject: OMAPDSS: raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/video/fbdev/omap2/dss/dispc.c | 4 ++-- drivers/video/fbdev/omap2/dss/dsi.c | 4 ++-- drivers/video/fbdev/omap2/dss/dss.c | 4 ++-- drivers/video/fbdev/omap2/dss/hdmi.h | 4 ++-- drivers/video/fbdev/omap2/dss/venc.c | 4 ++-- drivers/video/fbdev/omap2/omapfb/omapfb-main.c | 10 +++++----- drivers/video/fbdev/omap2/vrfb.c | 6 +++--- 7 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index 7aa33b0f4a1f..4a1766678a39 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -238,12 +238,12 @@ static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); static inline void dispc_write_reg(const u16 idx, u32 val) { - __raw_writel(val, dispc.base + idx); + writel_relaxed(val, dispc.base + idx); } static inline u32 dispc_read_reg(const u16 idx) { - return __raw_readl(dispc.base + idx); + return readl_relaxed(dispc.base + idx); } static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c index 4755a34a5422..fb3b6a94b876 100644 --- a/drivers/video/fbdev/omap2/dss/dsi.c +++ b/drivers/video/fbdev/omap2/dss/dsi.c @@ -446,7 +446,7 @@ static inline void dsi_write_reg(struct platform_device *dsidev, default: return; } - __raw_writel(val, base + idx.idx); + writel_relaxed(val, base + idx.idx); } static inline u32 dsi_read_reg(struct platform_device *dsidev, @@ -462,7 +462,7 @@ static inline u32 dsi_read_reg(struct platform_device *dsidev, default: return 0; } - return __raw_readl(base + idx.idx); + return readl_relaxed(base + idx.idx); } static void dsi_bus_lock(struct omap_dss_device *dssdev) diff --git a/drivers/video/fbdev/omap2/dss/dss.c b/drivers/video/fbdev/omap2/dss/dss.c index 6daeb7ed44c6..e7d7dc36f37b 100644 --- a/drivers/video/fbdev/omap2/dss/dss.c +++ b/drivers/video/fbdev/omap2/dss/dss.c @@ -105,12 +105,12 @@ static const char * const dss_generic_clk_source_names[] = { static inline void dss_write_reg(const struct dss_reg idx, u32 val) { - __raw_writel(val, dss.base + idx.idx); + writel_relaxed(val, dss.base + idx.idx); } static inline u32 dss_read_reg(const struct dss_reg idx) { - return __raw_readl(dss.base + idx.idx); + return readl_relaxed(dss.base + idx.idx); } #define SR(reg) \ diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index fbee07816337..00de2b50c1f2 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h @@ -365,12 +365,12 @@ struct hdmi_core_data { static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, u32 val) { - __raw_writel(val, base_addr + idx); + writel_relaxed(val, base_addr + idx); } static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) { - return __raw_readl(base_addr + idx); + return readl_relaxed(base_addr + idx); } #define REG_FLD_MOD(base, idx, val, start, end) \ diff --git a/drivers/video/fbdev/omap2/dss/venc.c b/drivers/video/fbdev/omap2/dss/venc.c index 21d81113962b..8095293562ef 100644 --- a/drivers/video/fbdev/omap2/dss/venc.c +++ b/drivers/video/fbdev/omap2/dss/venc.c @@ -310,12 +310,12 @@ static struct { static inline void venc_write_reg(int idx, u32 val) { - __raw_writel(val, venc.base + idx); + writel_relaxed(val, venc.base + idx); } static inline u32 venc_read_reg(int idx) { - u32 l = __raw_readl(venc.base + idx); + u32 l = readl_relaxed(venc.base + idx); return l; } diff --git a/drivers/video/fbdev/omap2/omapfb/omapfb-main.c b/drivers/video/fbdev/omap2/omapfb/omapfb-main.c index ec2d132c782d..5f345413d3e6 100644 --- a/drivers/video/fbdev/omap2/omapfb/omapfb-main.c +++ b/drivers/video/fbdev/omap2/omapfb/omapfb-main.c @@ -82,18 +82,18 @@ static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color) g = g * 64 / 256; b = b * 32 / 256; - __raw_writew((r << 11) | (g << 5) | (b << 0), p); + writew_relaxed((r << 11) | (g << 5) | (b << 0), p); } else if (var->bits_per_pixel == 24) { u8 __iomem *p = (u8 __iomem *)addr; p += (y * line_len + x) * 3; - __raw_writeb(b, p + 0); - __raw_writeb(g, p + 1); - __raw_writeb(r, p + 2); + writeb_relaxed(b, p + 0); + writeb_relaxed(g, p + 1); + writeb_relaxed(r, p + 2); } else if (var->bits_per_pixel == 32) { u32 __iomem *p = (u32 __iomem *)addr; p += y * line_len + x; - __raw_writel(color, p); + writel_relaxed(color, p); } } diff --git a/drivers/video/fbdev/omap2/vrfb.c b/drivers/video/fbdev/omap2/vrfb.c index f346b02eee1d..032469079bfe 100644 --- a/drivers/video/fbdev/omap2/vrfb.c +++ b/drivers/video/fbdev/omap2/vrfb.c @@ -82,17 +82,17 @@ static bool vrfb_loaded; static void omap2_sms_write_rot_control(u32 val, unsigned ctx) { - __raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx)); + writel_relaxed(val, vrfb_base + SMS_ROT_CONTROL(ctx)); } static void omap2_sms_write_rot_size(u32 val, unsigned ctx) { - __raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx)); + writel_relaxed(val, vrfb_base + SMS_ROT_SIZE(ctx)); } static void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx) { - __raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx)); + writel_relaxed(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx)); } static inline void restore_hw_context(int ctx) -- cgit v1.2.3 From bcf0e7f77a5e64115d04b1e02c7c6801ead999de Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 15:23:19 +0200 Subject: mmc: omap: raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/mmc/host/omap.c | 4 ++-- drivers/mmc/host/omap_hsmmc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 81974ecdfcbc..761ff00a65f3 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c @@ -81,8 +81,8 @@ #define mmc_omap2() (!mmc_omap1()) #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) -#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) -#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) +#define OMAP_MMC_READ(host, reg) readw_relaxed((host)->virt_base + OMAP_MMC_REG(host, reg)) +#define OMAP_MMC_WRITE(host, reg, val) writew_relaxed((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) /* * Command types diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 6b7b75585926..125a2d69fb05 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -152,10 +152,10 @@ * MMC Host controller read/write API's */ #define OMAP_HSMMC_READ(base, reg) \ - __raw_readl((base) + OMAP_HSMMC_##reg) + readl_relaxed((base) + OMAP_HSMMC_##reg) #define OMAP_HSMMC_WRITE(base, reg, val) \ - __raw_writel((val), (base) + OMAP_HSMMC_##reg) + writel_relaxed((val), (base) + OMAP_HSMMC_##reg) struct omap_hsmmc_next { unsigned int dma_len; -- cgit v1.2.3 From 2cba7218304e08b87f771f01678a4ecafee34c37 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 18:01:31 +0200 Subject: hwrng: omap - raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/char/hw_random/omap-rng.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c index f66ea258382f..4c8290ad377c 100644 --- a/drivers/char/hw_random/omap-rng.c +++ b/drivers/char/hw_random/omap-rng.c @@ -131,13 +131,13 @@ struct omap_rng_dev { static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg) { - return __raw_readl(priv->base + priv->pdata->regs[reg]); + return readl_relaxed(priv->base + priv->pdata->regs[reg]); } static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg, u32 val) { - __raw_writel(val, priv->base + priv->pdata->regs[reg]); + writel_relaxed(val, priv->base + priv->pdata->regs[reg]); } static int omap_rng_data_present(struct hwrng *rng, int wait) -- cgit v1.2.3 From 10acff9b825f2925176e4f9b0ab03c473cb90d01 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 18:07:16 +0200 Subject: crypto: omap-aes - raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/crypto/omap-aes.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c index cb98fa54573d..71a26d1f2838 100644 --- a/drivers/crypto/omap-aes.c +++ b/drivers/crypto/omap-aes.c @@ -195,7 +195,7 @@ static DEFINE_SPINLOCK(list_lock); #define omap_aes_read(dd, offset) \ ({ \ int _read_ret; \ - _read_ret = __raw_readl(dd->io_base + offset); \ + _read_ret = readl_relaxed(dd->io_base + offset); \ pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ offset, _read_ret); \ _read_ret; \ @@ -203,7 +203,7 @@ static DEFINE_SPINLOCK(list_lock); #else static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) { - return __raw_readl(dd->io_base + offset); + return readl_relaxed(dd->io_base + offset); } #endif @@ -212,13 +212,13 @@ static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) do { \ pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ offset, value); \ - __raw_writel(value, dd->io_base + offset); \ + writel_relaxed(value, dd->io_base + offset); \ } while (0) #else static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value) { - __raw_writel(value, dd->io_base + offset); + writel_relaxed(value, dd->io_base + offset); } #endif -- cgit v1.2.3 From d273f4616290b83672f85ef8e0aa0bf1a0f655e9 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 18:10:47 +0200 Subject: crypto: omap-sham - raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/crypto/omap-sham.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c index 710d86386965..3c0858657e3f 100644 --- a/drivers/crypto/omap-sham.c +++ b/drivers/crypto/omap-sham.c @@ -244,13 +244,13 @@ static struct omap_sham_drv sham = { static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) { - return __raw_readl(dd->io_base + offset); + return readl_relaxed(dd->io_base + offset); } static inline void omap_sham_write(struct omap_sham_dev *dd, u32 offset, u32 value) { - __raw_writel(value, dd->io_base + offset); + writel_relaxed(value, dd->io_base + offset); } static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, -- cgit v1.2.3 From 58dcda90331dbaf32ebffbe05c9e2911cbf25853 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 18:15:39 +0200 Subject: Input: omap-keypad - raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/input/keyboard/omap4-keypad.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c index 024b7bdffe5b..542d75a542d6 100644 --- a/drivers/input/keyboard/omap4-keypad.c +++ b/drivers/input/keyboard/omap4-keypad.c @@ -87,26 +87,26 @@ struct omap4_keypad { static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset) { - return __raw_readl(keypad_data->base + + return readl_relaxed(keypad_data->base + keypad_data->reg_offset + offset); } static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32 value) { - __raw_writel(value, + writel_relaxed(value, keypad_data->base + keypad_data->reg_offset + offset); } static int kbd_read_irqreg(struct omap4_keypad *keypad_data, u32 offset) { - return __raw_readl(keypad_data->base + + return readl_relaxed(keypad_data->base + keypad_data->irqreg_offset + offset); } static void kbd_write_irqreg(struct omap4_keypad *keypad_data, u32 offset, u32 value) { - __raw_writel(value, + writel_relaxed(value, keypad_data->base + keypad_data->irqreg_offset + offset); } @@ -293,7 +293,7 @@ static int omap4_keypad_probe(struct platform_device *pdev) dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); goto err_unmap; } - rev = __raw_readl(keypad_data->base + OMAP4_KBD_REVISION); + rev = readl_relaxed(keypad_data->base + OMAP4_KBD_REVISION); rev &= 0x03 << 30; rev >>= 30; switch (rev) { -- cgit v1.2.3 From 6469749cf0822ad916d691d19b884670966ddc22 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 19:30:38 +0200 Subject: USB: ehci-omap: raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/usb/host/ehci-omap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index a24720beb39d..f5870aa626ef 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -73,12 +73,12 @@ struct omap_hcd { static inline void ehci_write(void __iomem *base, u32 reg, u32 val) { - __raw_writel(val, base + reg); + writel_relaxed(val, base + reg); } static inline u32 ehci_read(void __iomem *base, u32 reg) { - return __raw_readl(base + reg); + return readl_relaxed(base + reg); } /* configure so an HC device and id are always provided */ -- cgit v1.2.3 From 36f5962458f7b3ac0b7652ee4498425b2d39c767 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Fri, 8 Nov 2013 19:44:09 +0200 Subject: usb: musb: raw read and write endian fix All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- drivers/usb/musb/musb_io.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h index eebeed78edd6..76f4d2afe528 100644 --- a/drivers/usb/musb/musb_io.h +++ b/drivers/usb/musb/musb_io.h @@ -42,17 +42,17 @@ /* NOTE: these offsets are all in bytes */ static inline u16 musb_readw(const void __iomem *addr, unsigned offset) - { return __raw_readw(addr + offset); } + { return readw_relaxed(addr + offset); } static inline u32 musb_readl(const void __iomem *addr, unsigned offset) - { return __raw_readl(addr + offset); } + { return readl_relaxed(addr + offset); } static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data) - { __raw_writew(data, addr + offset); } + { writew_relaxed(data, addr + offset); } static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data) - { __raw_writel(data, addr + offset); } + { writel_relaxed(data, addr + offset); } #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) @@ -65,7 +65,7 @@ static inline u8 musb_readb(const void __iomem *addr, unsigned offset) u16 tmp; u8 val; - tmp = __raw_readw(addr + (offset & ~1)); + tmp = readw_relaxed(addr + (offset & ~1)); if (offset & 1) val = (tmp >> 8); else @@ -78,22 +78,22 @@ static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data) { u16 tmp; - tmp = __raw_readw(addr + (offset & ~1)); + tmp = readw_relaxed(addr + (offset & ~1)); if (offset & 1) tmp = (data << 8) | (tmp & 0xff); else tmp = (tmp & 0xff00) | data; - __raw_writew(tmp, addr + (offset & ~1)); + writew_relaxed(tmp, addr + (offset & ~1)); } #else static inline u8 musb_readb(const void __iomem *addr, unsigned offset) - { return __raw_readb(addr + offset); } + { return readb_relaxed(addr + offset); } static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data) - { __raw_writeb(data, addr + offset); } + { writeb_relaxed(data, addr + offset); } #endif /* CONFIG_USB_MUSB_TUSB6010 */ -- cgit v1.2.3 From 8af84bc79ff74cac9fe69209363eade1f00c4b82 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Thu, 7 Nov 2013 10:32:07 -0800 Subject: ARM: OMAP4: sleep: byteswap data for big-endian Assembler functions defined in sleep44xx.S need to byteswap values after read / before write from h/w register if code compiled in big endian mode. Simple change to do 'rev x, x' before str instruction and after ldr instruction that deals with h/w registers. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- arch/arm/mach-omap2/sleep44xx.S | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 9086ce03ae12..8017016f6953 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "omap-secure.h" @@ -74,6 +75,7 @@ ENTRY(omap4_finish_suspend) */ bl omap4_get_sar_ram_base ldr r9, [r0, #OMAP_TYPE_OFFSET] +ARM_BE8(rev r9, r9) cmp r9, #0x1 @ Check for HS device bne skip_secure_l1_clean mov r0, #SCU_PM_NORMAL @@ -113,12 +115,14 @@ skip_secure_l1_clean: bl omap4_get_sar_ram_base mov r8, r0 ldr r9, [r8, #OMAP_TYPE_OFFSET] +ARM_BE8(rev r9, r9) cmp r9, #0x1 @ Check for HS device bne scu_gp_set mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR ands r0, r0, #0x0f ldreq r0, [r8, #SCU_OFFSET0] ldrne r0, [r8, #SCU_OFFSET1] +ARM_BE8(rev r0, r0) mov r1, #0x00 stmfd r13!, {r4-r12, r14} ldr r12, =OMAP4_MON_SCU_PWR_INDEX @@ -130,6 +134,7 @@ scu_gp_set: ands r0, r0, #0x0f ldreq r1, [r8, #SCU_OFFSET0] ldrne r1, [r8, #SCU_OFFSET1] +ARM_BE8(rev r1, r1) bl omap4_get_scu_base bl scu_power_mode skip_scu_gp_set: @@ -157,6 +162,7 @@ skip_scu_gp_set: ands r5, r5, #0x0f ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory. +ARM_BE8(rev r0, r0) cmp r0, #3 bne do_WFI #ifdef CONFIG_PL310_ERRATA_727915 @@ -167,9 +173,11 @@ skip_scu_gp_set: bl omap4_get_l2cache_base mov r2, r0 ldr r0, =0xffff +ARM_BE8(rev r0, r0) str r0, [r2, #L2X0_CLEAN_INV_WAY] wait: ldr r0, [r2, #L2X0_CLEAN_INV_WAY] +ARM_BE8(rev r0, r0) ldr r1, =0xffff ands r0, r0, r1 bne wait @@ -182,9 +190,11 @@ l2x_sync: bl omap4_get_l2cache_base mov r2, r0 mov r0, #0x0 +ARM_BE8(rev r0, r0) str r0, [r2, #L2X0_CACHE_SYNC] sync: ldr r0, [r2, #L2X0_CACHE_SYNC] +ARM_BE8(rev r0, r0) ands r0, r0, #0x1 bne sync #endif @@ -216,6 +226,7 @@ do_WFI: bl omap4_get_sar_ram_base mov r8, r0 ldr r9, [r8, #OMAP_TYPE_OFFSET] +ARM_BE8(rev r9, r9) cmp r9, #0x1 @ Check for HS device bne scu_gp_clear mov r0, #SCU_PM_NORMAL @@ -258,6 +269,7 @@ ENTRY(omap4_cpu_resume) */ ldr r8, =OMAP44XX_SAR_RAM_BASE ldr r9, [r8, #OMAP_TYPE_OFFSET] +ARM_BE8(rev r9, r9) cmp r9, #0x1 @ Skip if GP device bne skip_ns_smp_enable mrc p15, 0, r0, c0, c0, 5 @@ -292,16 +304,19 @@ skip_ns_smp_enable: */ ldr r2, =OMAP44XX_L2CACHE_BASE ldr r0, [r2, #L2X0_CTRL] +ARM_BE8(rev r0, r0) and r0, #0x0f cmp r0, #1 beq skip_l2en @ Skip if already enabled ldr r3, =OMAP44XX_SAR_RAM_BASE ldr r1, [r3, #OMAP_TYPE_OFFSET] +ARM_BE8(rev r1, r1) cmp r1, #0x1 @ Check for HS device bne set_gp_por ldr r0, =OMAP4_PPA_L2_POR_INDEX ldr r1, =OMAP44XX_SAR_RAM_BASE ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET] +ARM_BE8(rev r4, r4) adr r3, ppa_por_params str r4, [r3, #0x04] mov r1, #0x0 @ Process ID @@ -313,11 +328,13 @@ skip_ns_smp_enable: set_gp_por: ldr r1, =OMAP44XX_SAR_RAM_BASE ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET] +ARM_BE8(rev r0, r0) ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH DO_SMC set_aux_ctrl: ldr r1, =OMAP44XX_SAR_RAM_BASE ldr r0, [r1, #L2X0_AUXCTRL_OFFSET] +ARM_BE8(rev r0, r0) ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL DO_SMC mov r0, #0x1 -- cgit v1.2.3 From f35c53430b99a268e3c3ebd9d8abd12d3990ab52 Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Thu, 7 Nov 2013 10:32:08 -0800 Subject: ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE If kernel operates in BE mode on device that has LE bootloader/ROM code, we need to switch CPU to operate in BE mode before it will start to access BE data. Generic secondary_startup function that is called from OMAP specific secondary startup code will do the switch, but we need to do it earlier because OMAP's secondary_startup code works with BE data. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- arch/arm/mach-omap2/omap-headsmp.S | 13 +++++++++++++ arch/arm/mach-omap2/sleep44xx.S | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4993d4bfe9b2..998190a7b0f9 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -17,6 +17,7 @@ #include #include +#include #include "omap44xx.h" @@ -57,6 +58,12 @@ hold: ldr r12,=0x103 cmp r0, r4 bne hold + /* + * ROM code operates in little endian mode, when we get control we + * need to switch it back to big endian mode. + */ +ARM_BE8(setend be) + /* * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core @@ -74,6 +81,12 @@ hold_2: ldr r12,=0x103 cmp r0, r4 bne hold_2 + /* + * ROM code operates in little endian mode, when we get control we + * need to switch it back to big endian mode. + */ +ARM_BE8(setend be) + /* * GIC distributor control register has changed between * CortexA9 r1pX and r2pX. The Control Register secure diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 8017016f6953..f509dc580c53 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -259,6 +259,12 @@ ENDPROC(omap4_finish_suspend) * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. */ ENTRY(omap4_cpu_resume) + /* + * ROM code operates in little endian mode, when we get control we + * need to switch it back to big endian mode. + */ +ARM_BE8(setend be) + /* * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA -- cgit v1.2.3 From 9be6cbd771d9d34ba6e9242530dd4dcc3d93338c Mon Sep 17 00:00:00 2001 From: Victor Kamensky Date: Thu, 7 Nov 2013 10:32:09 -0800 Subject: ARM: OMAP4: enable big endian support Previous patches fixed big endian issues in OMAP4 code, so mark it as one that supports big endian Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- arch/arm/mach-omap2/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1c1ed737f7ab..44e8378223af 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -40,6 +40,7 @@ config ARCH_OMAP4 select PM_RUNTIME if CPU_IDLE select ARM_ERRATA_754322 select ARM_ERRATA_775420 + select ARCH_SUPPORTS_BIG_ENDIAN config SOC_OMAP5 bool "TI OMAP5" -- cgit v1.2.3