From 2fde1f1c343030d169945aa67a0e485b568f1393 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:10 +1000 Subject: drm/nouveau/disp: switch to device pri macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c | 12 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c | 233 ++++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c | 3 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c | 15 +- .../gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c | 13 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c | 45 ++-- .../gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c | 29 +-- .../gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c | 31 +-- .../gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c | 45 ++-- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c | 30 +-- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c | 252 +++++++++++---------- .../gpu/drm/nouveau/nvkm/engine/disp/piornv50.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c | 28 ++- .../gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c | 27 ++- .../gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c | 34 +-- drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c | 25 +- 20 files changed, 457 insertions(+), 380 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/disp') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c index f64dec917f85..acc9fbb4ae04 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c @@ -33,6 +33,7 @@ int nv50_dac_power(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 doff = outp->or * 0x800; union { struct nv50_disp_dac_pwr_v0 v0; @@ -54,7 +55,7 @@ nv50_dac_power(NV50_DISP_MTHD_V1) return ret; nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); - nv_mask(disp, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); + nvkm_mask(device, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); return 0; } @@ -62,6 +63,7 @@ nv50_dac_power(NV50_DISP_MTHD_V1) int nv50_dac_sense(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; union { struct nv50_disp_dac_load_v0 v0; } *args = data; @@ -79,15 +81,15 @@ nv50_dac_sense(NV50_DISP_MTHD_V1) } else return ret; - nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80150000); + nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80150000); nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); - nv_wr32(disp, 0x61a00c + doff, 0x00100000 | loadval); + nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval); mdelay(9); udelay(500); - loadval = nv_mask(disp, 0x61a00c + doff, 0xffffffff, 0x00000000); + loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000); - nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80550000); + nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80550000); nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); nv_debug(disp, "DAC%d sense: 0x%08x\n", outp->or, loadval); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c index 3301fedfe768..293b41bd2468 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c @@ -47,16 +47,18 @@ static void gf110_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) { struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); - nv_mask(disp, 0x610090, 0x00000001 << index, 0x00000000 << index); - nv_wr32(disp, 0x61008c, 0x00000001 << index); + struct nvkm_device *device = disp->base.engine.subdev.device; + nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000000 << index); + nvkm_wr32(device, 0x61008c, 0x00000001 << index); } static void gf110_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) { struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); - nv_wr32(disp, 0x61008c, 0x00000001 << index); - nv_mask(disp, 0x610090, 0x00000001 << index, 0x00000001 << index); + struct nvkm_device *device = disp->base.engine.subdev.device; + nvkm_wr32(device, 0x61008c, 0x00000001 << index); + nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000001 << index); } const struct nvkm_event_func @@ -93,6 +95,7 @@ gf110_disp_dmac_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = dmac->base.chid; int ret; @@ -101,20 +104,20 @@ gf110_disp_dmac_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); + nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); /* initialise channel for dma command submission */ - nv_wr32(disp, 0x610494 + (chid * 0x0010), dmac->push); - nv_wr32(disp, 0x610498 + (chid * 0x0010), 0x00010000); - nv_wr32(disp, 0x61049c + (chid * 0x0010), 0x00000001); - nv_mask(disp, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); - nv_wr32(disp, 0x640000 + (chid * 0x1000), 0x00000000); - nv_wr32(disp, 0x610490 + (chid * 0x0010), 0x00000013); + nvkm_wr32(device, 0x610494 + (chid * 0x0010), dmac->push); + nvkm_wr32(device, 0x610498 + (chid * 0x0010), 0x00010000); + nvkm_wr32(device, 0x61049c + (chid * 0x0010), 0x00000001); + nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); + nvkm_wr32(device, 0x640000 + (chid * 0x1000), 0x00000000); + nvkm_wr32(device, 0x610490 + (chid * 0x0010), 0x00000013); /* wait for it to go inactive */ if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) { nv_error(dmac, "init: 0x%08x\n", - nv_rd32(disp, 0x610490 + (chid * 0x10))); + nvkm_rd32(device, 0x610490 + (chid * 0x10))); return -EBUSY; } @@ -126,21 +129,22 @@ gf110_disp_dmac_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = dmac->base.chid; /* deactivate channel */ - nv_mask(disp, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); - nv_mask(disp, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); + nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); + nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) { nv_error(dmac, "fini: 0x%08x\n", - nv_rd32(disp, 0x610490 + (chid * 0x10))); + nvkm_rd32(device, 0x610490 + (chid * 0x10))); if (suspend) return -EBUSY; } /* disable error reporting and completion notification */ - nv_mask(disp, 0x610090, 0x00000001 << chid, 0x00000000); - nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000000); + nvkm_mask(device, 0x610090, 0x00000001 << chid, 0x00000000); + nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000000); return nv50_disp_chan_fini(&dmac->base, suspend); } @@ -294,6 +298,7 @@ gf110_disp_core_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int ret; ret = nv50_disp_chan_init(&mast->base); @@ -301,19 +306,19 @@ gf110_disp_core_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(disp, 0x6100a0, 0x00000001, 0x00000001); + nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000001); /* initialise channel for dma command submission */ - nv_wr32(disp, 0x610494, mast->push); - nv_wr32(disp, 0x610498, 0x00010000); - nv_wr32(disp, 0x61049c, 0x00000001); - nv_mask(disp, 0x610490, 0x00000010, 0x00000010); - nv_wr32(disp, 0x640000, 0x00000000); - nv_wr32(disp, 0x610490, 0x01000013); + nvkm_wr32(device, 0x610494, mast->push); + nvkm_wr32(device, 0x610498, 0x00010000); + nvkm_wr32(device, 0x61049c, 0x00000001); + nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); + nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x610490, 0x01000013); /* wait for it to go inactive */ if (!nv_wait(disp, 0x610490, 0x80000000, 0x00000000)) { - nv_error(mast, "init: 0x%08x\n", nv_rd32(disp, 0x610490)); + nv_error(mast, "init: 0x%08x\n", nvkm_rd32(device, 0x610490)); return -EBUSY; } @@ -325,19 +330,20 @@ gf110_disp_core_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; /* deactivate channel */ - nv_mask(disp, 0x610490, 0x00000010, 0x00000000); - nv_mask(disp, 0x610490, 0x00000003, 0x00000000); + nvkm_mask(device, 0x610490, 0x00000010, 0x00000000); + nvkm_mask(device, 0x610490, 0x00000003, 0x00000000); if (!nv_wait(disp, 0x610490, 0x001e0000, 0x00000000)) { - nv_error(mast, "fini: 0x%08x\n", nv_rd32(disp, 0x610490)); + nv_error(mast, "fini: 0x%08x\n", nvkm_rd32(device, 0x610490)); if (suspend) return -EBUSY; } /* disable error reporting and completion notification */ - nv_mask(disp, 0x610090, 0x00000001, 0x00000000); - nv_mask(disp, 0x6100a0, 0x00000001, 0x00000000); + nvkm_mask(device, 0x610090, 0x00000001, 0x00000000); + nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000000); return nv50_disp_chan_fini(&mast->base, suspend); } @@ -541,6 +547,7 @@ gf110_disp_pioc_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = pioc->base.chid; int ret; @@ -549,13 +556,13 @@ gf110_disp_pioc_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); + nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); /* activate channel */ - nv_wr32(disp, 0x610490 + (chid * 0x10), 0x00000001); + nvkm_wr32(device, 0x610490 + (chid * 0x10), 0x00000001); if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) { nv_error(pioc, "init: 0x%08x\n", - nv_rd32(disp, 0x610490 + (chid * 0x10))); + nvkm_rd32(device, 0x610490 + (chid * 0x10))); return -EBUSY; } @@ -567,19 +574,20 @@ gf110_disp_pioc_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = pioc->base.chid; - nv_mask(disp, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); + nvkm_mask(device, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) { nv_error(pioc, "timeout: 0x%08x\n", - nv_rd32(disp, 0x610490 + (chid * 0x10))); + nvkm_rd32(device, 0x610490 + (chid * 0x10))); if (suspend) return -EBUSY; } /* disable error reporting and completion notification */ - nv_mask(disp, 0x610090, 0x00000001 << chid, 0x00000000); - nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000000); + nvkm_mask(device, 0x610090, 0x00000001 << chid, 0x00000000); + nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000000); return nv50_disp_chan_fini(&pioc->base, suspend); } @@ -625,9 +633,10 @@ gf110_disp_curs_ofuncs = { int gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0) { - const u32 total = nv_rd32(disp, 0x640414 + (head * 0x300)); - const u32 blanke = nv_rd32(disp, 0x64041c + (head * 0x300)); - const u32 blanks = nv_rd32(disp, 0x640420 + (head * 0x300)); + struct nvkm_device *device = disp->base.engine.subdev.device; + const u32 total = nvkm_rd32(device, 0x640414 + (head * 0x300)); + const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300)); + const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300)); union { struct nv04_disp_scanoutpos_v0 v0; } *args = data; @@ -644,10 +653,10 @@ gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0) args->v0.htotal = ( total & 0x0000ffff); args->v0.time[0] = ktime_to_ns(ktime_get()); args->v0.vline = /* vline read locks hline */ - nv_rd32(disp, 0x616340 + (head * 0x800)) & 0xffff; + nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff; args->v0.time[1] = ktime_to_ns(ktime_get()); args->v0.hline = - nv_rd32(disp, 0x616344 + (head * 0x800)) & 0xffff; + nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff; } else return ret; @@ -659,6 +668,7 @@ gf110_disp_main_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int ret, i; u32 tmp; @@ -673,30 +683,30 @@ gf110_disp_main_init(struct nvkm_object *object) /* ... CRTC caps */ for (i = 0; i < disp->head.nr; i++) { - tmp = nv_rd32(disp, 0x616104 + (i * 0x800)); - nv_wr32(disp, 0x6101b4 + (i * 0x800), tmp); - tmp = nv_rd32(disp, 0x616108 + (i * 0x800)); - nv_wr32(disp, 0x6101b8 + (i * 0x800), tmp); - tmp = nv_rd32(disp, 0x61610c + (i * 0x800)); - nv_wr32(disp, 0x6101bc + (i * 0x800), tmp); + tmp = nvkm_rd32(device, 0x616104 + (i * 0x800)); + nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp); + tmp = nvkm_rd32(device, 0x616108 + (i * 0x800)); + nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp); + tmp = nvkm_rd32(device, 0x61610c + (i * 0x800)); + nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp); } /* ... DAC caps */ for (i = 0; i < disp->dac.nr; i++) { - tmp = nv_rd32(disp, 0x61a000 + (i * 0x800)); - nv_wr32(disp, 0x6101c0 + (i * 0x800), tmp); + tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); + nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp); } /* ... SOR caps */ for (i = 0; i < disp->sor.nr; i++) { - tmp = nv_rd32(disp, 0x61c000 + (i * 0x800)); - nv_wr32(disp, 0x6301c4 + (i * 0x800), tmp); + tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); + nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp); } /* steal display away from vbios, or something like that */ - if (nv_rd32(disp, 0x6100ac) & 0x00000100) { - nv_wr32(disp, 0x6100ac, 0x00000100); - nv_mask(disp, 0x6194e8, 0x00000001, 0x00000000); + if (nvkm_rd32(device, 0x6100ac) & 0x00000100) { + nvkm_wr32(device, 0x6100ac, 0x00000100); + nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000); if (!nv_wait(disp, 0x6194e8, 0x00000002, 0x00000000)) { nv_error(disp, "timeout acquiring display\n"); return -EBUSY; @@ -704,12 +714,12 @@ gf110_disp_main_init(struct nvkm_object *object) } /* point at display engine memory area (hash table, objects) */ - nv_wr32(disp, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9); + nvkm_wr32(device, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9); /* enable supervisor interrupts, disable everything else */ - nv_wr32(disp, 0x610090, 0x00000000); - nv_wr32(disp, 0x6100a0, 0x00000000); - nv_wr32(disp, 0x6100b0, 0x00000307); + nvkm_wr32(device, 0x610090, 0x00000000); + nvkm_wr32(device, 0x6100a0, 0x00000000); + nvkm_wr32(device, 0x6100b0, 0x00000307); /* disable underflow reporting, preventing an intermittent issue * on some gk104 boards where the production vbios left this @@ -718,7 +728,7 @@ gf110_disp_main_init(struct nvkm_object *object) * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt */ for (i = 0; i < disp->head.nr; i++) - nv_mask(disp, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); + nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); return 0; } @@ -728,9 +738,10 @@ gf110_disp_main_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; /* disable all interrupts */ - nv_wr32(disp, 0x6100b0, 0x00000000); + nvkm_wr32(device, 0x6100b0, 0x00000000); return nvkm_parent_fini(&base->base, suspend); } @@ -769,14 +780,16 @@ static void gf110_disp_vblank_init(struct nvkm_event *event, int type, int head) { struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); - nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); + struct nvkm_device *device = disp->engine.subdev.device; + nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); } static void gf110_disp_vblank_fini(struct nvkm_event *event, int type, int head) { struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); - nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); + struct nvkm_device *device = disp->engine.subdev.device; + nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); } const struct nvkm_event_func @@ -835,7 +848,8 @@ exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, static struct nvkm_output * exec_script(struct nv50_disp *disp, int head, int id) { - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; struct nvkm_output *outp; struct nvbios_outp info; u8 ver, hdr, cnt, len; @@ -843,7 +857,7 @@ exec_script(struct nv50_disp *disp, int head, int id) int or; for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { - ctrl = nv_rd32(disp, 0x640180 + (or * 0x20)); + ctrl = nvkm_rd32(device, 0x640180 + (or * 0x20)); if (ctrl & (1 << head)) break; } @@ -871,7 +885,8 @@ exec_script(struct nv50_disp *disp, int head, int id) static struct nvkm_output * exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) { - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; struct nvkm_output *outp; struct nvbios_outp info1; struct nvbios_ocfg info2; @@ -880,7 +895,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) int or; for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { - ctrl = nv_rd32(disp, 0x660180 + (or * 0x20)); + ctrl = nvkm_rd32(device, 0x660180 + (or * 0x20)); if (ctrl & (1 << head)) break; } @@ -961,32 +976,34 @@ gf110_disp_intr_unk2_0(struct nv50_disp *disp, int head) static void gf110_disp_intr_unk2_1(struct nv50_disp *disp, int head) { - struct nvkm_devinit *devinit = nvkm_devinit(disp); - u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_devinit *devinit = device->devinit; + u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; if (pclk) devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); - nv_wr32(disp, 0x612200 + (head * 0x800), 0x00000000); + nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000); } static void gf110_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head, struct dcb_output *outp) { + struct nvkm_device *device = disp->base.engine.subdev.device; const int or = ffs(outp->or) - 1; - const u32 ctrl = nv_rd32(disp, 0x660200 + (or * 0x020)); - const u32 conf = nv_rd32(disp, 0x660404 + (head * 0x300)); - const s32 vactive = nv_rd32(disp, 0x660414 + (head * 0x300)) & 0xffff; - const s32 vblanke = nv_rd32(disp, 0x66041c + (head * 0x300)) & 0xffff; - const s32 vblanks = nv_rd32(disp, 0x660420 + (head * 0x300)) & 0xffff; - const u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; + const u32 ctrl = nvkm_rd32(device, 0x660200 + (or * 0x020)); + const u32 conf = nvkm_rd32(device, 0x660404 + (head * 0x300)); + const s32 vactive = nvkm_rd32(device, 0x660414 + (head * 0x300)) & 0xffff; + const s32 vblanke = nvkm_rd32(device, 0x66041c + (head * 0x300)) & 0xffff; + const s32 vblanks = nvkm_rd32(device, 0x660420 + (head * 0x300)) & 0xffff; + const u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1; const u32 hoff = (head * 0x800); const u32 soff = ( or * 0x800); const u32 loff = (link * 0x080) + soff; const u32 symbol = 100000; const u32 TU = 64; - u32 dpctrl = nv_rd32(disp, 0x61c10c + loff); - u32 clksor = nv_rd32(disp, 0x612300 + soff); + u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff); + u32 clksor = nvkm_rd32(device, 0x612300 + soff); u32 datarate, link_nr, link_bw, bits; u64 ratio, value; @@ -999,14 +1016,14 @@ gf110_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head, value = value * link_bw; do_div(value, pclk); value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); - nv_mask(disp, 0x616620 + hoff, 0x0000ffff, value); + nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, value); /* symbols/vblank - algorithm taken from comments in tegra driver */ value = vblanks - vblanke - 25; value = value * link_bw; do_div(value, pclk); value = value - ((36 / link_nr) + 3) - 1; - nv_mask(disp, 0x616624 + hoff, 0x00ffffff, value); + nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, value); /* watermark */ if ((conf & 0x3c0) == 0x180) bits = 30; @@ -1026,14 +1043,15 @@ gf110_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head, value += 5; value |= 0x08000000; - nv_wr32(disp, 0x616610 + hoff, value); + nvkm_wr32(device, 0x616610 + hoff, value); } static void gf110_disp_intr_unk2_2(struct nv50_disp *disp, int head) { + struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_output *outp; - u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; + u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; u32 conf, addr, data; outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); @@ -1042,7 +1060,7 @@ gf110_disp_intr_unk2_2(struct nv50_disp *disp, int head) /* see note in nv50_disp_intr_unk20_2() */ if (outp->info.type == DCB_OUTPUT_DP) { - u32 sync = nv_rd32(disp, 0x660404 + (head * 0x300)); + u32 sync = nvkm_rd32(device, 0x660404 + (head * 0x300)); switch ((sync & 0x000003c0) >> 6) { case 6: pclk = pclk * 30; break; case 5: pclk = pclk * 24; break; @@ -1069,7 +1087,7 @@ gf110_disp_intr_unk2_2(struct nv50_disp *disp, int head) data = (conf & 0x0100) ? 0x00000101 : 0x00000000; switch (outp->info.type) { case DCB_OUTPUT_TMDS: - nv_mask(disp, addr, 0x007c0000, 0x00280000); + nvkm_mask(device, addr, 0x007c0000, 0x00280000); break; case DCB_OUTPUT_DP: gf110_disp_intr_unk2_2_tu(disp, head, &outp->info); @@ -1079,13 +1097,14 @@ gf110_disp_intr_unk2_2(struct nv50_disp *disp, int head) } } - nv_mask(disp, addr, 0x00000707, data); + nvkm_mask(device, addr, 0x00000707, data); } static void gf110_disp_intr_unk4_0(struct nv50_disp *disp, int head) { - u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; + struct nvkm_device *device = disp->base.engine.subdev.device; + u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; u32 conf; exec_clkcmp(disp, head, 1, pclk, &conf); @@ -1097,12 +1116,13 @@ gf110_disp_intr_supervisor(struct work_struct *work) struct nv50_disp *disp = container_of(work, struct nv50_disp, supervisor); struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; + struct nvkm_device *device = disp->base.engine.subdev.device; u32 mask[4]; int head; nv_debug(disp, "supervisor %d\n", ffs(disp->super)); for (head = 0; head < disp->head.nr; head++) { - mask[head] = nv_rd32(disp, 0x6101d4 + (head * 0x800)); + mask[head] = nvkm_rd32(device, 0x6101d4 + (head * 0x800)); nv_debug(disp, "head %d: 0x%08x\n", head, mask[head]); } @@ -1145,17 +1165,18 @@ gf110_disp_intr_supervisor(struct work_struct *work) } for (head = 0; head < disp->head.nr; head++) - nv_wr32(disp, 0x6101d4 + (head * 0x800), 0x00000000); - nv_wr32(disp, 0x6101d0, 0x80000000); + nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000); + nvkm_wr32(device, 0x6101d0, 0x80000000); } static void gf110_disp_intr_error(struct nv50_disp *disp, int chid) { const struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; - u32 mthd = nv_rd32(disp, 0x6101f0 + (chid * 12)); - u32 data = nv_rd32(disp, 0x6101f4 + (chid * 12)); - u32 unkn = nv_rd32(disp, 0x6101f8 + (chid * 12)); + struct nvkm_device *device = disp->base.engine.subdev.device; + u32 mthd = nvkm_rd32(device, 0x6101f0 + (chid * 12)); + u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12)); + u32 unkn = nvkm_rd32(device, 0x6101f8 + (chid * 12)); nv_error(disp, "chid %d mthd 0x%04x data 0x%08x " "0x%08x 0x%08x\n", @@ -1192,29 +1213,30 @@ gf110_disp_intr_error(struct nv50_disp *disp, int chid) } } - nv_wr32(disp, 0x61009c, (1 << chid)); - nv_wr32(disp, 0x6101f0 + (chid * 12), 0x90000000); + nvkm_wr32(device, 0x61009c, (1 << chid)); + nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000); } void gf110_disp_intr(struct nvkm_subdev *subdev) { struct nv50_disp *disp = (void *)subdev; - u32 intr = nv_rd32(disp, 0x610088); + struct nvkm_device *device = disp->base.engine.subdev.device; + u32 intr = nvkm_rd32(device, 0x610088); int i; if (intr & 0x00000001) { - u32 stat = nv_rd32(disp, 0x61008c); + u32 stat = nvkm_rd32(device, 0x61008c); while (stat) { int chid = __ffs(stat); stat &= ~(1 << chid); nv50_disp_chan_uevent_send(disp, chid); - nv_wr32(disp, 0x61008c, 1 << chid); + nvkm_wr32(device, 0x61008c, 1 << chid); } intr &= ~0x00000001; } if (intr & 0x00000002) { - u32 stat = nv_rd32(disp, 0x61009c); + u32 stat = nvkm_rd32(device, 0x61009c); int chid = ffs(stat) - 1; if (chid >= 0) gf110_disp_intr_error(disp, chid); @@ -1222,17 +1244,17 @@ gf110_disp_intr(struct nvkm_subdev *subdev) } if (intr & 0x00100000) { - u32 stat = nv_rd32(disp, 0x6100ac); + u32 stat = nvkm_rd32(device, 0x6100ac); if (stat & 0x00000007) { disp->super = (stat & 0x00000007); schedule_work(&disp->supervisor); - nv_wr32(disp, 0x6100ac, disp->super); + nvkm_wr32(device, 0x6100ac, disp->super); stat &= ~0x00000007; } if (stat) { nv_info(disp, "unknown intr24 0x%08x\n", stat); - nv_wr32(disp, 0x6100ac, stat); + nvkm_wr32(device, 0x6100ac, stat); } intr &= ~0x00100000; @@ -1241,11 +1263,11 @@ gf110_disp_intr(struct nvkm_subdev *subdev) for (i = 0; i < disp->head.nr; i++) { u32 mask = 0x01000000 << i; if (mask & intr) { - u32 stat = nv_rd32(disp, 0x6100bc + (i * 0x800)); + u32 stat = nvkm_rd32(device, 0x6100bc + (i * 0x800)); if (stat & 0x00000001) nvkm_disp_vblank(&disp->base, i); - nv_mask(disp, 0x6100bc + (i * 0x800), 0, 0); - nv_rd32(disp, 0x6100c0 + (i * 0x800)); + nvkm_mask(device, 0x6100bc + (i * 0x800), 0, 0); + nvkm_rd32(device, 0x6100c0 + (i * 0x800)); } } } @@ -1255,8 +1277,9 @@ gf110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv50_disp *disp; - int heads = nv_rd32(parent, 0x022448); + int heads = nvkm_rd32(device, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c index ccb5bfad9ec8..baf2c2832c40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c @@ -219,8 +219,9 @@ gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv50_disp *disp; - int heads = nv_rd32(parent, 0x022448); + int heads = nvkm_rd32(device, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c index f4372fb38246..ee51b4f22aaa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c @@ -54,8 +54,9 @@ gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv50_disp *disp; - int heads = nv_rd32(parent, 0x022448); + int heads = nvkm_rd32(device, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c index 558c38736f55..13a02ac2ffa7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c @@ -54,8 +54,9 @@ gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv50_disp *disp; - int heads = nv_rd32(parent, 0x022448); + int heads = nvkm_rd32(device, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c index a56ef7bd6623..89d9839ecf65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c @@ -55,8 +55,9 @@ gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv50_disp *disp; - int heads = nv_rd32(parent, 0x022448); + int heads = nvkm_rd32(device, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c index fe07d7cb4dd7..a04ef426840d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c @@ -35,6 +35,7 @@ int gf110_hda_eld(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; union { struct nv50_disp_sor_hda_eld_v0 v0; } *args = data; @@ -52,21 +53,21 @@ gf110_hda_eld(NV50_DISP_MTHD_V1) if (size && args->v0.data[0]) { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(disp, 0x616618 + hoff, 0x8000000c, 0x80000001); + nvkm_mask(device, 0x616618 + hoff, 0x8000000c, 0x80000001); nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000); } - nv_mask(disp, 0x616548 + hoff, 0x00000070, 0x00000000); + nvkm_mask(device, 0x616548 + hoff, 0x00000070, 0x00000000); for (i = 0; i < size; i++) - nv_wr32(disp, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); + nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); for (; i < 0x60; i++) - nv_wr32(disp, 0x10ec00 + soff, (i << 8)); - nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000003); + nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); + nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000003); } else { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(disp, 0x616618 + hoff, 0x80000001, 0x80000000); + nvkm_mask(device, 0x616618 + hoff, 0x80000001, 0x80000000); nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000); } - nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); + nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); } return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c index 67d3cf99e0b5..c2ae112225fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c @@ -33,6 +33,7 @@ int gt215_hda_eld(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; union { struct nv50_disp_sor_hda_eld_v0 v0; } *args = data; @@ -49,20 +50,20 @@ gt215_hda_eld(NV50_DISP_MTHD_V1) if (size && args->v0.data[0]) { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(disp, 0x61c1e0 + soff, 0x8000000d, 0x80000001); + nvkm_mask(device, 0x61c1e0 + soff, 0x8000000d, 0x80000001); nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000); } for (i = 0; i < size; i++) - nv_wr32(disp, 0x61c440 + soff, (i << 8) | args->v0.data[0]); + nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[0]); for (; i < 0x60; i++) - nv_wr32(disp, 0x61c440 + soff, (i << 8)); - nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000003); + nvkm_wr32(device, 0x61c440 + soff, (i << 8)); + nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000003); } else { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(disp, 0x61c1e0 + soff, 0x80000001, 0x80000000); + nvkm_mask(device, 0x61c1e0 + soff, 0x80000001, 0x80000000); nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000); } - nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); + nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); } return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c index 0c282a4d31a8..da7f001f918c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c @@ -31,6 +31,7 @@ int g84_hdmi_ctrl(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 hoff = (head * 0x800); union { struct nv50_disp_sor_hdmi_pwr_v0 v0; @@ -54,38 +55,38 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(disp, 0x6165a4 + hoff, 0x40000000, 0x00000000); - nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000); - nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); + nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000); - nv_wr32(disp, 0x616528 + hoff, 0x000d0282); - nv_wr32(disp, 0x61652c + hoff, 0x0000006f); - nv_wr32(disp, 0x616530 + hoff, 0x00000000); - nv_wr32(disp, 0x616534 + hoff, 0x00000000); - nv_wr32(disp, 0x616538 + hoff, 0x00000000); - nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000001); + nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x616528 + hoff, 0x000d0282); + nvkm_wr32(device, 0x61652c + hoff, 0x0000006f); + nvkm_wr32(device, 0x616530 + hoff, 0x00000000); + nvkm_wr32(device, 0x616534 + hoff, 0x00000000); + nvkm_wr32(device, 0x616538 + hoff, 0x00000000); + nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001); /* Audio InfoFrame */ - nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000); - nv_wr32(disp, 0x616508 + hoff, 0x000a0184); - nv_wr32(disp, 0x61650c + hoff, 0x00000071); - nv_wr32(disp, 0x616510 + hoff, 0x00000000); - nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000001); + nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x616508 + hoff, 0x000a0184); + nvkm_wr32(device, 0x61650c + hoff, 0x00000071); + nvkm_wr32(device, 0x616510 + hoff, 0x00000000); + nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001); - nv_mask(disp, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ - nv_mask(disp, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ - nv_mask(disp, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ + nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ /* ??? */ - nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ - nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ - nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ + nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ + nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ + nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ /* HDMI_CTRL */ - nv_mask(disp, 0x6165a4 + hoff, 0x5f1f007f, ctrl); + nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c index 5dcbc8e50d81..1a474be0504b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c @@ -31,6 +31,7 @@ int gf110_hdmi_ctrl(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 hoff = (head * 0x800); union { struct nv50_disp_sor_hdmi_pwr_v0 v0; @@ -53,27 +54,27 @@ gf110_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000); - nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000); - nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); + nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000); - nv_wr32(disp, 0x61671c + hoff, 0x000d0282); - nv_wr32(disp, 0x616720 + hoff, 0x0000006f); - nv_wr32(disp, 0x616724 + hoff, 0x00000000); - nv_wr32(disp, 0x616728 + hoff, 0x00000000); - nv_wr32(disp, 0x61672c + hoff, 0x00000000); - nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000001); + nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x61671c + hoff, 0x000d0282); + nvkm_wr32(device, 0x616720 + hoff, 0x0000006f); + nvkm_wr32(device, 0x616724 + hoff, 0x00000000); + nvkm_wr32(device, 0x616728 + hoff, 0x00000000); + nvkm_wr32(device, 0x61672c + hoff, 0x00000000); + nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000001); /* ??? InfoFrame? */ - nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000); - nv_wr32(disp, 0x6167ac + hoff, 0x00000010); - nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000001); + nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x6167ac + hoff, 0x00000010); + nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000001); /* HDMI_CTRL */ - nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl); + nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c index 719d21e85301..b1a69bd93d96 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c @@ -31,6 +31,7 @@ int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 hoff = (head * 0x800); const u32 hdmi = (head * 0x400); union { @@ -54,30 +55,30 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000); - nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000); - nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000); + nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000); + nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); + nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000); - nv_wr32(disp, 0x690008 + hdmi, 0x000d0282); - nv_wr32(disp, 0x69000c + hdmi, 0x0000006f); - nv_wr32(disp, 0x690010 + hdmi, 0x00000000); - nv_wr32(disp, 0x690014 + hdmi, 0x00000000); - nv_wr32(disp, 0x690018 + hdmi, 0x00000000); - nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000001); + nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x690008 + hdmi, 0x000d0282); + nvkm_wr32(device, 0x69000c + hdmi, 0x0000006f); + nvkm_wr32(device, 0x690010 + hdmi, 0x00000000); + nvkm_wr32(device, 0x690014 + hdmi, 0x00000000); + nvkm_wr32(device, 0x690018 + hdmi, 0x00000000); + nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000001); /* ??? InfoFrame? */ - nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000); - nv_wr32(disp, 0x6900cc + hdmi, 0x00000010); - nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000001); + nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x6900cc + hdmi, 0x00000010); + nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000001); /* ??? */ - nv_wr32(disp, 0x690080 + hdmi, 0x82000000); + nvkm_wr32(device, 0x690080 + hdmi, 0x82000000); /* HDMI_CTRL */ - nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl); + nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c index dde989158153..353dde956fd1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c @@ -32,6 +32,7 @@ int gt215_hdmi_ctrl(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = outp->or * 0x800; union { struct nv50_disp_sor_hdmi_pwr_v0 v0; @@ -55,38 +56,38 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(disp, 0x61c5a4 + soff, 0x40000000, 0x00000000); - nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000); - nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000); + nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000); - nv_wr32(disp, 0x61c528 + soff, 0x000d0282); - nv_wr32(disp, 0x61c52c + soff, 0x0000006f); - nv_wr32(disp, 0x61c530 + soff, 0x00000000); - nv_wr32(disp, 0x61c534 + soff, 0x00000000); - nv_wr32(disp, 0x61c538 + soff, 0x00000000); - nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000001); + nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x61c528 + soff, 0x000d0282); + nvkm_wr32(device, 0x61c52c + soff, 0x0000006f); + nvkm_wr32(device, 0x61c530 + soff, 0x00000000); + nvkm_wr32(device, 0x61c534 + soff, 0x00000000); + nvkm_wr32(device, 0x61c538 + soff, 0x00000000); + nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001); /* Audio InfoFrame */ - nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000); - nv_wr32(disp, 0x61c508 + soff, 0x000a0184); - nv_wr32(disp, 0x61c50c + soff, 0x00000071); - nv_wr32(disp, 0x61c510 + soff, 0x00000000); - nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000001); + nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000); + nvkm_wr32(device, 0x61c508 + soff, 0x000a0184); + nvkm_wr32(device, 0x61c50c + soff, 0x00000071); + nvkm_wr32(device, 0x61c510 + soff, 0x00000000); + nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001); - nv_mask(disp, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ - nv_mask(disp, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ - nv_mask(disp, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ + nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ /* ??? */ - nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ - nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ - nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ + nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ + nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ + nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ /* HDMI_CTRL */ - nv_mask(disp, 0x61c5a4 + soff, 0x5f1f007f, ctrl); + nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index 81359d25afce..859c06ee6fc2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -32,6 +32,7 @@ static int nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp, void *data, u32 size, int head) { + struct nvkm_device *device = disp->engine.subdev.device; const u32 hoff = head * 0x2000; union { struct nv04_disp_scanoutpos_v0 v0; @@ -42,12 +43,12 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp, nv_ioctl(object, "disp scanoutpos size %d\n", size); if (nvif_unpack(args->v0, 0, 0, false)) { nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); - args->v0.vblanks = nv_rd32(disp, 0x680800 + hoff) & 0xffff; - args->v0.vtotal = nv_rd32(disp, 0x680804 + hoff) & 0xffff; + args->v0.vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0xffff; + args->v0.vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0xffff; args->v0.vblanke = args->v0.vtotal - 1; - args->v0.hblanks = nv_rd32(disp, 0x680820 + hoff) & 0xffff; - args->v0.htotal = nv_rd32(disp, 0x680824 + hoff) & 0xffff; + args->v0.hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0xffff; + args->v0.htotal = nvkm_rd32(device, 0x680824 + hoff) & 0xffff; args->v0.hblanke = args->v0.htotal - 1; /* @@ -59,7 +60,7 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp, return -ENOTSUPP; args->v0.time[0] = ktime_to_ns(ktime_get()); - line = nv_rd32(disp, 0x600868 + hoff); + line = nvkm_rd32(device, 0x600868 + hoff); args->v0.time[1] = ktime_to_ns(ktime_get()); args->v0.hline = (line & 0xffff0000) >> 16; args->v0.vline = (line & 0x0000ffff); @@ -124,14 +125,16 @@ static void nv04_disp_vblank_init(struct nvkm_event *event, int type, int head) { struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); - nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001); + struct nvkm_device *device = disp->engine.subdev.device; + nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000001); } static void nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head) { struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); - nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000); + struct nvkm_device *device = disp->engine.subdev.device; + nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000000); } static const struct nvkm_event_func @@ -145,26 +148,27 @@ static void nv04_disp_intr(struct nvkm_subdev *subdev) { struct nvkm_disp *disp = (void *)subdev; - u32 crtc0 = nv_rd32(disp, 0x600100); - u32 crtc1 = nv_rd32(disp, 0x602100); + struct nvkm_device *device = disp->engine.subdev.device; + u32 crtc0 = nvkm_rd32(device, 0x600100); + u32 crtc1 = nvkm_rd32(device, 0x602100); u32 pvideo; if (crtc0 & 0x00000001) { nvkm_disp_vblank(disp, 0); - nv_wr32(disp, 0x600100, 0x00000001); + nvkm_wr32(device, 0x600100, 0x00000001); } if (crtc1 & 0x00000001) { nvkm_disp_vblank(disp, 1); - nv_wr32(disp, 0x602100, 0x00000001); + nvkm_wr32(device, 0x602100, 0x00000001); } if (nv_device(disp)->chipset >= 0x10 && nv_device(disp)->chipset <= 0x40) { - pvideo = nv_rd32(disp, 0x8100); + pvideo = nvkm_rd32(device, 0x8100); if (pvideo & ~0x11) nv_info(disp, "PVIDEO intr: %08x\n", pvideo); - nv_wr32(disp, 0x8100, pvideo); + nvkm_wr32(device, 0x8100, pvideo); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index 9551cfe5622a..a57b7d0c4445 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -89,16 +89,18 @@ static void nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) { struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); - nv_mask(disp, 0x610028, 0x00000001 << index, 0x00000000 << index); - nv_wr32(disp, 0x610020, 0x00000001 << index); + struct nvkm_device *device = disp->base.engine.subdev.device; + nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000000 << index); + nvkm_wr32(device, 0x610020, 0x00000001 << index); } static void nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) { struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); - nv_wr32(disp, 0x610020, 0x00000001 << index); - nv_mask(disp, 0x610028, 0x00000001 << index, 0x00000001 << index); + struct nvkm_device *device = disp->base.engine.subdev.device; + nvkm_wr32(device, 0x610020, 0x00000001 << index); + nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000001 << index); } void @@ -165,17 +167,17 @@ nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size) u32 nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr) { - struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_chan *chan = (void *)object; - return nv_rd32(disp, 0x640000 + (chan->chid * 0x1000) + addr); + struct nvkm_device *device = object->engine->subdev.device; + return nvkm_rd32(device, 0x640000 + (chan->chid * 0x1000) + addr); } void nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_chan *chan = (void *)object; - nv_wr32(disp, 0x640000 + (chan->chid * 0x1000) + addr, data); + struct nvkm_device *device = object->engine->subdev.device; + nvkm_wr32(device, 0x640000 + (chan->chid * 0x1000) + addr, data); } /******************************************************************************* @@ -257,6 +259,7 @@ nv50_disp_dmac_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = dmac->base.chid; int ret; @@ -265,20 +268,20 @@ nv50_disp_dmac_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(disp, 0x610028, 0x00010000 << chid, 0x00010000 << chid); + nvkm_mask(device, 0x610028, 0x00010000 << chid, 0x00010000 << chid); /* initialise channel for dma command submission */ - nv_wr32(disp, 0x610204 + (chid * 0x0010), dmac->push); - nv_wr32(disp, 0x610208 + (chid * 0x0010), 0x00010000); - nv_wr32(disp, 0x61020c + (chid * 0x0010), chid); - nv_mask(disp, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); - nv_wr32(disp, 0x640000 + (chid * 0x1000), 0x00000000); - nv_wr32(disp, 0x610200 + (chid * 0x0010), 0x00000013); + nvkm_wr32(device, 0x610204 + (chid * 0x0010), dmac->push); + nvkm_wr32(device, 0x610208 + (chid * 0x0010), 0x00010000); + nvkm_wr32(device, 0x61020c + (chid * 0x0010), chid); + nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); + nvkm_wr32(device, 0x640000 + (chid * 0x1000), 0x00000000); + nvkm_wr32(device, 0x610200 + (chid * 0x0010), 0x00000013); /* wait for it to go inactive */ if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { nv_error(dmac, "init timeout, 0x%08x\n", - nv_rd32(disp, 0x610200 + (chid * 0x10))); + nvkm_rd32(device, 0x610200 + (chid * 0x10))); return -EBUSY; } @@ -290,20 +293,21 @@ nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = dmac->base.chid; /* deactivate channel */ - nv_mask(disp, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); - nv_mask(disp, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); + nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); + nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { nv_error(dmac, "fini timeout, 0x%08x\n", - nv_rd32(disp, 0x610200 + (chid * 0x10))); + nvkm_rd32(device, 0x610200 + (chid * 0x10))); if (suspend) return -EBUSY; } /* disable error reporting and completion notifications */ - nv_mask(disp, 0x610028, 0x00010001 << chid, 0x00000000 << chid); + nvkm_mask(device, 0x610028, 0x00010001 << chid, 0x00000000 << chid); return nv50_disp_chan_fini(&dmac->base, suspend); } @@ -316,13 +320,14 @@ static void nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c, const struct nv50_disp_mthd_list *list, int inst) { + struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_object *object = nv_object(disp); int i; for (i = 0; list->data[i].mthd; i++) { if (list->data[i].addr) { - u32 next = nv_rd32(disp, list->data[i].addr + base + 0); - u32 prev = nv_rd32(disp, list->data[i].addr + base + c); + u32 next = nvkm_rd32(device, list->data[i].addr + base + 0); + u32 prev = nvkm_rd32(device, list->data[i].addr + base + c); u32 mthd = list->data[i].mthd + (list->mthd * inst); const char *name = list->data[i].name; char mods[16]; @@ -517,6 +522,7 @@ nv50_disp_core_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int ret; ret = nv50_disp_chan_init(&mast->base); @@ -524,25 +530,25 @@ nv50_disp_core_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(disp, 0x610028, 0x00010000, 0x00010000); + nvkm_mask(device, 0x610028, 0x00010000, 0x00010000); /* attempt to unstick channel from some unknown state */ - if ((nv_rd32(disp, 0x610200) & 0x009f0000) == 0x00020000) - nv_mask(disp, 0x610200, 0x00800000, 0x00800000); - if ((nv_rd32(disp, 0x610200) & 0x003f0000) == 0x00030000) - nv_mask(disp, 0x610200, 0x00600000, 0x00600000); + if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000) + nvkm_mask(device, 0x610200, 0x00800000, 0x00800000); + if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000) + nvkm_mask(device, 0x610200, 0x00600000, 0x00600000); /* initialise channel for dma command submission */ - nv_wr32(disp, 0x610204, mast->push); - nv_wr32(disp, 0x610208, 0x00010000); - nv_wr32(disp, 0x61020c, 0x00000000); - nv_mask(disp, 0x610200, 0x00000010, 0x00000010); - nv_wr32(disp, 0x640000, 0x00000000); - nv_wr32(disp, 0x610200, 0x01000013); + nvkm_wr32(device, 0x610204, mast->push); + nvkm_wr32(device, 0x610208, 0x00010000); + nvkm_wr32(device, 0x61020c, 0x00000000); + nvkm_mask(device, 0x610200, 0x00000010, 0x00000010); + nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x610200, 0x01000013); /* wait for it to go inactive */ if (!nv_wait(disp, 0x610200, 0x80000000, 0x00000000)) { - nv_error(mast, "init: 0x%08x\n", nv_rd32(disp, 0x610200)); + nv_error(mast, "init: 0x%08x\n", nvkm_rd32(device, 0x610200)); return -EBUSY; } @@ -554,18 +560,19 @@ nv50_disp_core_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; /* deactivate channel */ - nv_mask(disp, 0x610200, 0x00000010, 0x00000000); - nv_mask(disp, 0x610200, 0x00000003, 0x00000000); + nvkm_mask(device, 0x610200, 0x00000010, 0x00000000); + nvkm_mask(device, 0x610200, 0x00000003, 0x00000000); if (!nv_wait(disp, 0x610200, 0x001e0000, 0x00000000)) { - nv_error(mast, "fini: 0x%08x\n", nv_rd32(disp, 0x610200)); + nv_error(mast, "fini: 0x%08x\n", nvkm_rd32(device, 0x610200)); if (suspend) return -EBUSY; } /* disable error reporting and completion notifications */ - nv_mask(disp, 0x610028, 0x00010001, 0x00000000); + nvkm_mask(device, 0x610028, 0x00010001, 0x00000000); return nv50_disp_chan_fini(&mast->base, suspend); } @@ -803,6 +810,7 @@ nv50_disp_pioc_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = pioc->base.chid; int ret; @@ -810,17 +818,17 @@ nv50_disp_pioc_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(disp, 0x610200 + (chid * 0x10), 0x00002000); + nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00002000); if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { nv_error(pioc, "timeout0: 0x%08x\n", - nv_rd32(disp, 0x610200 + (chid * 0x10))); + nvkm_rd32(device, 0x610200 + (chid * 0x10))); return -EBUSY; } - nv_wr32(disp, 0x610200 + (chid * 0x10), 0x00000001); + nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00000001); if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { nv_error(pioc, "timeout1: 0x%08x\n", - nv_rd32(disp, 0x610200 + (chid * 0x10))); + nvkm_rd32(device, 0x610200 + (chid * 0x10))); return -EBUSY; } @@ -832,12 +840,13 @@ nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int chid = pioc->base.chid; - nv_mask(disp, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); + nvkm_mask(device, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { nv_error(pioc, "timeout: 0x%08x\n", - nv_rd32(disp, 0x610200 + (chid * 0x10))); + nvkm_rd32(device, 0x610200 + (chid * 0x10))); if (suspend) return -EBUSY; } @@ -948,9 +957,10 @@ nv50_disp_curs_ofuncs = { int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0) { - const u32 blanke = nv_rd32(disp, 0x610aec + (head * 0x540)); - const u32 blanks = nv_rd32(disp, 0x610af4 + (head * 0x540)); - const u32 total = nv_rd32(disp, 0x610afc + (head * 0x540)); + struct nvkm_device *device = disp->base.engine.subdev.device; + const u32 blanke = nvkm_rd32(device, 0x610aec + (head * 0x540)); + const u32 blanks = nvkm_rd32(device, 0x610af4 + (head * 0x540)); + const u32 total = nvkm_rd32(device, 0x610afc + (head * 0x540)); union { struct nv04_disp_scanoutpos_v0 v0; } *args = data; @@ -967,10 +977,10 @@ nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0) args->v0.htotal = ( total & 0x0000ffff); args->v0.time[0] = ktime_to_ns(ktime_get()); args->v0.vline = /* vline read locks hline */ - nv_rd32(disp, 0x616340 + (head * 0x800)) & 0xffff; + nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff; args->v0.time[1] = ktime_to_ns(ktime_get()); args->v0.hline = - nv_rd32(disp, 0x616344 + (head * 0x800)) & 0xffff; + nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff; } else return ret; @@ -1133,6 +1143,7 @@ nv50_disp_main_init(struct nvkm_object *object) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; int ret, i; u32 tmp; @@ -1144,43 +1155,43 @@ nv50_disp_main_init(struct nvkm_object *object) * another appear to inform EVO of the display capabilities or * something similar. NFI what the 0x614004 caps are for.. */ - tmp = nv_rd32(disp, 0x614004); - nv_wr32(disp, 0x610184, tmp); + tmp = nvkm_rd32(device, 0x614004); + nvkm_wr32(device, 0x610184, tmp); /* ... CRTC caps */ for (i = 0; i < disp->head.nr; i++) { - tmp = nv_rd32(disp, 0x616100 + (i * 0x800)); - nv_wr32(disp, 0x610190 + (i * 0x10), tmp); - tmp = nv_rd32(disp, 0x616104 + (i * 0x800)); - nv_wr32(disp, 0x610194 + (i * 0x10), tmp); - tmp = nv_rd32(disp, 0x616108 + (i * 0x800)); - nv_wr32(disp, 0x610198 + (i * 0x10), tmp); - tmp = nv_rd32(disp, 0x61610c + (i * 0x800)); - nv_wr32(disp, 0x61019c + (i * 0x10), tmp); + tmp = nvkm_rd32(device, 0x616100 + (i * 0x800)); + nvkm_wr32(device, 0x610190 + (i * 0x10), tmp); + tmp = nvkm_rd32(device, 0x616104 + (i * 0x800)); + nvkm_wr32(device, 0x610194 + (i * 0x10), tmp); + tmp = nvkm_rd32(device, 0x616108 + (i * 0x800)); + nvkm_wr32(device, 0x610198 + (i * 0x10), tmp); + tmp = nvkm_rd32(device, 0x61610c + (i * 0x800)); + nvkm_wr32(device, 0x61019c + (i * 0x10), tmp); } /* ... DAC caps */ for (i = 0; i < disp->dac.nr; i++) { - tmp = nv_rd32(disp, 0x61a000 + (i * 0x800)); - nv_wr32(disp, 0x6101d0 + (i * 0x04), tmp); + tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); + nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp); } /* ... SOR caps */ for (i = 0; i < disp->sor.nr; i++) { - tmp = nv_rd32(disp, 0x61c000 + (i * 0x800)); - nv_wr32(disp, 0x6101e0 + (i * 0x04), tmp); + tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); + nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp); } /* ... PIOR caps */ for (i = 0; i < disp->pior.nr; i++) { - tmp = nv_rd32(disp, 0x61e000 + (i * 0x800)); - nv_wr32(disp, 0x6101f0 + (i * 0x04), tmp); + tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800)); + nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp); } /* steal display away from vbios, or something like that */ - if (nv_rd32(disp, 0x610024) & 0x00000100) { - nv_wr32(disp, 0x610024, 0x00000100); - nv_mask(disp, 0x6194e8, 0x00000001, 0x00000000); + if (nvkm_rd32(device, 0x610024) & 0x00000100) { + nvkm_wr32(device, 0x610024, 0x00000100); + nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000); if (!nv_wait(disp, 0x6194e8, 0x00000002, 0x00000000)) { nv_error(disp, "timeout acquiring display\n"); return -EBUSY; @@ -1188,11 +1199,11 @@ nv50_disp_main_init(struct nvkm_object *object) } /* point at display engine memory area (hash table, objects) */ - nv_wr32(disp, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); + nvkm_wr32(device, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); /* enable supervisor interrupts, disable everything else */ - nv_wr32(disp, 0x61002c, 0x00000370); - nv_wr32(disp, 0x610028, 0x00000000); + nvkm_wr32(device, 0x61002c, 0x00000370); + nvkm_wr32(device, 0x610028, 0x00000000); return 0; } @@ -1201,10 +1212,11 @@ nv50_disp_main_fini(struct nvkm_object *object, bool suspend) { struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; + struct nvkm_device *device = disp->base.engine.subdev.device; /* disable all interrupts */ - nv_wr32(disp, 0x610024, 0x00000000); - nv_wr32(disp, 0x610020, 0x00000000); + nvkm_wr32(device, 0x610024, 0x00000000); + nvkm_wr32(device, 0x610020, 0x00000000); return nvkm_parent_fini(&base->base, suspend); } @@ -1289,14 +1301,16 @@ static void nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head) { struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); - nv_mask(disp, 0x61002c, (4 << head), 0); + struct nvkm_device *device = disp->engine.subdev.device; + nvkm_mask(device, 0x61002c, (4 << head), 0); } static void nv50_disp_vblank_init(struct nvkm_event *event, int type, int head) { struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); - nv_mask(disp, 0x61002c, (4 << head), (4 << head)); + struct nvkm_device *device = disp->engine.subdev.device; + nvkm_mask(device, 0x61002c, (4 << head), (4 << head)); } const struct nvkm_event_func @@ -1325,8 +1339,9 @@ static void nv50_disp_intr_error(struct nv50_disp *disp, int chid) { struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; - u32 data = nv_rd32(disp, 0x610084 + (chid * 0x08)); - u32 addr = nv_rd32(disp, 0x610080 + (chid * 0x08)); + struct nvkm_device *device = disp->base.engine.subdev.device; + u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08)); + u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08)); u32 code = (addr & 0x00ff0000) >> 16; u32 type = (addr & 0x00007000) >> 12; u32 mthd = (addr & 0x00000ffc); @@ -1376,8 +1391,8 @@ nv50_disp_intr_error(struct nv50_disp *disp, int chid) } } - nv_wr32(disp, 0x610020, 0x00010000 << chid); - nv_wr32(disp, 0x610080 + (chid * 0x08), 0x90000000); + nvkm_wr32(device, 0x610020, 0x00010000 << chid); + nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000); } static struct nvkm_output * @@ -1440,7 +1455,8 @@ exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, static struct nvkm_output * exec_script(struct nv50_disp *disp, int head, int id) { - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; struct nvkm_output *outp; struct nvbios_outp info; u8 ver, hdr, cnt, len; @@ -1450,7 +1466,7 @@ exec_script(struct nv50_disp *disp, int head, int id) /* DAC */ for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++) - ctrl = nv_rd32(disp, 0x610b5c + (i * 8)); + ctrl = nvkm_rd32(device, 0x610b5c + (i * 8)); /* SOR */ if (!(ctrl & (1 << head))) { @@ -1462,14 +1478,14 @@ exec_script(struct nv50_disp *disp, int head, int id) reg = 0x610798; } for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++) - ctrl = nv_rd32(disp, reg + (i * 8)); + ctrl = nvkm_rd32(device, reg + (i * 8)); i += 4; } /* PIOR */ if (!(ctrl & (1 << head))) { for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++) - ctrl = nv_rd32(disp, 0x610b84 + (i * 8)); + ctrl = nvkm_rd32(device, 0x610b84 + (i * 8)); i += 8; } @@ -1497,7 +1513,8 @@ exec_script(struct nv50_disp *disp, int head, int id) static struct nvkm_output * exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) { - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; struct nvkm_output *outp; struct nvbios_outp info1; struct nvbios_ocfg info2; @@ -1508,7 +1525,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) /* DAC */ for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++) - ctrl = nv_rd32(disp, 0x610b58 + (i * 8)); + ctrl = nvkm_rd32(device, 0x610b58 + (i * 8)); /* SOR */ if (!(ctrl & (1 << head))) { @@ -1520,14 +1537,14 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) reg = 0x610794; } for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++) - ctrl = nv_rd32(disp, reg + (i * 8)); + ctrl = nvkm_rd32(device, reg + (i * 8)); i += 4; } /* PIOR */ if (!(ctrl & (1 << head))) { for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++) - ctrl = nv_rd32(disp, 0x610b80 + (i * 8)); + ctrl = nvkm_rd32(device, 0x610b80 + (i * 8)); i += 8; } @@ -1625,8 +1642,9 @@ nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head) static void nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head) { - struct nvkm_devinit *devinit = nvkm_devinit(disp); - u32 pclk = nv_rd32(disp, 0x610ad0 + (head * 0x540)) & 0x3fffff; + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_devinit *devinit = device->devinit; + u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; if (pclk) devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); } @@ -1635,17 +1653,18 @@ static void nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, struct dcb_output *outp, u32 pclk) { + struct nvkm_device *device = disp->base.engine.subdev.device; const int link = !(outp->sorconf.link & 1); const int or = ffs(outp->or) - 1; const u32 soff = ( or * 0x800); const u32 loff = (link * 0x080) + soff; - const u32 ctrl = nv_rd32(disp, 0x610794 + (or * 8)); + const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8)); const u32 symbol = 100000; - const s32 vactive = nv_rd32(disp, 0x610af8 + (head * 0x540)) & 0xffff; - const s32 vblanke = nv_rd32(disp, 0x610ae8 + (head * 0x540)) & 0xffff; - const s32 vblanks = nv_rd32(disp, 0x610af0 + (head * 0x540)) & 0xffff; - u32 dpctrl = nv_rd32(disp, 0x61c10c + loff); - u32 clksor = nv_rd32(disp, 0x614300 + soff); + const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff; + const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff; + const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff; + u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff); + u32 clksor = nvkm_rd32(device, 0x614300 + soff); int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; int TU, VTUi, VTUf, VTUa; u64 link_data_rate, link_ratio, unk; @@ -1661,14 +1680,14 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, value = value * link_bw; do_div(value, pclk); value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); - nv_mask(disp, 0x61c1e8 + soff, 0x0000ffff, value); + nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value); /* symbols/vblank - algorithm taken from comments in tegra driver */ value = vblanks - vblanke - 25; value = value * link_bw; do_div(value, pclk); value = value - ((36 / link_nr) + 3) - 1; - nv_mask(disp, 0x61c1ec + soff, 0x00ffffff, value); + nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value); /* watermark / activesym */ if ((ctrl & 0xf0000) == 0x60000) bits = 30; @@ -1744,8 +1763,8 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, do_div(unk, symbol); unk += 6; - nv_mask(disp, 0x61c10c + loff, 0x000001fc, bestTU << 2); - nv_mask(disp, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | + nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2); + nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | bestVTUf << 16 | bestVTUi << 8 | unk); } @@ -1753,8 +1772,9 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, static void nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) { + struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_output *outp; - u32 pclk = nv_rd32(disp, 0x610ad0 + (head * 0x540)) & 0x3fffff; + u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; u32 hval, hreg = 0x614200 + (head * 0x800); u32 oval, oreg; u32 mask, conf; @@ -1786,10 +1806,10 @@ nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) u32 ctrl, datarate; if (outp->info.location == 0) { - ctrl = nv_rd32(disp, 0x610794 + soff); + ctrl = nvkm_rd32(device, 0x610794 + soff); soff = 1; } else { - ctrl = nv_rd32(disp, 0x610b80 + soff); + ctrl = nvkm_rd32(device, 0x610b80 + soff); soff = 2; } @@ -1828,8 +1848,8 @@ nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) mask = 0x00000707; } - nv_mask(disp, hreg, 0x0000000f, hval); - nv_mask(disp, oreg, mask, oval); + nvkm_mask(device, hreg, 0x0000000f, hval); + nvkm_mask(device, oreg, mask, oval); } /* If programming a TMDS output on a SOR that can also be configured for @@ -1844,7 +1864,8 @@ static void nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp, struct dcb_output *outp) { - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; const int link = !(outp->sorconf.link & 1); const int or = ffs(outp->or) - 1; const u32 loff = (or * 0x800) + (link * 0x80); @@ -1853,14 +1874,15 @@ nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp, u8 ver, hdr; if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) - nv_mask(disp, 0x61c10c + loff, 0x00000001, 0x00000000); + nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000); } static void nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head) { + struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_output *outp; - u32 pclk = nv_rd32(disp, 0x610ad0 + (head * 0x540)) & 0x3fffff; + u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; u32 conf; outp = exec_clkcmp(disp, head, 1, pclk, &conf); @@ -1877,7 +1899,8 @@ nv50_disp_intr_supervisor(struct work_struct *work) struct nv50_disp *disp = container_of(work, struct nv50_disp, supervisor); struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; - u32 super = nv_rd32(disp, 0x610030); + struct nvkm_device *device = disp->base.engine.subdev.device; + u32 super = nvkm_rd32(device, 0x610030); int head; nv_debug(disp, "supervisor 0x%08x 0x%08x\n", disp->super, super); @@ -1917,15 +1940,16 @@ nv50_disp_intr_supervisor(struct work_struct *work) } } - nv_wr32(disp, 0x610030, 0x80000000); + nvkm_wr32(device, 0x610030, 0x80000000); } void nv50_disp_intr(struct nvkm_subdev *subdev) { struct nv50_disp *disp = (void *)subdev; - u32 intr0 = nv_rd32(disp, 0x610020); - u32 intr1 = nv_rd32(disp, 0x610024); + struct nvkm_device *device = disp->base.engine.subdev.device; + u32 intr0 = nvkm_rd32(device, 0x610020); + u32 intr1 = nvkm_rd32(device, 0x610024); while (intr0 & 0x001f0000) { u32 chid = __ffs(intr0 & 0x001f0000) - 16; @@ -1941,18 +1965,18 @@ nv50_disp_intr(struct nvkm_subdev *subdev) if (intr1 & 0x00000004) { nvkm_disp_vblank(&disp->base, 0); - nv_wr32(disp, 0x610024, 0x00000004); + nvkm_wr32(device, 0x610024, 0x00000004); } if (intr1 & 0x00000008) { nvkm_disp_vblank(&disp->base, 1); - nv_wr32(disp, 0x610024, 0x00000008); + nvkm_wr32(device, 0x610024, 0x00000008); } if (intr1 & 0x00000070) { disp->super = (intr1 & 0x00000070); schedule_work(&disp->supervisor); - nv_wr32(disp, 0x610024, disp->super); + nvkm_wr32(device, 0x610024, disp->super); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c index 94f0b4d2c890..d93d5945a2d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c @@ -144,6 +144,7 @@ nv50_pior_dp_impl = { int nv50_pior_power(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = outp->or * 0x800; union { struct nv50_disp_pior_pwr_v0 v0; @@ -163,7 +164,7 @@ nv50_pior_power(NV50_DISP_MTHD_V1) return ret; nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000); - nv_mask(disp, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); + nvkm_mask(device, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000); disp->pior.type[outp->or] = type; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c index b4138acc94de..ed4d13222d9d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c @@ -55,8 +55,9 @@ static int g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 loff = g94_sor_loff(outp); - nv_mask(disp, 0x61c10c + loff, 0x0f000000, pattern << 24); + nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24); return 0; } @@ -64,6 +65,7 @@ int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = g94_sor_soff(outp); const u32 loff = g94_sor_loff(outp); u32 mask = 0, i; @@ -71,8 +73,8 @@ g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) for (i = 0; i < nr; i++) mask |= 1 << (g94_sor_dp_lane_map(disp, i) >> 3); - nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask); - nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000); + nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); + nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000); nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000); return 0; } @@ -81,6 +83,7 @@ static int g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = g94_sor_soff(outp); const u32 loff = g94_sor_loff(outp); u32 dpctrl = 0x00000000; @@ -92,8 +95,8 @@ g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) if (bw > 0x06) clksor |= 0x00040000; - nv_mask(disp, 0x614300 + soff, 0x000c0000, clksor); - nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl); + nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor); + nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl); return 0; } @@ -101,7 +104,8 @@ static int g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { struct nv50_disp *disp = (void *)nvkm_disp(outp); - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; const u32 shift = g94_sor_dp_lane_map(disp, ln); const u32 loff = g94_sor_loff(outp); u32 addr, data[3]; @@ -120,14 +124,14 @@ g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) if (!addr) return -EINVAL; - data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift); - data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift); - data[2] = nv_rd32(disp, 0x61c130 + loff); + data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); + data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); + data[2] = nvkm_rd32(device, 0x61c130 + loff); if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); - nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); - nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); - nv_wr32(disp, 0x61c130 + loff, data[2]); + nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); + nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); + nvkm_wr32(device, 0x61c130 + loff, data[2]); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c index 07dbe45996c7..696bc6469377 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c @@ -40,8 +40,9 @@ static int gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 loff = gf110_sor_loff(outp); - nv_mask(disp, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); + nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); return 0; } @@ -49,6 +50,7 @@ int gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = gf110_sor_soff(outp); const u32 loff = gf110_sor_loff(outp); u32 dpctrl = 0x00000000; @@ -59,8 +61,8 @@ gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) if (ef) dpctrl |= 0x00004000; - nv_mask(disp, 0x612300 + soff, 0x007c0000, clksor); - nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl); + nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); + nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl); return 0; } @@ -69,7 +71,8 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { struct nv50_disp *disp = (void *)nvkm_disp(outp); - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; const u32 shift = g94_sor_dp_lane_map(disp, ln); const u32 loff = gf110_sor_loff(outp); u32 addr, data[4]; @@ -88,16 +91,16 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp, if (!addr) return -EINVAL; - data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift); - data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift); - data[2] = nv_rd32(disp, 0x61c130 + loff); + data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); + data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); + data[2] = nvkm_rd32(device, 0x61c130 + loff); if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); - nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); - nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); - nv_wr32(disp, 0x61c130 + loff, data[2]); - data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift); - nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); + nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); + nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); + nvkm_wr32(device, 0x61c130 + loff, data[2]); + data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); + nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c index 3078f4d91972..4c61702ede8a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c @@ -42,12 +42,13 @@ void gm204_sor_magic(struct nvkm_output *outp) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = outp->or * 0x100; const u32 data = outp->or + 1; if (outp->info.sorconf.link & 1) - nv_mask(disp, 0x612308 + soff, 0x0000001f, 0x00000000 | data); + nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data); if (outp->info.sorconf.link & 2) - nv_mask(disp, 0x612388 + soff, 0x0000001f, 0x00000010 | data); + nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data); } static inline u32 @@ -60,12 +61,13 @@ static int gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = gm204_sor_soff(outp); const u32 data = 0x01010101 * pattern; if (outp->base.info.sorconf.link & 1) - nv_mask(disp, 0x61c110 + soff, 0x0f0f0f0f, data); + nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data); else - nv_mask(disp, 0x61c12c + soff, 0x0f0f0f0f, data); + nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data); return 0; } @@ -73,6 +75,7 @@ static int gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_device *device = disp->base.engine.subdev.device; const u32 soff = gm204_sor_soff(outp); const u32 loff = gm204_sor_loff(outp); u32 mask = 0, i; @@ -80,8 +83,8 @@ gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) for (i = 0; i < nr; i++) mask |= 1 << (gm204_sor_dp_lane_map(disp, i) >> 3); - nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask); - nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000); + nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); + nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000); nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000); return 0; } @@ -91,7 +94,8 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { struct nv50_disp *disp = (void *)nvkm_disp(outp); - struct nvkm_bios *bios = nvkm_bios(disp); + struct nvkm_device *device = disp->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; const u32 shift = gm204_sor_dp_lane_map(disp, ln); const u32 loff = gm204_sor_loff(outp); u32 addr, data[4]; @@ -111,16 +115,16 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, return -EINVAL; ocfg.tx_pu &= 0x0f; - data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift); - data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift); - data[2] = nv_rd32(disp, 0x61c130 + loff); + data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); + data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); + data[2] = nvkm_rd32(device, 0x61c130 + loff); if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8); - nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); - nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); - nv_wr32(disp, 0x61c130 + loff, data[2]); - data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift); - nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); + nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); + nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); + nvkm_wr32(device, 0x61c130 + loff, data[2]); + data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); + nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c index 74ad5921b230..bf61ce7bac11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c @@ -33,6 +33,7 @@ int nv50_sor_power(NV50_DISP_MTHD_V1) { + struct nvkm_device *device = disp->base.engine.subdev.device; union { struct nv50_disp_sor_pwr_v0 v0; } *args = data; @@ -49,7 +50,7 @@ nv50_sor_power(NV50_DISP_MTHD_V1) return ret; nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000); - nv_mask(disp, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); + nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000); nv_wait(disp, 0x61c030 + soff, 0x10000000, 0x00000000); return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c index c91d73bc9c9b..9f933ac7e870 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c @@ -29,19 +29,19 @@ nv_rdport(void *obj, int head, u16 port) struct nvkm_device *device = nv_device(obj); if (device->card_type >= NV_50) - return nv_rd08(obj, 0x601000 + port); + return nvkm_rd08(device, 0x601000 + port); if (port == 0x03c0 || port == 0x03c1 || /* AR */ port == 0x03c2 || port == 0x03da || /* INP0 */ port == 0x03d4 || port == 0x03d5) /* CR */ - return nv_rd08(obj, 0x601000 + (head * 0x2000) + port); + return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port); if (port == 0x03c2 || port == 0x03cc || /* MISC */ port == 0x03c4 || port == 0x03c5 || /* SR */ port == 0x03ce || port == 0x03cf) { /* GR */ if (device->card_type < NV_40) head = 0; /* CR44 selects head */ - return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port); + return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port); } nv_error(obj, "unknown vga port 0x%04x\n", port); @@ -54,19 +54,19 @@ nv_wrport(void *obj, int head, u16 port, u8 data) struct nvkm_device *device = nv_device(obj); if (device->card_type >= NV_50) - nv_wr08(obj, 0x601000 + port, data); + nvkm_wr08(device, 0x601000 + port, data); else if (port == 0x03c0 || port == 0x03c1 || /* AR */ port == 0x03c2 || port == 0x03da || /* INP0 */ port == 0x03d4 || port == 0x03d5) /* CR */ - nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data); + nvkm_wr08(device, 0x601000 + (head * 0x2000) + port, data); else if (port == 0x03c2 || port == 0x03cc || /* MISC */ port == 0x03c4 || port == 0x03c5 || /* SR */ port == 0x03ce || port == 0x03cf) { /* GR */ if (device->card_type < NV_40) head = 0; /* CR44 selects head */ - nv_wr08(obj, 0x0c0000 + (head * 0x2000) + port, data); + nvkm_wr08(device, 0x0c0000 + (head * 0x2000) + port, data); } else nv_error(obj, "unknown vga port 0x%04x\n", port); } @@ -135,16 +135,16 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value) bool nv_lockvgac(void *obj, bool lock) { - struct nvkm_device *dev = nv_device(obj); + struct nvkm_device *device = nv_device(obj); bool locked = !nv_rdvgac(obj, 0, 0x1f); u8 data = lock ? 0x99 : 0x57; - if (dev->card_type < NV_50) + if (device->card_type < NV_50) nv_wrvgac(obj, 0, 0x1f, data); else nv_wrvgac(obj, 0, 0x3f, data); - if (dev->chipset == 0x11) { - if (!(nv_rd32(obj, 0x001084) & 0x10000000)) + if (device->chipset == 0x11) { + if (!(nvkm_rd32(device, 0x001084) & 0x10000000)) nv_wrvgac(obj, 1, 0x1f, data); } return locked; @@ -171,9 +171,10 @@ nv_lockvgac(void *obj, bool lock) u8 nv_rdvgaowner(void *obj) { - if (nv_device(obj)->card_type < NV_50) { + struct nvkm_device *device = nv_device(obj); + if (device->card_type < NV_50) { if (nv_device(obj)->chipset == 0x11) { - u32 tied = nv_rd32(obj, 0x001084) & 0x10000000; + u32 tied = nvkm_rd32(device, 0x001084) & 0x10000000; if (tied == 0) { u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80; u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01; -- cgit v1.2.3