drm/nouveau/gr: convert to new-style nvkm_engine

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

10 files changed, 69 insertions, 139 deletions

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 62395ab742c5..3cf15d46f9d2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -89,7 +89,7 @@ nv4_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv04_fifo_new,
-//	.gr = nv04_gr_new,
+	.gr = nv04_gr_new,
 //	.sw = nv04_sw_new,
 };
 
@@ -109,7 +109,7 @@ nv5_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv04_fifo_new,
-//	.gr = nv04_gr_new,
+	.gr = nv04_gr_new,
 //	.sw = nv04_sw_new,
 };
 
@@ -129,7 +129,7 @@ nv10_chipset = {
 	.timer = nv04_timer_new,
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
-//	.gr = nv10_gr_new,
+	.gr = nv10_gr_new,
 };
 
 static const struct nvkm_device_chip
@@ -149,7 +149,7 @@ nv11_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv10_fifo_new,
-//	.gr = nv10_gr_new,
+	.gr = nv15_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -170,7 +170,7 @@ nv15_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv10_fifo_new,
-//	.gr = nv10_gr_new,
+	.gr = nv15_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -191,7 +191,7 @@ nv17_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv10_gr_new,
+	.gr = nv17_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -212,7 +212,7 @@ nv18_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv10_gr_new,
+	.gr = nv17_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -233,7 +233,7 @@ nv1a_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv10_fifo_new,
-//	.gr = nv10_gr_new,
+	.gr = nv15_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -254,7 +254,7 @@ nv1f_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv10_gr_new,
+	.gr = nv17_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -275,7 +275,7 @@ nv20_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv20_gr_new,
+	.gr = nv20_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -296,7 +296,7 @@ nv25_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv25_gr_new,
+	.gr = nv25_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -317,7 +317,7 @@ nv28_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv25_gr_new,
+	.gr = nv25_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -338,7 +338,7 @@ nv2a_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv2a_gr_new,
+	.gr = nv2a_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -359,7 +359,7 @@ nv30_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv30_gr_new,
+	.gr = nv30_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -380,7 +380,7 @@ nv31_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv30_gr_new,
+	.gr = nv30_gr_new,
 //	.mpeg = nv31_mpeg_new,
 //	.sw = nv10_sw_new,
 };
@@ -402,7 +402,7 @@ nv34_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv34_gr_new,
+	.gr = nv34_gr_new,
 //	.mpeg = nv31_mpeg_new,
 //	.sw = nv10_sw_new,
 };
@@ -424,7 +424,7 @@ nv35_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv35_gr_new,
+	.gr = nv35_gr_new,
 //	.sw = nv10_sw_new,
 };
 
@@ -445,7 +445,7 @@ nv36_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv17_fifo_new,
-//	.gr = nv35_gr_new,
+	.gr = nv35_gr_new,
 //	.mpeg = nv31_mpeg_new,
 //	.sw = nv10_sw_new,
 };
@@ -469,7 +469,7 @@ nv40_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv40_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -494,7 +494,7 @@ nv41_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv40_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -519,7 +519,7 @@ nv42_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv40_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -544,7 +544,7 @@ nv43_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv40_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -569,7 +569,7 @@ nv44_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -594,7 +594,7 @@ nv45_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -619,7 +619,7 @@ nv46_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -644,7 +644,7 @@ nv47_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -669,7 +669,7 @@ nv49_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -694,7 +694,7 @@ nv4a_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -719,7 +719,7 @@ nv4b_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv40_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -744,7 +744,7 @@ nv4c_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -769,7 +769,7 @@ nv4e_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -797,7 +797,7 @@ nv50_chipset = {
 	.disp = nv50_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = nv50_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = nv50_gr_new,
 //	.mpeg = nv50_mpeg_new,
 //	.pm = nv50_pm_new,
 //	.sw = nv50_sw_new,
@@ -822,7 +822,7 @@ nv63_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -847,7 +847,7 @@ nv67_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -872,7 +872,7 @@ nv68_chipset = {
 	.disp = nv04_disp_new,
 	.dma = nv04_dma_new,
 	.fifo = nv40_fifo_new,
-//	.gr = nv40_gr_new,
+	.gr = nv44_gr_new,
 //	.mpeg = nv44_mpeg_new,
 //	.pm = nv40_pm_new,
 //	.sw = nv10_sw_new,
@@ -902,7 +902,7 @@ nv84_chipset = {
 	.disp = g84_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = g84_gr_new,
 //	.mpeg = g84_mpeg_new,
 //	.pm = g84_pm_new,
 //	.sw = nv50_sw_new,
@@ -933,7 +933,7 @@ nv86_chipset = {
 	.disp = g84_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = g84_gr_new,
 //	.mpeg = g84_mpeg_new,
 //	.pm = g84_pm_new,
 //	.sw = nv50_sw_new,
@@ -964,7 +964,7 @@ nv92_chipset = {
 	.disp = g84_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = g84_gr_new,
 //	.mpeg = g84_mpeg_new,
 //	.pm = g84_pm_new,
 //	.sw = nv50_sw_new,
@@ -995,7 +995,7 @@ nv94_chipset = {
 	.disp = g94_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = g84_gr_new,
 //	.mpeg = g84_mpeg_new,
 //	.pm = g84_pm_new,
 //	.sw = nv50_sw_new,
@@ -1024,7 +1024,7 @@ nv96_chipset = {
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
 //	.sw = nv50_sw_new,
-//	.gr = nv50_gr_new,
+	.gr = g84_gr_new,
 //	.mpeg = g84_mpeg_new,
 	.vp = g84_vp_new,
 	.cipher = g84_cipher_new,
@@ -1055,7 +1055,7 @@ nv98_chipset = {
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
 //	.sw = nv50_sw_new,
-//	.gr = nv50_gr_new,
+	.gr = g84_gr_new,
 	.mspdec = g98_mspdec_new,
 	.sec = g98_sec_new,
 	.msvld = g98_msvld_new,
@@ -1088,7 +1088,7 @@ nva0_chipset = {
 	.disp = gt200_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = gt200_gr_new,
 //	.mpeg = g84_mpeg_new,
 //	.pm = gt200_pm_new,
 //	.sw = nv50_sw_new,
@@ -1119,7 +1119,7 @@ nva3_chipset = {
 	.disp = gt215_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = gt215_gr_new,
 //	.mpeg = g84_mpeg_new,
 	.mspdec = gt215_mspdec_new,
 	.msppp = gt215_msppp_new,
@@ -1152,7 +1152,7 @@ nva5_chipset = {
 	.disp = gt215_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = gt215_gr_new,
 	.mspdec = gt215_mspdec_new,
 	.msppp = gt215_msppp_new,
 	.msvld = gt215_msvld_new,
@@ -1184,7 +1184,7 @@ nva8_chipset = {
 	.disp = gt215_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = gt215_gr_new,
 	.mspdec = gt215_mspdec_new,
 	.msppp = gt215_msppp_new,
 	.msvld = gt215_msvld_new,
@@ -1214,7 +1214,7 @@ nvaa_chipset = {
 	.disp = g94_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = gt200_gr_new,
 	.mspdec = g98_mspdec_new,
 	.msppp = g98_msppp_new,
 	.msvld = g98_msvld_new,
@@ -1245,7 +1245,7 @@ nvac_chipset = {
 	.disp = g94_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = mcp79_gr_new,
 	.mspdec = g98_mspdec_new,
 	.msppp = g98_msppp_new,
 	.msvld = g98_msvld_new,
@@ -1278,7 +1278,7 @@ nvaf_chipset = {
 	.disp = gt215_disp_new,
 	.dma = nv50_dma_new,
 	.fifo = g84_fifo_new,
-//	.gr = nv50_gr_new,
+	.gr = mcp89_gr_new,
 	.mspdec = gt215_mspdec_new,
 	.msppp = gt215_msppp_new,
 	.msvld = mcp89_msvld_new,
@@ -1313,7 +1313,7 @@ nvc0_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf100_gr_new,
+	.gr = gf100_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1347,7 +1347,7 @@ nvc1_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf108_gr_new,
+	.gr = gf108_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1381,7 +1381,7 @@ nvc3_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf104_gr_new,
+	.gr = gf104_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1416,7 +1416,7 @@ nvc4_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf104_gr_new,
+	.gr = gf104_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1451,7 +1451,7 @@ nvc8_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf110_gr_new,
+	.gr = gf110_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1486,7 +1486,7 @@ nvce_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf104_gr_new,
+	.gr = gf104_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1520,7 +1520,7 @@ nvcf_chipset = {
 	.disp = gt215_disp_new,
 	.dma = gf100_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf104_gr_new,
+	.gr = gf104_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1552,7 +1552,7 @@ nvd7_chipset = {
 	.disp = gf119_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf117_gr_new,
+	.gr = gf117_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1586,7 +1586,7 @@ nvd9_chipset = {
 	.disp = gf119_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gf100_fifo_new,
-//	.gr = gf119_gr_new,
+	.gr = gf119_gr_new,
 	.mspdec = gf100_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gf100_msvld_new,
@@ -1622,7 +1622,7 @@ nve4_chipset = {
 	.disp = gk104_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk104_fifo_new,
-//	.gr = gk104_gr_new,
+	.gr = gk104_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1658,7 +1658,7 @@ nve6_chipset = {
 	.disp = gk104_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk104_fifo_new,
-//	.gr = gk104_gr_new,
+	.gr = gk104_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1694,7 +1694,7 @@ nve7_chipset = {
 	.disp = gk104_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk104_fifo_new,
-//	.gr = gk104_gr_new,
+	.gr = gk104_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1721,7 +1721,7 @@ nvea_chipset = {
 	.ce[2] = gk104_ce_new,
 	.dma = gf119_dma_new,
 	.fifo = gk20a_fifo_new,
-//	.gr = gk20a_gr_new,
+	.gr = gk20a_gr_new,
 //	.pm = gk104_pm_new,
 //	.sw = gf100_sw_new,
 };
@@ -1754,7 +1754,7 @@ nvf0_chipset = {
 	.disp = gk110_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk104_fifo_new,
-//	.gr = gk110_gr_new,
+	.gr = gk110_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1790,7 +1790,7 @@ nvf1_chipset = {
 	.disp = gk110_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk104_fifo_new,
-//	.gr = gk110b_gr_new,
+	.gr = gk110b_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1826,7 +1826,7 @@ nv106_chipset = {
 	.disp = gk110_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk208_fifo_new,
-//	.gr = gk208_gr_new,
+	.gr = gk208_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1861,7 +1861,7 @@ nv108_chipset = {
 	.disp = gk110_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk208_fifo_new,
-//	.gr = gk208_gr_new,
+	.gr = gk208_gr_new,
 	.mspdec = gk104_mspdec_new,
 	.msppp = gf100_msppp_new,
 	.msvld = gk104_msvld_new,
@@ -1894,7 +1894,7 @@ nv117_chipset = {
 	.disp = gm107_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gk208_fifo_new,
-//	.gr = gm107_gr_new,
+	.gr = gm107_gr_new,
 //	.sw = gf100_sw_new,
 };
 
@@ -1923,7 +1923,7 @@ nv124_chipset = {
 	.disp = gm204_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gm204_fifo_new,
-//	.gr = gm204_gr_new,
+	.gr = gm204_gr_new,
 //	.sw = gf100_sw_new,
 };
 
@@ -1952,7 +1952,7 @@ nv126_chipset = {
 	.disp = gm204_disp_new,
 	.dma = gf119_dma_new,
 	.fifo = gm204_fifo_new,
-//	.gr = gm206_gr_new,
+	.gr = gm206_gr_new,
 //	.sw = gf100_sw_new,
 };
 
@@ -1973,7 +1973,7 @@ nv12b_chipset = {
 	.ce[2] = gm204_ce_new,
 	.dma = gf119_dma_new,
 	.fifo = gm20b_fifo_new,
-//	.gr = gm20b_gr_new,
+	.gr = gm20b_gr_new,
 //	.sw = gf100_sw_new,
 };
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index d319f5680f44..b88aceb343c8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -29,47 +29,38 @@ gf100_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0xc0:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
 		break;
 	case 0xc4:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
 		break;
 	case 0xc3:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
 		break;
 	case 0xce:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
 		break;
 	case 0xcf:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
 		break;
 	case 0xc1:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf108_pm_oclass;
 		break;
 	case 0xc8:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
 		break;
 	case 0xd9:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;
 		break;
 	case 0xd7:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;
 		break;
 	default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index fe8298e02e9f..1ad7b217e2b8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -29,41 +29,33 @@ gk104_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0xe4:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
 		break;
 	case 0xe7:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
 		break;
 	case 0xe6:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
 		break;
 	case 0xea:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
 		break;
 	case 0xf0:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk110_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &gk110_pm_oclass;
 		break;
 	case 0xf1:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &gk110_pm_oclass;
 		break;
 	case 0x106:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
 		break;
 	case 0x108:
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
 		break;
 	default:
 		return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 2362a634462c..71e088abb620 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -32,7 +32,6 @@ gm100_identify(struct nvkm_device *device)
 #if 0
 #endif
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 #if 0
 #endif
 #if 0
@@ -46,7 +45,6 @@ gm100_identify(struct nvkm_device *device)
 #if 0
 #endif
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm204_gr_oclass;
 #if 0
 #endif
 		break;
@@ -58,14 +56,12 @@ gm100_identify(struct nvkm_device *device)
 #if 0
 #endif
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm206_gr_oclass;
 #if 0
 #endif
 		break;
 	case 0x12b:
 
 		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] =  gm20b_gr_oclass;
 		break;
 	default:
 		return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index edddbaa41b43..7a8071be7ed0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -29,11 +29,9 @@ nv04_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0x04:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
 		break;
 	case 0x05:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
 		break;
 	default:
 		return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index f1ebb9bcda3b..15dbd71ebabf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -28,35 +28,27 @@ nv10_identify(struct nvkm_device *device)
 {
 	switch (device->chipset) {
 	case 0x10:
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x15:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x16:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x1a:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x11:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x17:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x1f:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	case 0x18:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
 		break;
 	default:
 		return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index f9c4dad1f8ff..158efa44054f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -29,19 +29,15 @@ nv20_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0x20:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_gr_oclass;
 		break;
 	case 0x25:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
 		break;
 	case 0x28:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
 		break;
 	case 0x2a:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_gr_oclass;
 		break;
 	default:
 		return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index b8e1e43723a3..5a8fd485467a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -29,25 +29,20 @@ nv30_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0x30:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
 		break;
 	case 0x35:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
 		break;
 	case 0x31:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		break;
 	case 0x36:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		break;
 	case 0x34:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 		break;
 	default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 158ed5e395df..e3fdbf6ba871 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -29,97 +29,81 @@ nv40_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0x40:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x41:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x42:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x43:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x45:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x47:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x49:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x4b:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x44:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x46:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x4a:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x4c:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x4e:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x63:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x67:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	case 0x68:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 688b3e2d61ff..912bd8070db7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -29,80 +29,66 @@ nv50_identify(struct nvkm_device *device)
 	switch (device->chipset) {
 	case 0x50:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
 		break;
 	case 0x84:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0x86:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0x92:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0x94:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0x96:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0x98:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0xa0:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  gt200_pm_oclass;
 		break;
 	case 0xaa:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0xac:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 		break;
 	case 0xa3:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 		break;
 	case 0xa5:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 		break;
 	case 0xa8:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 		break;
 	case 0xaf:
 		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
-		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 		break;
 	default: