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2015-08-04Merge branch 'linux-linaro-lsk-v3.14' into linux-linaro-lsk-v3.14-androidlinux-linaro-lsk-v3.14-android-testKevin Hilman
2015-08-03Merge tag 'v3.14.48' of git://git./linux/kernel/git/stable/linux-stable into ↵Shannon Zhao
linux-linaro-lsk-v3.14 Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Conflicts: include/kvm/arm_vgic.h virt/kvm/arm/vgic.c virt/kvm/arm/vgic-v2.c virt/kvm/arm/vgic-v3.c
2015-07-10arm64: KVM: Do not use pgd_index to index stage-2 pgdMarc Zyngier
commit 04b8dc85bf4a64517e3cf20e409eeaa503b15cc1 upstream. [Since we don't backport commit c647355 (KVM: arm: Add initial dirty page locking support) for linux-3.14.y, there is no stage2_wp_range in arch/arm/kvm/mmu.c. So ignore the change in stage2_wp_range introduced by this patch.] The kernel's pgd_index macro is designed to index a normal, page sized array. KVM is a bit diffferent, as we can use concatenated pages to have a bigger address space (for example 40bit IPA with 4kB pages gives us an 8kB PGD. In the above case, the use of pgd_index will always return an index inside the first 4kB, which makes a guest that has memory above 0x8000000000 rather unhappy, as it spins forever in a page fault, whist the host happilly corrupts the lower pgd. The obvious fix is to get our own kvm_pgd_index that does the right thing(tm). Tested on X-Gene with a hacked kvmtool that put memory at a stupidly high address. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-10arm64: KVM: Fix HCR setting for 32bit guestsMarc Zyngier
commit 801f6772cecea6cfc7da61aa197716ab64db5f9e upstream. Commit b856a59141b1 (arm/arm64: KVM: Reset the HCR on each vcpu when resetting the vcpu) moved the init of the HCR register to happen later in the init of a vcpu, but left out the fixup done in kvm_reset_vcpu when preparing for a 32bit guest. As a result, the 32bit guest is run as a 64bit guest, but the rest of the kernel still manages it as a 32bit. Fun follows. Moving the fixup to vcpu_reset_hcr solves the problem for good. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-07Merge tag 'v3.14.47' of git://git./linux/kernel/git/stable/linux-stable into ↵Shannon Zhao
linux-linaro-lsk-v3.14 Conflicts: arch/arm/include/asm/kvm_mmu.h arch/arm/kvm/mmu.c arch/arm64/include/asm/kvm_arm.h arch/arm64/include/asm/kvm_host.h arch/arm64/include/asm/kvm_mmu.h virt/kvm/arm/vgic.c
2015-07-03arm/arm64: KVM: Introduce stage2_unmap_vmChristoffer Dall
commit 957db105c99792ae8ef61ffc9ae77d910f6471da upstream. Introduce a new function to unmap user RAM regions in the stage2 page tables. This is needed on reboot (or when the guest turns off the MMU) to ensure we fault in pages again and make the dcache, RAM, and icache coherent. Using unmap_stage2_range for the whole guest physical range does not work, because that unmaps IO regions (such as the GIC) which will not be recreated or in the best case faulted in on a page-by-page basis. Call this function on secondary and subsequent calls to the KVM_ARM_VCPU_INIT ioctl so that a reset VCPU will detect the guest Stage-1 MMU is off when faulting in pages and make the caches coherent. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-03arm/arm64: KVM: Reset the HCR on each vcpu when resetting the vcpuChristoffer Dall
commit b856a59141b1066d3c896a0d0231f84dabd040af upstream. When userspace resets the vcpu using KVM_ARM_VCPU_INIT, we should also reset the HCR, because we now modify the HCR dynamically to enable/disable trapping of guest accesses to the VM registers. This is crucial for reboot of VMs working since otherwise we will not be doing the necessary cache maintenance operations when faulting in pages with the guest MMU off. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-03arm64/kvm: Fix assembler compatibility of macrosGeoff Levand
commit 286fb1cc32b11c18da3573a8c8c37a4f9da16e30 upstream. Some of the macros defined in kvm_arm.h are useful in assembly files, but are not compatible with the assembler. Change any C language integer constant definitions using appended U, UL, or ULL to the UL() preprocessor macro. Also, add a preprocessor include of the asm/memory.h file which defines the UL() macro. Fixes build errors like these when using kvm_arm.h in assembly source files: Error: unexpected characters following instruction at operand 3 -- `and x0,x1,#((1U<<25)-1)' Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Geoff Levand <geoff@infradead.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-03arm/arm64: KVM: Fix VTTBR_BADDR_MASK and pgd allocJoel Schopp
commit dbff124e29fa24aff9705b354b5f4648cd96e0bb upstream. The current aarch64 calculation for VTTBR_BADDR_MASK masks only 39 bits and not all the bits in the PA range. This is clearly a bug that manifests itself on systems that allocate memory in the higher address space range. [ Modified from Joel's original patch to be based on PHYS_MASK_SHIFT instead of a hard-coded value and to move the alignment check of the allocation to mmu.c. Also added a comment explaining why we hardcode the IPA range and changed the stage-2 pgd allocation to be based on the 40 bit IPA range instead of the maximum possible 48 bit PA range. - Christoffer ] Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Joel Schopp <joel.schopp@amd.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-03ARM/arm64: KVM: fix use of WnR bit in kvm_is_write_fault()Ard Biesheuvel
commit a7d079cea2dffb112e26da2566dd84c0ef1fce97 upstream. [Since we don't backport commit 9804788 (arm/arm64: KVM: Support KVM_CAP_READONLY_MEM), ingore the changes in kvm_handle_guest_abort introduced by this patch.] The ISS encoding for an exception from a Data Abort has a WnR bit[6] that indicates whether the Data Abort was caused by a read or a write instruction. While there are several fields in the encoding that are only valid if the ISV bit[24] is set, WnR is not one of them, so we can read it unconditionally. Instead of fixing both implementations of kvm_is_write_fault() in place, reimplement it just once using kvm_vcpu_dabt_iswrite(), which already does the right thing with respect to the WnR bit. Also fix up the callers to pass 'vcpu' Acked-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-06-29KVM: ARM/arm64: fix broken __percpu annotationWill Deacon
commit 4000be423cb01a8d09de878bb8184511c49d4238 upstream. Running sparse results in a bunch of noisy address space mismatches thanks to the broken __percpu annotation on kvm_get_running_vcpus. This function returns a pcpu pointer to a pointer, not a pointer to a pcpu pointer. This patch fixes the annotation, which kills the warnings from sparse. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-06-29KVM: ARM/arm64: fix non-const declaration of function returning constWill Deacon
commit 6951e48bff0b55d2a8e825a953fc1f8e3a34bf1c upstream. Sparse kicks up about a type mismatch for kvm_target_cpu: arch/arm64/kvm/guest.c:271:25: error: symbol 'kvm_target_cpu' redeclared with different type (originally declared at ./arch/arm64/include/asm/kvm_host.h:45) - different modifiers so fix this by adding the missing const attribute to the function declaration. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-06-29arm/arm64: KVM: Fix and refactor unmap_rangeChristoffer Dall
commit 4f853a714bf16338ff5261128e6c7ae2569e9505 upstream. unmap_range() was utterly broken, to quote Marc, and broke in all sorts of situations. It was also quite complicated to follow and didn't follow the usual scheme of having a separate iterating function for each level of page tables. Address this by refactoring the code and introduce a pgd_clear() function. Reviewed-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Mario Smarduch <m.smarduch@samsung.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-06-25Merge branch 'linux-linaro-lsk-v3.14' into linux-linaro-lsk-v3.14-androidlsk-v3.14-15.07-androidAlex Shi
Conflicts: fs/exec.c Solutions: follow commit d221244a7 sched: move no_new_privs into new atomic flags to use task_no_new_privs(current).
2015-06-10Merge branch 'linaro-android-3.14-lsk' of ↵lsk-v3.14-15.06-androidKevin Hilman
git://android.git.linaro.org/kernel/linaro-android into linux-linaro-lsk-v3.14-android * 'linaro-android-3.14-lsk' of git://android.git.linaro.org/kernel/linaro-android: fix: align closely to AOSP. sched: cpufreq: update power usage only if cpufreq_stat is enabled uid_cputime: Extends the cputime functionality to report power per uid sched: cpufreq: Adds a field cpu_power in the task_struct cpufreq_stats: Adds the fucntionality to load current values for each frequency for all the cores. New Build Breakage in branch: kernel-m-dev-tegra-flounder-3.10 @ 1960706 net/unix: sk_socket can disappear when state is unlocked selinux: enable genfscon labeling for sysfs and pstore files ext4: don't save the error information if the block device is read-only selinux: enable per-file labeling for debugfs files. cpufreq: interactive: Rearm governor timer at max freq cpufreq: interactive: Implement cluster-based min_sample_time cpufreq: interactive: Exercise hispeed settings at a policy level suspend: Return error when pending wakeup source is found. proc: uid_cputime: fix show_uid_stat permission nf: IDLETIMER: Fix broken uid field in the msg
2015-06-08fix: align closely to AOSP.Sumit Semwal
To support Android on a member platform, LMG carry forwarded quiet a few (200+) aosp/android-3.10 patches to linaro-android-3.14-lsk tree when aosp/android-3.14 was not announced. There are few gaps in our forward-ported branch from 3.10->3.14, and how AOSP is maintaining the patches. This consolidated patch help align our tree with AOSP, unless we've added some fixes. Listed below are file-wise changes and rationale behind them: - arch/arm/Kconfig: c0cc1d84: seccomp revert is missing from AOSP, potentially because of cleaner seccomp patches => Align with AOSP. - arch/arm/mm/mmu.c: 97b095e5: "ARM: mm: Split memory banks that span multiple sections when sparsemem is enabled" doesn't seem required anymore, and isn't added to AOSP => Align with AOSP. - arch/arm64/Kconfig: 27aa5398: "arm64: a backwards compatible config option", and 8354fc2d: "arm64: cpuinfo: ARMv7 compatable cpuinfo option" are reverted in AOSP trees => Remove and align with AOSP - arch/arm64/include/asm/debug-monitors.h: Minor differences with AOSP merge v/s ours => Align with AOSP - arch/mips/include/uapi/asm/unistd.h: 598966e MIPS: add seccomp syscall has merge differences between AOSP and ours => Align with AOSP. - drivers/mmc/core/core.c: drivers/mmc/core/host.c: include/linux/mmc/host.h: 2f76feb mmc: core: host: only use wakelock for detect work by Colin Cross: was present in 3.10,and so in fwd-port; Missing from 3.14/3.18; it als introduced a memory leak w/ TI => Align with AOSP by reverting the above commit - drivers/usb/gadget/f_accessory.c: feee075e: "usb: gadget: f_accessory: fix missing NULL pointer check" by Amit Pundir that was being carried in linaro-fixes isn't required anymore due to the AOSP merged fix. => Align with AOSP. - drivers/usb/gadget/u_ether.c: minor code rearrangement during our merge => ALIGN with AOSP. - include/net/bluetooth/hci.h: include/net/bluetooth/hci_core.h: net/bluetooth/hci_conn.c: net/bluetooth/hci_event.c: net/bluetooth/rfcomm/core.c: => BT Patches not in 3.14/3.18; ALIGN with AOSP. - include/net/netfilter/ipv4/nf_reject.h: include/net/netfilter/ipv6/nf_reject.h: net/ipv4/netfilter/Kconfig: net/ipv6/netfilter/Kconfig: 8d83a89758: netfilter: have ip*t REJECT set the sock err when an icmp is to be sent: NOT in 3.14/3.18 => ALIGN with AOSP - include/uapi/asm-generic/unistd.h: 08f6b117d: seccomp: add "seccomp" syscall has merge differences between our merge and AOSP's => ALIGN with AOSP - kernel/irq/pm.c: c2d35c6 irq: pm: Remove unused variable by Dmitry Shmidt => ALIGN with AOSP. - kernel/power/wakelock.c: 11388c8 PM / Sleep: Require CAP_BLOCK_SUSPEND to use wake_lock/wake_unlock by Rafael J. Wysocki has merge differences between our merge and AOSP's => ALIGN with AOSP - kernel/sys.c: 77d83f8d: prctl: adds PR_SET_TIMERSLACK_PID for setting timer slack of an arbitrary thread has merge differences between our merge and AOSP's => ALIGN with AOSP - net/wireless/Kconfig: net/wireless/sme.c: CONFIG_CFG80211 related patches are not in 3.14/3.18 AOSP => ALIGN with AOSP Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
2015-05-26Merge branch 'linux-3.14.y' of ↵Shannon Zhao
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into linux-linaro-lsk-v3.14 Conflicts: arch/arm/include/asm/kvm_mmu.h arch/arm/kvm/mmu.c arch/arm64/include/asm/kvm_arm.h arch/arm64/include/asm/kvm_mmu.h arch/arm64/kvm/sys_regs.c virt/kvm/arm/vgic.c
2015-05-17arm64: KVM: flush VM pages before letting the guest enable cachesMarc Zyngier
commit 9d218a1fcf4c6b759d442ef702842fae92e1ea61 upstream. When the guest runs with caches disabled (like in an early boot sequence, for example), all the writes are diectly going to RAM, bypassing the caches altogether. Once the MMU and caches are enabled, whatever sits in the cache becomes suddenly visible, which isn't what the guest expects. A way to avoid this potential disaster is to invalidate the cache when the MMU is being turned on. For this, we hook into the SCTLR_EL1 trapping code, and scan the stage-2 page tables, invalidating the pages/sections that have already been mapped in. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Cc: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-17ARM: KVM: introduce kvm_p*d_addr_endMarc Zyngier
commit a3c8bd31af260a17d626514f636849ee1cd1f63e upstream. The use of p*d_addr_end with stage-2 translation is slightly dodgy, as the IPA is 40bits, while all the p*d_addr_end helpers are taking an unsigned long (arm64 is fine with that as unligned long is 64bit). The fix is to introduce 64bit clean versions of the same helpers, and use them in the stage-2 page table code. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Cc: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-17arm64: KVM: trap VM system registers until MMU and caches are ONMarc Zyngier
commit 4d44923b17bff283c002ed961373848284aaff1b upstream. In order to be able to detect the point where the guest enables its MMU and caches, trap all the VM related system registers. Once we see the guest enabling both the MMU and the caches, we can go back to a saner mode of operation, which is to leave these registers in complete control of the guest. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Cc: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-17arm64: KVM: force cache clean on page fault when caches are offMarc Zyngier
commit 2d58b733c87689d3d5144e4ac94ea861cc729145 upstream. In order for the guest with caches off to observe data written contained in a given page, we need to make sure that page is committed to memory, and not just hanging in the cache (as guest accesses are completely bypassing the cache until it decides to enable it). For this purpose, hook into the coherent_icache_guest_page function and flush the region if the guest SCTLR_EL1 register doesn't show the MMU and caches as being enabled. The function also get renamed to coherent_cache_guest_page. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Cc: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-04-18Merge branch 'linux-linaro-lsk-v3.14' into linux-linaro-lsk-v3.14-androidAlex Shi
Conflicts: arch/x86/syscalls/syscall_64.tbl
2015-04-18Merge remote-tracking branch 'origin/v3.14/topic/overlayfs' into ↵Alex Shi
linux-linaro-lsk-v3.14
2015-04-13arm64: Use the reserved TTBR0 if context switching to the init_mmCatalin Marinas
commit e53f21bce4d35a93b23d8fa1a840860f6c74f59e upstream. The idle_task_exit() function may call switch_mm() with next == &init_mm. On arm64, init_mm.pgd cannot be used for user mappings, so this patch simply sets the reserved TTBR0. Reported-by: Jon Medhurst (Tixy) <tixy@linaro.org> Tested-by: Jon Medhurst (Tixy) <tixy@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-03-13Merge branch 'linux-linaro-lsk-v3.14' into linux-linaro-lsk-v3.14-androidAlex Shi
Remove cpuinfo_arm64/cpuinfo_store_cpu() that comes from commit 42b34c73ae40(used for stable kernel only), since we have newer commit 5aa9ef6f286. Conflicts: arch/arm64/include/asm/cputype.h arch/arm64/kernel/setup.c
2015-03-03Merge tag 'v3.14.34' into linux-linaro-lsk-v3.14Mark Brown
This is the 3.14.34 stable release Conflicts: arch/arm64/kernel/setup.c
2015-02-25ARM: android: Fix previous fixlsk-v3.14-android-15.02lsk-v3.14-android-14.02Mark Brown
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-02-23Merge remote-tracking branch 'lsk/v3.14/topic/aosp' into ↵Mark Brown
linux-linaro-lsk-v3.14-android
2015-02-23arm64: android: Move ARMv8 deprecated instructions under __ASSEMBLY__ guardsv3.14/topic/aospAmit Pundir
Move recently added ARMV8 deprecated instructions under __ASSEMBLY_ guards in insn.h, otherwise we run into following build error if FUNCTION_TRACER is enabled: -----8<----- arch/arm64/include/asm/insn.h:113: Error: unknown mnemonic `bool' -- `bool aarch32_insn_is_wide(u32 insn)' arch/arm64/include/asm/insn.h:119: Error: unknown mnemonic `u32' -- `u32 aarch32_insn_extract_reg_num(u32 insn,int offset)' arch/arm64/include/asm/insn.h:120: Error: unknown mnemonic `u32' -- `u32 aarch32_insn_mcr_extract_opc2(u32 insn)' arch/arm64/include/asm/insn.h:121: Error: unknown mnemonic `u32' -- `u32 aarch32_insn_mcr_extract_crm(u32 insn)' make[3]: *** [arch/arm64/kernel/entry-ftrace.o] Error 1 ----->8----- Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-02-20Merge branch 'linaro-android-3.14-lsk' into linux-linaro-lsk-v3.14-androidAmit Pundir
* linaro-android-3.14-lsk: (52 commits) xt_qtaguid: use sock_gen_put() instead of xt_socket_put_sk() android: base-cfg: enable ARMV8_DEPRECATED and subfeatures arm64: kconfig: move emulation option under kernel features kbuild: make it possible to specify the module output dir arm64: Emulate SETEND for AArch32 tasks arm64: Consolidate hotplug notifier for instruction emulation arm64: kernel: explicitly add include in armv8_deprecated arm64: Track system support for mixed endian EL0 arm64: Fix up /proc/cpuinfo arm64: cpuinfo: record cpu system register values arm64: add MIDR_EL1 field accessors arm64: fix return code check when changing emulation handler arm64: Trace emulation of AArch32 legacy instructions arm64: Emulate CP15 Barrier instructions arm64: barriers: add dmb barrier arm64: Port SWP/SWPB emulation support from arm arm64: Add framework for legacy instruction emulation arm64: Add AArch32 instruction set condition code checks arm64: Add support for hooks to handle undefined instructions arm64: kernel: Explicitly add include in traps.c ... Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Conflicts: arch/arm64/include/asm/barrier.h arch/arm64/include/asm/cputype.h arch/arm64/include/asm/insn.h arch/arm64/kernel/Makefile arch/arm64/kernel/setup.c
2015-02-12Merge branch 'android-3.14' of ↵Amit Pundir
https://android.googlesource.com/kernel/common into linaro-android-3.14-lsk * aosp/android-3.14: (52 commits) xt_qtaguid: use sock_gen_put() instead of xt_socket_put_sk() android: base-cfg: enable ARMV8_DEPRECATED and subfeatures arm64: kconfig: move emulation option under kernel features kbuild: make it possible to specify the module output dir arm64: Emulate SETEND for AArch32 tasks arm64: Consolidate hotplug notifier for instruction emulation arm64: kernel: explicitly add include in armv8_deprecated arm64: Track system support for mixed endian EL0 arm64: Fix up /proc/cpuinfo arm64: cpuinfo: record cpu system register values arm64: add MIDR_EL1 field accessors arm64: fix return code check when changing emulation handler arm64: Trace emulation of AArch32 legacy instructions arm64: Emulate CP15 Barrier instructions arm64: barriers: add dmb barrier arm64: Port SWP/SWPB emulation support from arm arm64: Add framework for legacy instruction emulation arm64: Add AArch32 instruction set condition code checks arm64: Add support for hooks to handle undefined instructions arm64: kernel: Explicitly add include in traps.c ... Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Conflicts: arch/arm64/kernel/Makefile net/netfilter/xt_qtaguid.c
2015-02-11arm64: Fix up /proc/cpuinfoMark Rutland
commit 44b82b7700d05a52cd983799d3ecde1a976b3bed upstream. Commit d7a49086f263164a (arm64: cpuinfo: print info for all CPUs) attempted to clean up /proc/cpuinfo, but due to concerns regarding further changes was reverted in commit 5e39977edf6500fd (Revert "arm64: cpuinfo: print info for all CPUs"). There are two major issues with the arm64 /proc/cpuinfo format currently: * The "Features" line describes (only) the 64-bit hwcaps, which is problematic for some 32-bit applications which attempt to parse it. As the same names are used for analogous ISA features (e.g. aes) despite these generally being architecturally unrelated, it is not possible to simply append the 64-bit and 32-bit hwcaps in a manner that might not be misleading to some applications. Various potential solutions have appeared in vendor kernels. Typically the format of the Features line varies depending on whether the task is 32-bit. * Information is only printed regarding a single CPU. This does not match the ARM format, and does not provide sufficient information in big.LITTLE systems where CPUs are heterogeneous. The CPU information printed is queried from the current CPU's registers, which is racy w.r.t. cross-cpu migration. This patch attempts to solve these issues. The following changes are made: * When a task with a LINUX32 personality attempts to read /proc/cpuinfo, the "Features" line contains the decoded 32-bit hwcaps, as with the arm port. Otherwise, the decoded 64-bit hwcaps are shown. This aligns with the behaviour of COMPAT_UTS_MACHINE and COMPAT_ELF_PLATFORM. In the absense of compat support, the Features line is empty. The set of hwcaps injected into a task's auxval are unaffected. * Properties are printed per-cpu, as with the ARM port. The per-cpu information is queried from pre-recorded cpu information (as used by the sanity checks). * As with the previous attempt at fixing up /proc/cpuinfo, the hardware field is removed. The only users so far are 32-bit applications tied to particular boards, so no portable applications should be affected, and this should prevent future tying to particular boards. The following differences remain: * No model_name is printed, as this cannot be queried from the hardware and cannot be provided in a stable fashion. Use of the CPU {implementor,variant,part,revision} fields is sufficient to identify a CPU and is portable across arm and arm64. * The following system-wide properties are not provided, as they are not possible to provide generally. Programs relying on these are already tied to particular (32-bit only) boards: - Hardware - Revision - Serial No software has yet been identified for which these remaining differences are problematic. Cc: Greg Hackmann <ghackmann@google.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Serban Constantinescu <serban.constantinescu@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: cross-distro@lists.linaro.org Cc: linux-api@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-02-05arm64: Emulate SETEND for AArch32 tasksSuzuki K. Poulose
Emulate deprecated 'setend' instruction for AArch32 bit tasks. setend [le/be] - Sets the endianness of EL0 On systems with CPUs which support mixed endian at EL0, the hardware support for the instruction can be enabled by setting the SCTLR_EL1.SED bit. Like the other emulated instructions it is controlled by an entry in /proc/sys/abi/. For more information see : Documentation/arm64/legacy_instructions.txt The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which will be reflected in the PSTATE.E in AArch32 context. This patch also restores the native endianness for the execution of signal handlers, since the process could have changed the endianness. Note: All CPUs on the system must have mixed endian support at EL0. Once the handler is registered, hotplugging a CPU which doesn't support mixed endian, could lead to unexpected results/behavior in applications. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Change-Id: I5993237889a049a23f6c234daa130d3a740d5525
2015-02-05arm64: Consolidate hotplug notifier for instruction emulationSuzuki K. Poulose
As of now each insn_emulation has a cpu hotplug notifier that enables/disables the CPU feature bit for the functionality. This patch re-arranges the code, such that there is only one notifier that runs through the list of registered emulation hooks and runs their corresponding set_hw_mode. We do nothing when a CPU is dying as we will set the appropriate bits as it comes back online based on the state of the hooks. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> [catalin.marinas@arm.com: fix pr_warn compilation error] [catalin.marinas@arm.com: remove unnecessary "insn" check] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-02-05arm64: Track system support for mixed endian EL0Suzuki K. Poulose
This patch keeps track of the mixed endian EL0 support across the system and provides helper functions to export it. The status is a boolean indicating whether all the CPUs on the system supports mixed endian at EL0. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Change-Id: Ib2ff964718db4c9175a0ffbf25c7dbb67e2a037a
2015-02-05arm64: cpuinfo: record cpu system register valuesMark Rutland
Several kernel subsystems need to know details about CPU system register values, sometimes for CPUs other than that they are executing on. Rather than hard-coding system register accesses and cross-calls for these cases, this patch adds logic to record various system register values at boot-time. This may be used for feature reporting, firmware bug detection, etc. Separate hooks are added for the boot and hotplug paths to enable one-time intialisation and cold/warm boot value mismatch detection in later patches. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Change-Id: Ie12f014c8ec1738913cb3d04eab4f5293ce8c856
2015-02-05arm64: add MIDR_EL1 field accessorsMark Rutland
The MIDR_EL1 register is composed of a number of bitfields, and uses of the fields has so far involved open-coding of the shifts and masks required. This patch adds shifts and masks for each of the MIDR_EL1 subfields, and also provides accessors built atop of these. Existing uses within cputype.h are updated to use these accessors. The read_cpuid_part_number macro is modified to return the extracted bitfield rather than returning the value in-place with all other fields (including revision) masked out, to better match the other accessors. As the value is only used in comparison with the *_CPU_PART_* macros which are similarly updated, and these values are never exposed to userspace, this change should not affect any functionality. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Change-Id: Ic71c87c653b655242651ccda40a81137fffde1d9
2015-02-05arm64: Emulate CP15 Barrier instructionsPunit Agrawal
The CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB instructions respectively. Some implementations may provide the ability to disable the CP15 barriers by disabling the CP15BEN bit in SCTLR_EL1. If not enabled, the encodings for these instructions become undefined. To support legacy software using these instructions, this patch register hooks to - * emulate CP15 barriers and warn the user about their use * toggle CP15BEN in SCTLR_EL1 Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Change-Id: I16e70c2505489a4d88c898759256df20d2f4c21d
2015-02-05arm64: barriers: add dmb barrierWill Deacon
Commit 8adbf57fc429 ("irqchip: gic: use dmb ishst instead of dsb when raising a softirq") added an explicit dmb(...) call to the GIC driver. This patch adds a simple dmb() macro to arm64, which expands to a DMB SY instruction. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-02-05arm64: Port SWP/SWPB emulation support from armPunit Agrawal
The SWP instruction was deprecated in the ARMv6 architecture. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. With ARMv8, the option to enable these instructions through System Control Register was dropped as well. To support legacy applications using these instructions, port the emulation of the SWP and SWPB instructions from the arm port to arm64. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Change-Id: I5ef56cac623d58a210e67c705aa5f5f63e784c0a
2015-02-05arm64: Add AArch32 instruction set condition code checksPunit Agrawal
Port support for AArch32 instruction condition code checking from arm to arm64. Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Change-Id: I45f9665346da3f8692c289bc3088d43708780b1c
2015-02-05arm64: Add support for hooks to handle undefined instructionsPunit Agrawal
Add support to register hooks for undefined instructions. The handlers will be called when the undefined instruction and the processor state (as contained in pstate) match criteria used at registration. Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Change-Id: Id63a0ddec8b6af448d9512b259e6e7edaee7abff
2015-02-05Revert "arm64: copy conditional instruction tests from arm"Daniel Rosenberg
This reverts commit 3680c87e7358d8b5539b4156dd93326454b4041d.
2015-02-05Revert "arm64: ptrace: add is_wide_instruction() macro"Daniel Rosenberg
This reverts commit c4af5493328d3ec7aa43c830f48fab6e920417e9.
2015-02-05Revert "arm64: add undefined instruction handler hooks"Daniel Rosenberg
This reverts commit b302f74ce2618e3f2377676ec289f50c1e8fefb6.
2015-01-28Merge remote-tracking branch 'lsk/v3.14/topic/aosp' into ↵Mark Brown
linux-linaro-lsk-v3.14-android Conflicts: arch/arm64/kernel/Makefile
2015-01-24Merge branch 'linux-linaro-lsk-v3.14' into linux-linaro-lsk-v3.14-androidlsk-v3.14-android-15.01Mark Brown
2015-01-23Merge remote-tracking branch 'lsk/v3.14/topic/arm64-efi' into ↵lsk-v3.14-15.01Mark Brown
linux-linaro-lsk-v3.14 Conflicts: arch/arm64/kernel/Makefile drivers/firmware/efi/efi-stub-helper.c
2015-01-20Merge branch 'linaro-android-3.14-fwd-port' into linaro-android-3.14-lskAmit Pundir
Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Conflicts: arch/arm/include/uapi/asm/unistd.h arch/arm/kernel/calls.S arch/arm64/include/asm/unistd.h arch/arm64/include/asm/unistd32.h arch/arm64/kernel/fpsimd.c arch/x86/syscalls/syscall_32.tbl arch/x86/syscalls/syscall_64.tbl drivers/cpufreq/cpufreq_interactive.c drivers/cpufreq/cpufreq_stats.c drivers/usb/gadget/u_ether.c include/linux/cgroup.h include/linux/wlan_plat.h include/net/fib_rules.h include/net/route.h include/uapi/asm-generic/unistd.h include/uapi/linux/ipv6.h kernel/cgroup.c kernel/power/process.c kernel/power/suspend.c mm/memcontrol.c mm/util.c net/ipv4/route.c net/ipv6/route.c net/ipv6/sysctl_net_ipv6.c
2015-01-19Merge remote-tracking branch 'lsk/v3.14/topic/aosp' into ↵Mark Brown
linux-linaro-lsk-v3.14-android Conflicts: arch/arm64/Kconfig arch/arm64/crypto/Makefile arch/arm64/crypto/aes-glue.c arch/arm64/include/asm/ptrace.h arch/arm64/include/asm/thread_info.h arch/arm64/include/asm/unistd32.h arch/arm64/kernel/Makefile arch/arm64/kernel/entry.S arch/arm64/kernel/ptrace.c drivers/base/cpu.c drivers/of/fdt.c fs/pstore/inode.c kernel/futex.c
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