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author | Suzuki K. Poulose <suzuki.poulose@arm.com> | 2015-07-22 11:38:14 +0100 |
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committer | David Brown <david.brown@linaro.org> | 2015-12-03 16:53:53 -0800 |
commit | e7aa2ecf27faab420d6dd3b173419f6fd7bf85be (patch) | |
tree | 342115645dd99b2d08ebbd670325aa9c8d588cbe /net/sysctl_net.c | |
parent | b690b7b8ea781d8459160af548a05522438962ec (diff) |
arm64: Generalise msr_s/mrs_s operations
commit 9ded63aaf83eba76e1a54ac02581c2badc497f1a upstream.
The system register encoding generated by sys_reg() works only
for MRS/MSR(Register) operations, as we hardcode Bit20 to 1 in
mrs_s/msr_s mask. This makes it unusable for generating instructions
accessing registers with Op0 < 2(e.g, PSTATE.x with Op0=0).
As per ARMv8 ARM, (Ref: ARMv8 ARM, Section: "System instruction class
encoding overview", C5.2, version:ARM DDI 0487A.f), the instruction
encoding reserves bits [20-19] for Op0.
This patch generalises the sys_reg, mrs_s and msr_s macros, so that
we could use them to access any of the supported system register.
Cc: James Morse <james.morse@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: David Brown <david.brown@linaro.org>
Diffstat (limited to 'net/sysctl_net.c')
0 files changed, 0 insertions, 0 deletions