diff options
author | Gary S. Robertson <gary.robertson@linaro.org> | 2015-04-21 08:15:06 -0500 |
---|---|---|
committer | Gary S. Robertson <gary.robertson@linaro.org> | 2015-04-21 08:15:06 -0500 |
commit | 7f54cddfc767c29bc030a9f512c1d5e8e33f337d (patch) | |
tree | e69a57ebce834150e4d28b230eea93ecbb6895de /drivers/cpufreq/exynos4210-cpufreq.c | |
parent | 93d431e2909e0ec03127b861f4865cde89d84520 (diff) | |
parent | 494db70db363f41da78ee5f07096cf04068d7a3e (diff) |
Merge branch 'linux-linaro-lng-v3.18' into linux-linaro-lng-v3.18-rtlinux-lng-preempt-rt-3.18.11-2015.05linux-lng-preempt-rt-3.18.11-2015.04
Conflicts:
include/linux/interrupt.h
kernel/irq/manage.c
Diffstat (limited to 'drivers/cpufreq/exynos4210-cpufreq.c')
-rw-r--r-- | drivers/cpufreq/exynos4210-cpufreq.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index 843ec824fd91..834fb3775d48 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -63,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index) tmp = apll_freq_4210[div_index].clk_div_cpu0; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); do { - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU); } while (tmp & 0x1111111); /* Change Divider - CPU1 */ tmp = apll_freq_4210[div_index].clk_div_cpu1; - __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); + writel_relaxed(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); do { - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); } while (tmp & 0x11); } @@ -88,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index) clk_set_parent(moutcore, mout_mpll); do { - tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) + tmp = (readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); tmp &= 0x7; } while (tmp != 0x2); @@ -99,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index) clk_set_parent(moutcore, mout_apll); do { - tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); + tmp = readl_relaxed(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } |