diff options
26 files changed, 153 insertions, 113 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index d14a7bb60..9a6f6cbee 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -234,7 +234,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index dc692edc1..237dcfef1 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -288,7 +288,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index f048badf9..abfa12463 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -203,7 +203,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index aa014d09d..08f178de1 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -249,7 +249,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 67e706b3c..2c0c86942 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -240,7 +240,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c index 9da7443f3..1c6fa4ae8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/timer.c +++ b/arch/arm/cpu/arm926ejs/davinci/timer.c @@ -40,6 +40,8 @@ #include <common.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + struct davinci_timer { u_int32_t pid12; u_int32_t emumgt; @@ -57,11 +59,9 @@ struct davinci_timer { static struct davinci_timer * const timer = (struct davinci_timer *)CONFIG_SYS_TIMERBASE; -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) -#define TIM_CLK_DIV 16 +#define TIMER_LOAD_VAL 0xffffffff -static ulong timestamp; -static ulong lastinc; +#define TIM_CLK_DIV 16 int timer_init(void) { @@ -71,72 +71,51 @@ int timer_init(void) writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr); writel(0x0, &timer->tim34); writel(TIMER_LOAD_VAL, &timer->prd34); - lastinc = 0; - timestamp = 0; writel(2 << 22, &timer->tcr); + gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV; + gd->timer_reset_value = 0; return(0); } void reset_timer(void) { - writel(0x0, &timer->tcr); - writel(0x0, &timer->tim34); - lastinc = 0; - timestamp = 0; - writel(2 << 22, &timer->tcr); + gd->timer_reset_value = get_ticks(); } -static ulong get_timer_raw(void) +/* + * Get the current 64 bit timer tick count + */ +unsigned long long get_ticks(void) { - ulong now = readl(&timer->tim34); - - if (now >= lastinc) { - /* normal mode */ - timestamp += now - lastinc; - } else { - /* overflow ... */ - timestamp += now + TIMER_LOAD_VAL - lastinc; - } - lastinc = now; - return timestamp; + unsigned long now = readl(&timer->tim34); + + /* increment tbu if tbl has rolled over */ + if (now < gd->tbl) + gd->tbu++; + gd->tbl = now; + + return (((unsigned long long)gd->tbu) << 32) | gd->tbl; } ulong get_timer(ulong base) { - return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); -} + unsigned long long timer_diff; -void set_timer(ulong t) -{ - timestamp = t; + timer_diff = get_ticks() - gd->timer_reset_value; + + return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base; } void __udelay(unsigned long usec) { - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= (1000 * TIM_CLK_DIV); - - endtime = get_timer_raw() + tmo; + unsigned long long endtime; - do { - ulong now = get_timer_raw(); - diff = endtime - now; - } while (diff >= 0); -} + endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL; + endtime += get_ticks(); -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return(get_timer(0)); + while (get_ticks() < endtime) + ; } /* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 6c49c830f..55192521b 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -239,7 +239,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 4e75109f8..f9c947024 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -211,7 +211,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index cbbc612b5..d28e745b2 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -207,7 +207,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 6b8cf7ba2..9beebb1e7 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -35,8 +35,8 @@ #include <common.h> #include <asm/io.h> -static ulong timestamp; -static ulong lastinc; +DECLARE_GLOBAL_DATA_PTR; + static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; /* @@ -74,7 +74,7 @@ ulong get_timer(ulong base) void set_timer(ulong t) { - timestamp = t; + gd->tbl = t; } /* delay x useconds */ @@ -96,8 +96,8 @@ void __udelay(unsigned long usec) void reset_timer_masked(void) { /* reset time, capture current incrementer value time */ - lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ + gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + gd->tbl = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked(void) @@ -105,14 +105,14 @@ ulong get_timer_masked(void) /* current tick value */ ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - if (now >= lastinc) /* normal mode (non roll) */ + if (now >= gd->lastinc) /* normal mode (non roll) */ /* move stamp fordward with absoulte diff ticks */ - timestamp += (now - lastinc); + gd->tbl += (now - gd->lastinc); else /* we have rollover of incrementer */ - timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) - - lastinc) + now; - lastinc = now; - return timestamp; + gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) + - gd->lastinc) + now; + gd->lastinc = now; + return gd->tbl; } /* diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c index 2227576b7..30856372b 100644 --- a/arch/arm/cpu/armv7/omap3/emif4.c +++ b/arch/arm/cpu/armv7/omap3/emif4.c @@ -29,6 +29,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/emif4.h> +DECLARE_GLOBAL_DATA_PTR; extern omap3_sysinfo sysinfo; static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE; @@ -139,7 +140,6 @@ void do_emif4_init(void) */ int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; unsigned int size0 = 0, size1 = 0; size0 = get_sdr_cs_size(CS0); @@ -157,7 +157,6 @@ int dram_init(void) void dram_init_banksize (void) { - DECLARE_GLOBAL_DATA_PTR; unsigned int size0 = 0, size1 = 0; size0 = get_sdr_cs_size(CS0); diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index a4979ce61..2a7970b4d 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -37,6 +37,7 @@ #include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> +DECLARE_GLOBAL_DATA_PTR; extern omap3_sysinfo sysinfo; static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; @@ -172,7 +173,6 @@ void do_sdrc_init(u32 cs, u32 early) */ int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; unsigned int size0 = 0, size1 = 0; size0 = get_sdr_cs_size(CS0); @@ -194,7 +194,6 @@ int dram_init(void) void dram_init_banksize (void) { - DECLARE_GLOBAL_DATA_PTR; unsigned int size0 = 0, size1 = 0; size0 = get_sdr_cs_size(CS0); diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index c71ef6cf9..684f2d253 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -209,7 +209,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 87942cd7d..9f8c15b87 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -333,7 +333,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 499b6328a..32dfe8b5f 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -220,7 +220,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 0580adce1..fbd0def46 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -287,7 +287,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 50e3f21cf..9379af67b 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -192,7 +192,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index b34e94655..7c2db4f14 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -196,7 +196,7 @@ fixabs: mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ add r1, r10, r1 /* r1 <- address of symbol in table */ ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r9 /* r1 <- relocated sym addr */ + add r1, r1, r9 /* r1 <- relocated sym addr */ b fixnext fixrel: /* relative fix: increase location by offset */ diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c index 12b40a01e..8f5305ca1 100644 --- a/board/freescale/p1022ds/diu.c +++ b/board/freescale/p1022ds/diu.c @@ -32,6 +32,7 @@ #define PMUXCR_ELBCDIU_MASK 0xc0000000 #define PMUXCR_ELBCDIU_NOR16 0x80000000 +#define PMUXCR_ELBCDIU_DIU 0x40000000 /* * DIU Area Descriptor @@ -131,9 +132,8 @@ int platform_diu_init(unsigned int *xres, unsigned int *yres) px_brdcfg0 = in_8(lbc_lcs1_ba); out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); - /* Setting PMUXCR to switch to DVI from ELBC */ - clrsetbits_be32(&gur->pmuxcr, - PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16); + /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ + clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); pmuxcr = in_be32(&gur->pmuxcr); return fsl_diu_init(*xres, pixel_format, 0); @@ -161,7 +161,7 @@ static int set_mux_to_lbc(void) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* Switch the muxes only if they're currently set to DIU mode */ - if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) == + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != PMUXCR_ELBCDIU_NOR16) { /* * In DIU mode, the PIXIS can only be accessed indirectly @@ -216,8 +216,17 @@ void flash_write8(u8 value, void *addr) int sw = set_mux_to_lbc(); __raw_writeb(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + * set_mux_to_diu() includes a sync that will ensure the + * __raw_readb() completes before it switches the mux. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write16(u16 value, void *addr) @@ -225,8 +234,17 @@ void flash_write16(u16 value, void *addr) int sw = set_mux_to_lbc(); __raw_writew(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + * set_mux_to_diu() includes a sync that will ensure the + * __raw_readb() completes before it switches the mux. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write32(u32 value, void *addr) @@ -234,18 +252,47 @@ void flash_write32(u32 value, void *addr) int sw = set_mux_to_lbc(); __raw_writel(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + * set_mux_to_diu() includes a sync that will ensure the + * __raw_readb() completes before it switches the mux. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write64(u64 value, void *addr) { int sw = set_mux_to_lbc(); + uint32_t *p = addr; - /* There is no __raw_writeq(), so do the write manually */ - *(volatile u64 *)addr = value; - if (sw) + /* + * There is no __raw_writeq(), so do the write manually. We don't trust + * the compiler, so we use inline assembly. + */ + __asm__ __volatile__( + "stw%U0%X0 %2,%0;\n" + "stw%U1%X1 %3,%1;\n" + : "=m" (*p), "=m" (*(p + 1)) + : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value))); + + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. We + * read addr+4 because we just wrote to addr+4, so that's how we + * maintain execution order. set_mux_to_diu() includes a sync + * that will ensure the __raw_readb() completes before it + * switches the mux. + */ + __raw_readb(addr + 4); set_mux_to_diu(); + } } u8 flash_read8(void *addr) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a368fe60d..57cd4ee1f 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc) int ret = 0; u8 card_absent; - /* Enable cache snooping */ - if (cfg && !cfg->no_snoop) - esdhc_write32(®s->scr, 0x00000040); - /* Reset the entire host controller */ esdhc_write32(®s->sysctl, SYSCTL_RSTA); @@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000); + /* Enable cache snooping */ + if (cfg && !cfg->no_snoop) + esdhc_write32(®s->scr, 0x00000040); + esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 7cb99cbc0..c33e2786b 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -21,6 +21,7 @@ static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); + (void)in_be32(upm->mxmr); } static void fsl_upm_end_pattern(struct fsl_upm *upm) @@ -35,6 +36,7 @@ static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, void __iomem *io_addr, u32 mar) { out_be32(upm->mar, mar); + (void)in_be32(upm->mar); switch (width) { case 8: out_8(io_addr, 0x0); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9b5dd92fb..77908d1e1 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2010 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -292,13 +292,12 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ #ifndef CONFIG_TSEC_TBICR_SETTINGS -#define TBICR_SETTINGS ( \ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) -#else -#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS #endif /* CONFIG_TSEC_TBICR_SETTINGS */ /* Configure the TBI for SGMII operation */ @@ -311,7 +310,7 @@ static void tsec_configure_serdes(struct tsec_private *priv) tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, - TBICR_SETTINGS); + CONFIG_TSEC_TBICR_SETTINGS); } /* Discover which PHY is attached to the device, and configure it diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a21afb7ac..2dfee3d1b 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -437,14 +437,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - #endif /* CONFIG_TSEC_ENET */ /* diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index e1b1db16e..45214fa42 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -50,7 +50,7 @@ /*=======*/ #define DV_EVM #define CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_SYS_USE_NOR +#define CONFIG_SYS_USE_NAND #define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ @@ -78,6 +78,7 @@ #define CONFIG_STACKSIZE (256*1024) /* regular stack */ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ + #define DDR_8BANKS /* 8-bank DDR2 (256MB) */ /*====================*/ /* Serial Driver info */ @@ -228,11 +229,13 @@ #define CONFIG_PREBOOT "usb start" #endif #endif -/*=======================*/ -/* KGDB support (if any) */ -/*=======================*/ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif + +#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index e0a1fa406..a74766dce 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -375,6 +375,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_ETHPRIME "eTSEC2" +/* + * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force + * 1000mbps SGMII link + */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 42d1f6980..a051913ff 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -345,6 +345,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_ETHPRIME "eTSEC2" +/* + * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force + * 1000mbps SGMII link + */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |