vixl.git - mirror of https://github.com/Linaro/vixl

Age	Commit message (Expand)	Author
2021-02-10	Empty commit to test CI. DO NOT MERGE.dev/do-not-merge	Jacob Bramley
2021-02-09	Further tighten AArch32 push/pop selection.	Jacob Bramley
2021-02-09	Use IsPowerOf2.	Jacob Bramley
2021-02-09	Optimize GetFirstAvailableRegister() using CountTrailingZeros().	Peter Collingbourne
2021-02-09	Fix invalid encoding for single register push/pop.	Peter Collingbourne
2021-02-09	Fix clang build.	Peter Collingbourne
2021-02-09	Redirect repository links to GitHub.	Jacob Bramley
2020-12-31	Fix encoding for integer PAC instructions with zero contextmaster	Pierre Langlois
2020-12-02	Skip top 64-bit write in movi if identical.	Pierre Langlois
2020-11-24	Fix ldapr test	Martyn Capewell
2020-11-20	Add missing aliases for mov instruction with immediate	mateusz.kalinowski
2020-11-12	[sve] Fix while simulation corner case	Martyn Capewell
2020-11-10	Remove "dummy" from test and tools	Martyn Capewell
2020-11-10	Remove use of "dummy"	Martyn Capewell
2020-11-05	Make the stack size configurable.	Jacob Bramley
2020-11-05	Fix FPRoundInt's handling of INT64_MAX.	Jacob Bramley
2020-10-30	Don't simulate invalid logical immediate instructions	Martyn Capewell
2020-10-20	Fix undefined behaviour in Halve	Martyn Capewell
2020-10-15	Simplify the command-line disassembly example UI.	Jacob Bramley
2020-10-14	Add a command-line disassembly example.	Jacob Bramley
2020-10-07	Add email address for bug reporting	Martyn Capewell
2020-09-23	Define values for unallocated prefetch modes	Martyn Capewell
2020-09-10	Fix lint.py error regex.	Jacob Bramley
2020-08-14	Optimise single handler tables in the decoder.	Martyn Capewell
2020-08-13	[sve] Disallow dup with shift on byte-sized lanes	Martyn Capewell
2020-08-06	Fix infinite loops in some native tests.	Jacob Bramley
2020-08-03	Remove undefined behaviour in add/sub immediate	Martyn Capewell
2020-07-29	Revert optimisation for add/sub immediates	Martyn Capewell
2020-07-24	Fix initialisation order for ID register fields.	Jacob Bramley
2020-07-23	Fix add/sub immediate for min-int case	Martyn Capewell
2020-07-16	Add missing aliases for SVE 0.0 moves.	Jacob Bramley
2020-07-16	Fix and enable CanTakeSVEMovprfx.	Jacob Bramley
2020-07-16	Support more than 64 CPU features.	Jacob Bramley
2020-07-16	Fix CPUFeature iterator behaviour.	Jacob Bramley
2020-07-16	Add an example that dumps CPU feature information.	Jacob Bramley
2020-07-16	Add support for AT_HWCAP2.	Jacob Bramley
2020-07-16	Add CPUFeatures up to Armv8.6.	Jacob Bramley
2020-07-13	Emit pairs of add/sub for larger immediates	Martyn Capewell
2020-07-13	Use segments in SVE indexed fmul simulation	Martyn Capewell
2020-07-06	Fix numerous issues related to CAS* instructions.	Jacob Bramley
2020-07-06	Make assembler more strict about SVE prefetch arguments	Martyn Capewell
2020-07-03	Use PgLow8 rather than Pg<12, 10>.	Jacob Bramley
2020-07-03	Always assert that 'pg' does not have a lane size.	Jacob Bramley
2020-07-02	Disallow x31/xzr for SVE prefetch scalar offset register	Martyn Capewell
2020-07-02	Fix simulation of FCMNE.	Jacob Bramley
2020-07-02	Require an immediate (0.0) for compare-with-zero instructions.	Jacob Bramley
2020-07-02	Prefer to use 'rd' as a scratch.	Jacob Bramley
2020-07-02	Fix CPURegister::GetArchitecturalName().	Jacob Bramley
2020-07-02	Fix simulation of FTSMUL.	Jacob Bramley
2020-07-02	Fix the `sve_fmla_fmls` test.	Jacob Bramley