Simulator branch interception (#75)dev/vixl-interception

* Add maybe_unused to runtime call arguments

Currently runtime calls cannot be done if the function to be called
has no parameters because the compiler will give a
"unused-but-set-parameter" warning which is treated as an error. Fix
this by always using the 'arguments' parameter.

Change-Id: I9f4b75ea8b6ae6fe03be33cefa45fa99f5485b7a

* Add branch interception to VIXL simulator

Simulated AARCH64 code, that is not written in using the
macroassembler, can branch (change the simulated PC) to arbitrary
function addresses. This works fine if that function is AARCH64
however if that function is a native (x86_64) C++ function then an
error (likely SIGILL) will be thrown. To handle this case we need to
"intercept" branches to these native (x86_64) C++ functions and
instead either perform a runtime call to the function or provide a
callback to manually handle the particular case.

Add a mechanism to intercept functions as they are branched to
within the VIXL simulator. This means that whenever a function X is
branched to (e.g: bl X) instead, if provided, a callback function Y
is called. If no callback is provided for the interception to
function X then a runtime call will be done on function X.

Branch interception objects consisting of the function to intercept:
X, and an optional callback function Y are stored within the
simulator and checked every unconditional branch to register.

Change-Id: I874a6fa5b8f0581fe930a7a98f762031bdb2f591

4 files changed, 311 insertions, 1 deletions

diff --git a/examples/aarch64/simulator_interception.cc b/examples/aarch64/simulator_interception.cc
new file mode 100644
index 00000000..b7d88c11
--- /dev/null
+++ b/examples/aarch64/simulator_interception.cc
@@ -0,0 +1,150 @@
+// Copyright 2023, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "examples.h"
+
+#include "aarch64/disasm-aarch64.h"
+#include "aarch64/macro-assembler-aarch64.h"
+#include "aarch64/simulator-aarch64.h"
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+#define __ masm->
+
+enum Result {
+  FAILURE,
+  SUCCESS
+};
+
+// This will be called via a runtime call.
+extern "C" int example_1() {
+  return SUCCESS;
+}
+
+// This will never be called, instead it will be intercepted and 'callback'
+// will be called.
+uint32_t example_2() {
+  return FAILURE;
+}
+
+uint32_t example_3() {
+  return FAILURE;
+}
+
+// This will be called instead of example_2.
+uint32_t callback(uint64_t original_target) {
+  USE(original_target);
+  return SUCCESS;
+}
+
+void GenerateInterceptionExamples(MacroAssembler* masm) {
+  // Preserve lr, since the calls will overwrite it.
+  __ Push(xzr, lr);
+
+  // example_1 will be intercepted and called through a runtime call.
+  __ Mov(x16, reinterpret_cast<uint64_t>(example_1));
+  __ Blr(x16);
+  __ Mov(w1, w0);
+
+  // example_2 will be intercepted and callback will be called instead.
+  __ Mov(x16, reinterpret_cast<uint64_t>(example_2));
+  __ Blr(x16);
+  __ Mov(w2, w0);
+
+  __ Mov(x16, reinterpret_cast<uint64_t>(example_3));
+  __ Blr(x16);
+  __ Mov(w3, w0);
+
+  // Restore lr and return.
+  __ Pop(lr, xzr);
+  __ Ret();
+}
+
+#ifndef TEST_EXAMPLES
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+
+int main(void) {
+  MacroAssembler masm;
+
+  // Generate the code for the example function.
+  Label call_simulator_interception;
+  masm.Bind(&call_simulator_interception);
+  GenerateInterceptionExamples(&masm);
+  masm.FinalizeCode();
+
+  Instruction* start =
+      masm.GetLabelAddress<Instruction*>(&call_simulator_interception);
+
+  // Disassemble the generated code.
+  PrintDisassembler disassembler(stdout);
+  disassembler.DisassembleBuffer(start, masm.GetSizeOfCodeGenerated());
+
+  Decoder decoder;
+  Simulator simulator(&decoder);
+
+  // Register interceptions to the branches, example_1 will be called via a
+  // runtime call and callback will be called instead of example_2.
+  simulator.RegisterBranchInterception(example_1);
+  simulator.RegisterBranchInterception(example_2, callback);
+
+  // Lambda callbacks can be used to arbitrarily modify the simulator.
+  simulator.RegisterBranchInterception(example_3,
+                                       [&simulator](uint64_t original_target) {
+    USE(original_target);
+    simulator.WriteWRegister(0, SUCCESS);
+  });
+
+  simulator.RunFrom(start);
+
+  uint32_t result_1 = simulator.ReadWRegister(1);
+  if (result_1 == SUCCESS) {
+    printf("SUCCESS: example_1 was called via a runtime call.\n");
+  } else {
+    printf("ERROR: example_1 was not called.\n");
+  }
+
+  uint32_t result_2 = simulator.ReadWRegister(2);
+  if (result_2 == SUCCESS) {
+    printf("SUCCESS: callback was called instead of example_2.\n");
+  } else {
+    printf("ERROR: example_2 was called incorrectly.\n");
+  }
+
+  uint32_t result_3 = simulator.ReadWRegister(0);
+  if (result_3 == SUCCESS) {
+    printf("SUCCESS: Lambda callback called instead of example_3.\n");
+  } else {
+    printf("ERROR: example_3 was called instead of the lambda.\n");
+  }
+
+  return 0;
+}
+#else
+// TODO: Support running natively.
+int main(void) { return 0; }
+#endif  // VIXL_INCLUDE_SIMULATOR_AARCH64
+#endif  // TEST_EXAMPLES
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc
index d183dc35..a7a2dbf3 100644
--- a/src/aarch64/simulator-aarch64.cc
+++ b/src/aarch64/simulator-aarch64.cc
@@ -533,6 +533,8 @@ void Simulator::ResetState() {
   // BTI state.
   btype_ = DefaultBType;
   next_btype_ = DefaultBType;
+
+  branch_interceptions_.clear();
 }
 
 void Simulator::SetVectorLengthInBits(unsigned vector_length) {
@@ -3613,6 +3615,7 @@ BType Simulator::GetBTypeFromInstruction(const Instruction* instr) const {
 void Simulator::VisitUnconditionalBranchToRegister(const Instruction* instr) {
   bool authenticate = false;
   bool link = false;
+  bool ret = false;
   uint64_t addr = ReadXRegister(instr->GetRn());
   uint64_t context = 0;
 
@@ -3621,7 +3624,6 @@ void Simulator::VisitUnconditionalBranchToRegister(const Instruction* instr) {
       link = true;
       VIXL_FALLTHROUGH();
     case BR:
-    case RET:
       break;
 
     case BLRAAZ:
@@ -3648,6 +3650,9 @@ void Simulator::VisitUnconditionalBranchToRegister(const Instruction* instr) {
       authenticate = true;
       addr = ReadXRegister(kLinkRegCode);
       context = ReadXRegister(31, Reg31IsStackPointer);
+      VIXL_FALLTHROUGH();
+    case RET:
+      ret = true;
       break;
     default:
       VIXL_UNREACHABLE();
@@ -3667,6 +3672,22 @@ void Simulator::VisitUnconditionalBranchToRegister(const Instruction* instr) {
     }
   }
 
+  if (!ret) {
+    // Check for interceptions to the target address, if one is found, call it.
+    auto search = branch_interceptions_.find(addr);
+    if (search != branch_interceptions_.end()) {
+      BranchInterceptionAbstract* interception = search->second.get();
+
+      // Instead of writing the address of the function to the PC, call the
+      // function's interception directly. We change the address that will be
+      // branched to so that afterwards we continue execution from
+      // the address in the LR. Note: the interception may modify the LR so
+      // store it before calling the interception.
+      addr = ReadRegister<uint64_t>(kLinkRegCode);
+      (*interception)(this);
+    }
+  }
+
   WritePc(Instruction::Cast(addr));
   WriteNextBType(GetBTypeFromInstruction(instr));
 }
diff --git a/src/aarch64/simulator-aarch64.h b/src/aarch64/simulator-aarch64.h
index 1fdbb6f6..9a686ad9 100644
--- a/src/aarch64/simulator-aarch64.h
+++ b/src/aarch64/simulator-aarch64.h
@@ -2656,6 +2656,7 @@ class Simulator : public DecoderVisitor {
   R DoRuntimeCall(R (*function)(P...),
                   std::tuple<P...> arguments,
                   local_index_sequence<I...>) {
+    USE(arguments);
     return function(std::get<I>(arguments)...);
   }
 
@@ -2786,6 +2787,27 @@ class Simulator : public DecoderVisitor {
 
   SimPRegister& GetPTrue() { return pregister_all_true_; }
 
+  // A callback function, called when a function has been intercepted if a
+  // BranchInterception entry exists in branch_interceptions. The address of
+  // the intercepted function is passed to the callback. For usage see
+  // BranchInterception.
+  using InterceptionCallback = std::function<void(uint64_t)>;
+
+  // Register a new BranchInterception object. If 'function' is branched to
+  // (e.g: "bl function") in the future; instead, if provided, 'callback' will
+  // be called otherwise a runtime call will be performed on 'function'.
+  //
+  // For example: this can be used to always perform runtime calls on
+  // non-AArch64 functions without using the macroassembler.
+  template <typename R, typename... P>
+  void RegisterBranchInterception(R (*function)(P...),
+                                  InterceptionCallback callback = nullptr) {
+    uintptr_t addr = reinterpret_cast<uintptr_t>(function);
+    std::unique_ptr<BranchInterceptionAbstract> intercept = std::make_unique<
+        BranchInterception<R, P...>>(function, callback);
+    branch_interceptions_.insert(std::make_pair(addr, std::move(intercept)));
+  }
+
  protected:
   const char* clr_normal;
   const char* clr_flag_name;
@@ -4667,6 +4689,41 @@ class Simulator : public DecoderVisitor {
   // Simulate a runtime call.
   void DoRuntimeCall(const Instruction* instr);
 
+  // A pure virtual struct that allows the templated BranchInterception struct
+  // to be stored. For more information see BranchInterception.
+  struct BranchInterceptionAbstract {
+    virtual ~BranchInterceptionAbstract() {};
+    // Call the callback_ if one exists, otherwise do a RuntimeCall.
+    virtual void operator()(Simulator* simulator) const = 0;
+  };
+
+  // An entry denoting a function to intercept when branched to during
+  // simulator execution. When a function is intercepted the callback will be
+  // called if one exists otherwise the function will be passed to
+  // RuntimeCall.
+  template <typename R, typename... P>
+  struct BranchInterception : public BranchInterceptionAbstract {
+    BranchInterception(R (*function)(P...),
+                       InterceptionCallback callback = nullptr)
+        : function_(function), callback_(callback) {}
+
+    void operator()(Simulator* simulator) const VIXL_OVERRIDE {
+      if (callback_ == nullptr) {
+        Simulator::RuntimeCallStructHelper<R, P...>::Wrapper(simulator,
+            reinterpret_cast<uint64_t>(function_));
+      } else {
+        callback_(reinterpret_cast<uint64_t>(function_));
+      }
+    }
+
+  private:
+    // Pointer to the function that will be intercepted.
+    R (*function_)(P...);
+
+    // Function to be called instead of function_
+    InterceptionCallback callback_;
+  };
+
   // Processor state ---------------------------------------
 
   // Simulated monitors for exclusive access instructions.
@@ -4867,6 +4924,12 @@ class Simulator : public DecoderVisitor {
 
   // A configurable size of SVE vector registers.
   unsigned vector_length_;
+
+  // Store a map of addresses to be intercepted and their corresponding branch
+  // interception object, see 'BranchInterception'.
+  std::unordered_map<uintptr_t,
+                     std::unique_ptr<BranchInterceptionAbstract>>
+      branch_interceptions_;
 };
 
 #if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 4ca1a56e..f3408c84 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -13242,6 +13242,8 @@ double runtime_call_two_arguments_on_stack(int64_t arg1 __attribute__((unused)),
 
 void runtime_call_store_at_address(int64_t* address) { *address = 0xf00d; }
 
+int32_t runtime_call_no_args() { return 1; }
+
 enum RuntimeCallTestEnum { Enum0 };
 
 RuntimeCallTestEnum runtime_call_enum(RuntimeCallTestEnum e) { return e; }
@@ -13362,6 +13364,10 @@ TEST(runtime_calls) {
   __ Mov(x0, reinterpret_cast<uint64_t>(&value));
   __ CallRuntime(runtime_call_store_at_address);
 
+  __ Mov(w0, 0);
+  __ CallRuntime(runtime_call_no_args);
+  __ Mov(w25, w0);
+
   END();
 
 #if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) || \
@@ -13377,9 +13383,79 @@ TEST(runtime_calls) {
     ASSERT_EQUAL_64(0, x22);
     ASSERT_EQUAL_32(124, w23);
     ASSERT_EQUAL_64(0, x24);
+    ASSERT_EQUAL_32(1, w25);
   }
 #endif  // #if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) || ...
 }
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+void void_func() {}
+uint32_t uint32_func() { return 2; }
+void void_param_func(uint32_t x) { USE(x); }
+uint32_t uint32_param_func(uint32_t x) { return ++x; }
+
+void void_placeholder() {}
+uint32_t uint32_placeholder() { return 4; }
+void void_param_placeholder(uint32_t x) { USE(x); }
+uint32_t uint32_param_placeholder(uint32_t x) { return ++x; }
+
+#define DO_TEST_BRANCH_INTERCEPTION(func)         \
+  __ Mov(x16, reinterpret_cast<uint64_t>(func));   \
+  __ Blr(x16);
+
+TEST(branch_interception) {
+  SETUP();
+  START();
+
+  // Test default branch interception, i.e: do a runtime call to the function.
+  DO_TEST_BRANCH_INTERCEPTION(void_func);
+  DO_TEST_BRANCH_INTERCEPTION(uint32_func);
+  __ Mov(w20, w0);
+  DO_TEST_BRANCH_INTERCEPTION(void_param_func);
+  __ Mov(w0, 2);
+  DO_TEST_BRANCH_INTERCEPTION(uint32_param_func);
+  __ Mov(w21, w0);
+
+  // Test interceptions with callbacks.
+  DO_TEST_BRANCH_INTERCEPTION(void_placeholder);
+  __ Mov(w22, w0);
+  DO_TEST_BRANCH_INTERCEPTION(uint32_placeholder);
+  __ Mov(w23, w0);
+  __ Mov(w0, 4);
+  DO_TEST_BRANCH_INTERCEPTION(uint32_placeholder);
+  __ Mov(w24, w0);
+  DO_TEST_BRANCH_INTERCEPTION(uint32_placeholder);
+  __ Mov(w25, w0);
+
+  END();
+
+  simulator.RegisterBranchInterception(void_func);
+  simulator.RegisterBranchInterception(uint32_func);
+  simulator.RegisterBranchInterception(void_param_func);
+  simulator.RegisterBranchInterception(uint32_param_func);
+
+  auto callback = [&simulator](uint64_t original_target) {
+    USE(original_target);
+    simulator.WriteWRegister(0, 1);
+  };
+
+  simulator.RegisterBranchInterception(void_placeholder, callback);
+  simulator.RegisterBranchInterception(uint32_placeholder, callback);
+  simulator.RegisterBranchInterception(void_param_placeholder, callback);
+  simulator.RegisterBranchInterception(uint32_param_placeholder, callback);
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_32(2, w20);
+    ASSERT_EQUAL_32(3, w21);
+    ASSERT_EQUAL_32(1, w22);
+    ASSERT_EQUAL_32(1, w23);
+    ASSERT_EQUAL_32(1, w24);
+    ASSERT_EQUAL_32(1, w25);
+  }
+}
+#endif  // #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
 #endif  // #ifdef VIXL_HAS_MACROASSEMBLER_RUNTIME_CALL_SUPPORT