diff options
Diffstat (limited to 'edk2/ArmPlatformPkg/ArmVExpressPkg/Library')
6 files changed, 380 insertions, 124 deletions
diff --git a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S index f09d2cf1e..d865d6701 100644 --- a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S +++ b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S @@ -74,6 +74,23 @@ ASM_PFX(ArmPlatformSecBootMemoryInit): **/ smc_init: + // + // Disable loop buffer for A15 + // + MRC p15, 0, r2, c0, c0, 0 + MOV r1, r2, lsr #4 + LDR r0, =0xFFF + AND r1, r1, r0 + LDR r0, =0xC0F // See if A15 + CMP r1, r0 + BNE smc_init2 // Go if not + + MRC p15, 0, r1, c1, c0, 1 // Read Aux Ctrl Reg + ORR r1, r1, #(1 << 1) // Set Bit 1 + MCR p15, 0, r1, c1, c0, 1 // and write it back + +smc_init2: + LDR r0, = ARM_VE_SMC_CTRL_BASE LDR r2, = ARM_VE_SMB_PERIPH_BASE @@ -141,6 +158,13 @@ smc_init: LDR r1, = 0x03C00000 STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + // Set refresh period + LDR r1, = 0x1 + STR r1, [r0, #0x20] + + LDR r1, = 0x1 + STR r1, [r0, #0x24] + // page mode setup for VRAM LDR r0, = 0x00FFFFFC ADD r0, r0, r2 @@ -465,6 +489,15 @@ waitloop_14: LDR r3, =0 STR r3, [r2, #PHY_PTM_SQU_TRAINING] + // For Test Chip Change Program architected timer frequency + MRC p15, 0, r0, c0, c1, 1 // CPUID_EXT_PFR1 + LSR r0, r0, #16 + ANDS r0, r0, #1 // Check generic timer support + BEQ exit + LDR r0, = 600000000 // 600MHz timer frequency + MCR p15, 0, r0, c14, c0, 0 // CNTFRQ + +exit: bx lr // end of dmc_init diff --git a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf index 129660417..c368456d2 100644 --- a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf +++ b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf @@ -46,6 +46,3 @@ gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdFvBaseAddress - - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf index f0521b95c..cec7bbe8a 100644 --- a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf +++ b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf @@ -48,6 +48,3 @@ [FixedPcd] gArmTokenSpaceGuid.PcdFvBaseAddress - - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c index 48934cc6d..227f9e62f 100644 --- a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c +++ b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c @@ -51,39 +51,6 @@ ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA5s[] = { }, }; -// DDR2 timings -PL341_DMC_CONFIG DDRTimings = { - .MaxChip = 1, - .IsUserCfg = FALSE, - .User0Cfg = 0x7C924924, - .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT), - .HasQos = FALSE, - .RefreshPeriod = 0x3D0, - .CasLatency = 0xA, - .WriteLatency = 0x3, - .t_mrd = 0x2, - .t_ras = 0xC, - .t_rc = 0xF, - .t_rcd = 0x104, - .t_rfc = 0x1022, - .t_rp = 0x104, - .t_rrd = 0x2, - .t_wr = 0x4, - .t_wtr = 0x2, - .t_xp = 0x2, - .t_xsr = 0xC8, - .t_esr = 0x4, - .MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 | - DMC_MEMORY_CONFIG_ROW_ADDRESS_14 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10, - .MemoryCfg2 = DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_64, - .MemoryCfg3 = 0x00000001, - .ChipCfg0 = 0x000180C0, - .ChipCfg1 = 0x0000FF00, - .t_faw = 0x00000407, - .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_5 | DDR2_MR_WR_CYCLES_3, - .ExtModeReg = 0x47, -}; - /** Return the current Boot Mode @@ -111,15 +78,11 @@ ArmPlatformGetBootMode ( in the PEI phase. **/ -RETURN_STATUS -ArmPlatformInitialize ( - IN UINTN MpId +VOID +ArmPlatformNormalInitialize ( + VOID ) { - if (!IS_PRIMARY_CORE(MpId)) { - return RETURN_SUCCESS; - } - // Configure periodic timer (TIMER0) for 1MHz operation MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); // Configure 1MHz clock @@ -128,8 +91,6 @@ ArmPlatformInitialize ( MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); // Configure SP810 to use 1MHz clock and disable MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); - - return RETURN_SUCCESS; } /** @@ -143,7 +104,7 @@ ArmPlatformInitializeSystemMemory ( VOID ) { - PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings); + // Memory is initialised in CTA5sBoot.S } EFI_STATUS @@ -194,3 +155,16 @@ ArmPlatformSecTrustzoneInit ( { } + /** + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + diff --git a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S index f90546ef2..62750bde2 100644 --- a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S +++ b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S @@ -15,6 +15,7 @@ #include <Base.h> #include <Library/ArmPlatformLib.h> #include <Drivers/PL35xSmc.h> +#include <Drivers/PL341Dmc.h> #include <ArmPlatform.h> #include <AutoGen.h> @@ -23,44 +24,8 @@ GCC_ASM_EXPORT(ArmPlatformSecBootAction) GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory) -GCC_ASM_IMPORT(PL35xSmcInitialize) GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) -// -// For each Chip Select: ChipSelect / SetCycle / SetOpMode -// -VersatileExpressSmcConfiguration: - // NOR Flash 0 - .word PL350_SMC_DIRECT_CMD_ADDR_CS(0) - .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) - .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV - - // NOR Flash 1 - .word PL350_SMC_DIRECT_CMD_ADDR_CS(4) - .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) - .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV - - // SRAM - .word PL350_SMC_DIRECT_CMD_ADDR_CS(2) - .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) - .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_ADV - - // Usb/Eth/VRAM - .word PL350_SMC_DIRECT_CMD_ADDR_CS(3) - .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6) - .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC - - // Memory Mapped Peripherals - .word PL350_SMC_DIRECT_CMD_ADDR_CS(7) - .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) - .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC - - // VRAM - .word PL350_SMC_DIRECT_CMD_ADDR_CS(1) - .word 0x00049249 - .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC -VersatileExpressSmcConfigurationEnd: - /** Call at the beginning of the platform boot up @@ -84,7 +49,8 @@ ASM_PFX(ArmPlatformSecBootAction): **/ ASM_PFX(ArmPlatformInitializeBootMemory): - bx lr + bx lr + /** Initialize the memory where the initial stacks will reside @@ -97,43 +63,324 @@ ASM_PFX(ArmPlatformInitializeBootMemory): **/ ASM_PFX(ArmPlatformSecBootMemoryInit): - mov r5, lr - - // - // Initialize PL354 SMC - // - LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) - LoadConstantToReg (VersatileExpressSmcConfiguration, r2) - LoadConstantToReg (VersatileExpressSmcConfigurationEnd, r3) - blx ASM_PFX(PL35xSmcInitialize) - - // - // Page mode setup for VRAM - // - LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2) - - // Read current state - ldr r0, [r2, #0] - ldr r0, [r2, #0] - ldr r0, = 0x00000000 - str r0, [r2, #0] - ldr r0, [r2, #0] - - // Enable page mode - ldr r0, [r2, #0] - ldr r0, [r2, #0] - ldr r0, = 0x00000000 - str r0, [r2, #0] - LoadConstantToReg (0x00900090, r0) - str r0, [r2, #0] - - // Confirm page mode enabled - ldr r0, [r2, #0] - ldr r0, [r2, #0] - ldr r0, = 0x00000000 - str r0, [r2, #0] - ldr r0, [r2, #0] - - bx r5 + mov r8, lr + bl smc_init + bl dmc_init + bx r8 + + +/** + Initialise the Static Memory Controller +**/ +smc_init: + + // + // Disable loop buffer for A15 + // + MRC p15, 0, r2, c0, c0, 0 + MOV r1, r2, lsr #4 + LDR r0, =0xFFF + AND r1, r1, r0 + LDR r0, =0xC0F // See if A15 + CMP r1, r0 + BNE smc_init2 // Go if not + + MRC p15, 0, r1, c1, c0, 1 // Read Aux Ctrl Reg + ORR r1, r1, #(1 << 1) // Set Bit 1 + MCR p15, 0, r1, c1, c0, 1 // and write it back + +smc_init2: + + LDR r0, = ARM_VE_SMC_CTRL_BASE + LDR r2, = ARM_VE_SMB_PERIPH_BASE + + // CS0 - NOR0 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS1 - PSRAM + LDR r1, = 0x00027158 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000802 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS2 - usb, ethernet and vram + LDR r1, = 0x000CD2AA + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS3 - IOFPGA peripherals + LDR r1, = 0x00025156 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS4 - NOR1 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS5 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS6 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS7 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // Set refresh period + LDR r1, = 0x1 + STR r1, [r0, #0x20] + + LDR r1, = 0x1 + STR r1, [r0, #0x24] + + // page mode setup for VRAM + LDR r0, = 0x00FFFFFC + ADD r0, r0, r2 + + // read current state + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + // enable page mode + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, = 0x00900090 + STR r1, [r0, #0] + + // confirm page mode enabled + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + BX lr + // end of smc_init + + +/** + Initialise the PL341 Dynamic Memory Controller (DMC) + + On A15, the PHY needs to be locked before configuring the DMC. + After DMC config, the PHY needs to be trained +**/ +#define SCC_PHY_RESET_REG_OFFSET 0x04 + +dmc_init: + + LDR r0, = ARM_VE_DMC_BASE + LDR r1, = ARM_VE_BOARD_PERIPH_BASE + + // On entry:- + // r0 = base address of ssmc controller + // r1 = address of system registers + + // Initializes V2P_CA5 dynamic memory controller + + MOV r2, r1 + + // set config mode + MOV r1, #0x4 + STR r1, [r0, #DMC_COMMAND_REG] + + // initialise memory controlller + + // refresh period + LDR r1, =0x3D0 + STR r1, [r0, #DMC_REFRESH_PRD_REG] + + // cas latency + MOV r1, #0xA + STR r1, [r0, #DMC_CAS_LATENCY_REG] + + // write latency + MOV r1, #0x3 + STR r1, [r0, #DMC_WRITE_LATENCY_REG] + + // t_mrd + MOV r1, #0x2 + STR r1, [r0, #DMC_T_MRD_REG] + + // t_ras + MOV r1, #0x0C + STR r1, [r0, #DMC_T_RAS_REG] + + // t_rc + MOV r1, #0x0F + STR r1, [r0, #DMC_T_RC_REG] + + // t_rcd + LDR r1, =0x00000104 + STR r1, [r0,#DMC_T_RCD_REG] + + // t_rfc + LDR r1, =0x00001022 + STR r1, [r0, #DMC_T_RFC_REG] + + // t_rp + LDR r1, =0x00000104 + STR r1, [r0, #DMC_T_RP_REG] + + // t_rrd + MOV r1, #0x2 + STR r1, [r0, #DMC_T_RRD_REG] + + // t_wr + MOV r1, #0x4 + STR r1, [r0, #DMC_T_WR_REG] + + // t_wtr + MOV r1, #0x2 + STR r1, [r0, #DMC_T_WTR_REG] + + // t_xp + MOV r1, #0x2 + STR r1, [r0, #DMC_T_XP_REG] + + // t_xsr + MOV r1, #0xC8 + STR r1, [r0, #DMC_T_XSR_REG] + + // t_esr + MOV r1, #0x04 + STR r1, [r0, #DMC_T_ESR_REG] + + // t_faw + LDR r1, =0x00000407 + STR r1, [r0, #DMC_T_FAW_REG] + + // set memory config + LDR r1, =0x0001001A + STR r1, [r0, #DMC_MEMORY_CONFIG_REG] + + // set memory config 2 + LDR r1, =0x000000B0 + STR r1, [r0, #DMC_MEMORY_CFG2_REG] + + // initialise external memory chips + // set chip select for chip configuration + LDR r1, =0x000180C0 + STR r1, [r0, #DMC_CHIP_0_CFG_REG] + + // config memories + + // send nop + LDR r1, =0x000C0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B1: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B1 + + // pre-charge all + MOV r1, #0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B2: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B2 + + // set extended mode register 2 + LDR r1, =0x000A8000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register 3 + MOV r1, #0x000B0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register + LDR r1, =0x00094005 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register -DLL reset + LDR r1, =0x00080552 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B3: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B3 + + // pre-charge all + MOV r1, #0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + MOV r1, #0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + MOV r1, #0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register + LDR r1, =0x00080452 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register - Enable OCD defaults + LDR r1, =0x000943C5 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register - OCD Exit + LDR r1, =0x00094047 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + //---------------------------------------- + // go command + MOV r1, #0x0 + STR r1, [r0, #DMC_COMMAND_REG] + // wait for ready +B4: LDR r1, [r0,#DMC_STATUS_REG] + TST r1,#1 + BEQ B4 + +exit: + bx lr + // end of dmc_init diff --git a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c index b7e7b3700..986044156 100644 --- a/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c +++ b/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c @@ -212,3 +212,11 @@ ArmPlatformGetPlatformPpiList ( *PpiList = gPlatformPpiTable; } +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} + |