diff options
Diffstat (limited to 'edk2/ArmPkg')
90 files changed, 2505 insertions, 1548 deletions
diff --git a/edk2/ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf b/edk2/ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf index d3edb533b..0c0ee477b 100644 --- a/edk2/ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf +++ b/edk2/ArmPkg/Application/LinuxLoader/LinuxAtagLoader.inf @@ -35,6 +35,3 @@ [Protocols]
gEfiLoadedImageProtocolGuid
-
- #TODO: RemoveMe
- gEfiDevicePathToTextProtocolGuid
diff --git a/edk2/ArmPkg/Application/LinuxLoader/LinuxConfig.c b/edk2/ArmPkg/Application/LinuxLoader/LinuxConfig.c index 68f7b32c0..b95d0a4dc 100644 --- a/edk2/ArmPkg/Application/LinuxLoader/LinuxConfig.c +++ b/edk2/ArmPkg/Application/LinuxLoader/LinuxConfig.c @@ -14,9 +14,6 @@ #include "LinuxInternal.h" -//TODO: RemoveMe -#include <Protocol/DevicePathToText.h> - #define DEFAULT_BOOT_ENTRY_DESCRIPTION L"Linux" #define MAX_STR_INPUT 300 #define MAX_ASCII_INPUT 300 diff --git a/edk2/ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf b/edk2/ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf index 76773af76..a132dd9fe 100644 --- a/edk2/ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf +++ b/edk2/ArmPkg/Application/LinuxLoader/LinuxFdtLoader.inf @@ -35,6 +35,3 @@ [Protocols]
gEfiLoadedImageProtocolGuid
-
- #TODO: RemoveMe
- gEfiDevicePathToTextProtocolGuid
diff --git a/edk2/ArmPkg/ArmPkg.dec b/edk2/ArmPkg/ArmPkg.dec index c12de9481..7a4aa7993 100644 --- a/edk2/ArmPkg/ArmPkg.dec +++ b/edk2/ArmPkg/ArmPkg.dec @@ -2,7 +2,7 @@ # ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -82,7 +82,7 @@ #
gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
- gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
#
# ARM Secure Firmware PCDs
@@ -99,7 +99,15 @@ gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
-
+
+ #
+ # ARM Hypervisor Firmware PCDs
+ #
+ gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
+ gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
+ gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
+ gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
+
#
# ARM Security Extension
#
@@ -138,26 +146,29 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
# The Primary Core is ClusterId[0] & CoreId[0]
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
+ # Number of the CPU Interface for the Primary Core (eg: The number for the CPU0 of
+ # Cluster1 might be 4 if the implementer had followed the convention: Cpu Interface
+ # = 4 * Cluster)
+ gArmTokenSpaceGuid.PcdGicPrimaryCoreId|0|UINT32|0x00000043
#
# ARM L2x0 PCDs
#
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
- #
- # ARM PL390 General Interrupt Controller
- #
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D
-
#
# BdsLib
#
gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
+ # The compressed Linux kernel is expected to load at MemStart + 0x8000 (e.g. 0x8000_8000)
+ gArmTokenSpaceGuid.PcdArmLinuxKernelFixedOffset|0x00008000|UINT32|0x00000027
# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
+ # If the fixed FDT address is not available, then it should be loaded the below the kernel
+ # The recommandation from the Linux kernel is to have the FDT below 16KB
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
#
# ARM Architectural Timer
diff --git a/edk2/ArmPkg/Contributions.txt b/edk2/ArmPkg/Contributions.txt new file mode 100644 index 000000000..667ca1035 --- /dev/null +++ b/edk2/ArmPkg/Contributions.txt @@ -0,0 +1,188 @@ +
+======================
+= Code Contributions =
+======================
+
+To make a contribution to a TianoCore project, follow these steps.
+1. Create a change description in the format specified below to
+ use in the source control commit log.
+2. Your commit message must include your "Signed-off-by" signature,
+ and "Contributed-under" message.
+3. Your "Contributed-under" message explicitly states that the
+ contribution is made under the terms of the specified
+ contribution agreement. Your "Contributed-under" message
+ must include the name of contribution agreement and version.
+ For example: Contributed-under: TianoCore Contribution Agreement 1.0
+ The "TianoCore Contribution Agreement" is included below in
+ this document.
+4. Submit your code to the TianoCore project using the process
+ that the project documents on its web page. If the process is
+ not documented, then submit the code on development email list
+ for the project.
+
+=======================================
+= Change Description / Commit Message =
+=======================================
+
+Your change description should use the standard format for a
+commit message, and must include your "Signed-off-by" signature
+and the "Contributed-under" message.
+
+== Sample Change Description / Commit Message =
+
+=== Definitions for sample change description ===
+
+* "CodeModule" is a short idenfier for the affected code. For
+ example MdePkg, or MdeModulePkg UsbBusDxe.
+* "Brief-single-line-summary" is a short summary of the change.
+* The entire first line should be less than ~70 characters.
+* "Full-commit-message" a verbose multiple line comment describing
+ the change. Each line should be less than ~70 characters.
+* "Contributed-under" explicitely states that the contribution is
+ made under the terms of the contribtion agreement. This
+ agreement is included below in this document.
+* "Signed-off-by" is the contributor's signature identifying them
+ by their real/legal name and their email address.
+
+=== Start of sample change description / commit message ===
+CodeModule: Brief-single-line-summary
+
+Full-commit-message
+
+Contributed-under: TianoCore Contribution Agreement 1.0
+Signed-off-by: Contributor Name <contributor@email.server>
+=== End of sample change description / commit message ===
+
+========================================
+= TianoCore Contribution Agreement 1.0 =
+========================================
+
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
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+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
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+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
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+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
+USE THE CONTENT.
+
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
+http://opensource.org/licenses/bsd-license.php
+or when applicable, in the associated License.txt file.
+
+Certain other content may be made available under other licenses as
+indicated in or with such Content. (For example, in a License.txt file.)
+
+You accept and agree to the following terms and conditions for Your
+present and future Contributions submitted to TianoCore site. Except
+for the license granted to Intel hereunder, You reserve all right,
+title, and interest in and to Your Contributions.
+
+== SECTION 1: Definitions ==
+* "You" or "Contributor" shall mean the copyright owner or legal
+ entity authorized by the copyright owner that is making a
+ Contribution hereunder. All other entities that control, are
+ controlled by, or are under common control with that entity are
+ considered to be a single Contributor. For the purposes of this
+ definition, "control" means (i) the power, direct or indirect, to
+ cause the direction or management of such entity, whether by
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+ or more of the outstanding shares, or (iii) beneficial ownership
+ of such entity.
+* "Contribution" shall mean any original work of authorship,
+ including any modifications or additions to an existing work,
+ that is intentionally submitted by You to the TinaoCore site for
+ inclusion in, or documentation of, any of the Content. For the
+ purposes of this definition, "submitted" means any form of
+ electronic, verbal, or written communication sent to the
+ TianoCore site or its representatives, including but not limited
+ to communication on electronic mailing lists, source code
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+ or on behalf of, the TianoCore site for the purpose of
+ discussing and improving the Content, but excluding
+ communication that is conspicuously marked or otherwise
+ designated in writing by You as "Not a Contribution."
+
+== SECTION 2: License for Contributions ==
+* Contributor hereby agrees that redistribution and use of the
+ Contribution in source and binary forms, with or without
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+** Redistributions of source code must retain the Contributor's
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+ Contribution and derivative works thereof solely to the minimum
+ extent necessary for licensee to exercise the granted copyright
+ license; this patent license applies solely to those portions of
+ the Contribution that are unmodified. No hardware per se is
+ licensed.
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
+ CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
+ CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ DAMAGE.
+
+== SECTION 3: Representations ==
+* You represent that You are legally entitled to grant the above
+ license. If your employer(s) has rights to intellectual property
+ that You create that includes Your Contributions, You represent
+ that You have received permission to make Contributions on behalf
+ of that employer, that Your employer has waived such rights for
+ Your Contributions.
+* You represent that each of Your Contributions is Your original
+ creation (see Section 4 for submissions on behalf of others).
+ You represent that Your Contribution submissions include complete
+ details of any third-party license or other restriction
+ (including, but not limited to, related patents and trademarks)
+ of which You are personally aware and which are associated with
+ any part of Your Contributions.
+
+== SECTION 4: Third Party Contributions ==
+* Should You wish to submit work that is not Your original creation,
+ You may submit it to TianoCore site separately from any
+ Contribution, identifying the complete details of its source
+ and of any license or other restriction (including, but not
+ limited to, related patents, trademarks, and license agreements)
+ of which You are personally aware, and conspicuously marking the
+ work as "Submitted on behalf of a third-party: [named here]".
+
+== SECTION 5: Miscellaneous ==
+* Applicable Laws. Any claims arising under or relating to this
+ Agreement shall be governed by the internal substantive laws of
+ the State of Delaware or federal courts located in Delaware,
+ without regard to principles of conflict of laws.
+* Language. This Agreement is in the English language only, which
+ language shall be controlling in all respects, and all versions
+ of this Agreement in any other language shall be for accommodation
+ only and shall not be binding. All communications and notices made
+ or given pursuant to this Agreement, and all documentation and
+ support to be provided, unless otherwise noted, shall be in the
+ English language.
+
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S b/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S deleted file mode 100644 index ad28d10ce..000000000 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S +++ /dev/null @@ -1,67 +0,0 @@ -//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <Library/ArmCpuLib.h>
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
-
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ASM_PFX(ArmCpuSynchronizeWait):
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- bx lr
- b ASM_PFX(CArmCpuSynchronizeWait)
-
-
-#if 0
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
-GCC_ASM_EXPORT(ArmGetScuBaseAddress)
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
-
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ASM_PFX(ArmCpuSynchronizeWait):
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- beq ArmWaitScuEnabled
- b ASM_PFX(CArmCpuSynchronizeWait)
-
-// IN None
-// OUT r0 = SCU Base Address
-ASM_PFX(ArmGetScuBaseAddress):
- // Read Configuration Base Address Register. ArmCBar cannot be called to get
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the
- // offset 0x0000 from the Private Memory Region.
- mrc p15, 4, r0, c15, c0, 0
- bx lr
-
-ASM_PFX(ArmWaitScuEnabled):
- // Read Configuration Base Address Register. ArmCBar cannot be called to get
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the
- // offset 0x0000 from the Private Memory Region.
- mrc p15, 4, r0, c15, c0, 0
- add r0, r0, #A9_SCU_CONTROL_OFFSET
- ldr r0, [r0]
- cmp r0, #1
- bne ArmWaitScuEnabled
- bx lr
-#endif
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm b/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm deleted file mode 100644 index d0fc2b5a8..000000000 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm +++ /dev/null @@ -1,54 +0,0 @@ -//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <Library/ArmCpuLib.h>
-#include <Chipset/ArmCortexA9.h>
-
- EXPORT ArmCpuSynchronizeWait
- EXPORT ArmGetScuBaseAddress
- IMPORT CArmCpuSynchronizeWait
-
- PRESERVE8
- AREA ArmCortexA9Helper, CODE, READONLY
-
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ArmCpuSynchronizeWait
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- beq ArmWaitScuEnabled
- b CArmCpuSynchronizeWait
-
-// IN None
-// OUT r0 = SCU Base Address
-ArmGetScuBaseAddress
- // Read Configuration Base Address Register. ArmCBar cannot be called to get
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the
- // offset 0x0000 from the Private Memory Region.
- mrc p15, 4, r0, c15, c0, 0
- bx lr
-
-ArmWaitScuEnabled
- // Read Configuration Base Address Register. ArmCBar cannot be called to get
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the
- // offset 0x0000 from the Private Memory Region.
- mrc p15, 4, r0, c15, c0, 0
- add r0, r0, #A9_SCU_CONTROL_OFFSET
- ldr r0, [r0]
- cmp r0, #1
- bne ArmWaitScuEnabled
- bx lr
-
- END
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c b/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c index 2e285d54c..a08b7b1ae 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c @@ -1,6 +1,6 @@ /** @file
- Copyright (c) 2011, ARM Limited. All rights reserved.
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,76 +15,15 @@ #include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
-#include <Library/ArmGicLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
VOID
-ArmCpuSynchronizeSignal (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
- // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
- // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
- // Mem as been initialized
- } else {
- // Send SGI to all Secondary core to wake them up from WFI state.
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
- }
-}
-
-VOID
-CArmCpuSynchronizeWait (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- // Waiting for the SGI from the primary core
- ArmCallWFI ();
-
- // Acknowledge the interrupt and send End of Interrupt signal.
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
-}
-
-#if 0
-VOID
-ArmEnableScu (
- VOID
- )
-{
- INTN ScuBase;
-
- ScuBase = ArmGetScuBaseAddress();
-
- // Invalidate all: write -1 to SCU Invalidate All register
- MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
- // Enable SCU
- MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
-}
-#endif
-
-VOID
ArmCpuSetup (
IN UINTN MpId
)
{
- /*AMP mode and SMP mode
-
- By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:
-
- 1.Write the SCU register to change CPU mode.
- 2.Disable interrupts.
- 3.Clean and invalidate all the D-cache.
- 4.Write SMP/nAMP bit as 1.
- 5.Enable interrupts.
-
- Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html
- */
-
- // If MPCore then Enable the SCU
- if (ArmIsMpCore()) {
- //ArmEnableScu ();
- }
+ ASSERT(0); //TODO: Implement me
}
@@ -93,20 +32,6 @@ ArmCpuSetupSmpNonSecure ( IN UINTN MpId
)
{
-#if 0
- INTN ScuBase;
-
- ArmSetAuxCrBit (A9_FEATURE_SMP);
-
- // Make the SCU accessible in Non Secure world
- if (IS_PRIMARY_CORE(MpId)) {
- ScuBase = ArmGetScuBaseAddress();
-
- // Allow NS access to SCU register
- MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
- // Allow NS access to Private Peripherals
- MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
- }
-#endif
+ ASSERT(0); //TODO: Implement me
}
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf b/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf index 2b9621c6e..f7ecfb090 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf @@ -1,5 +1,5 @@ #/* @file
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -25,18 +25,8 @@ [LibraryClasses]
ArmLib
- ArmGicSecLib
IoLib
PcdLib
[Sources.common]
Arm11Lib.c
- Arm11Helper.asm | RVCT
- Arm11Helper.S | GCC
-
-[FixedPcd]
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
- gArmTokenSpaceGuid.PcdArmPrimaryCore
-
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.S b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.S deleted file mode 100644 index feeefcdd4..000000000 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.S +++ /dev/null @@ -1,51 +0,0 @@ -//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AsmMacroIoLib.h>
-#include <Library/ArmCpuLib.h>
-#include <Library/ArmGicLib.h>
-#include <Library/PcdLib.h>
-#include <Chipset/ArmV7.h>
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
-// Dirty hack to get the Fixed value of GicDistributorBase
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdGicDistributorBase)
-
-
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ASM_PFX(ArmCpuSynchronizeWait):
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- beq ArmWaitGicDistributorEnabled
- push {r1,lr}
- LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)
- blx r1
- pop {r1,lr}
- bx lr
-
-// IN None
-ArmWaitGicDistributorEnabled:
- LoadConstantToReg (ASM_PFX(_gPcd_FixedAtBuild_PcdGicDistributorBase), r0)
- ldr r0, [r0]
-_WaitGicDistributor:
- ldr r1, [r0, #ARM_GIC_ICDDCR]
- cmp r1, #1
- bne _WaitGicDistributor
- bx lr
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.asm b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.asm deleted file mode 100644 index 886c00b61..000000000 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Helper.asm +++ /dev/null @@ -1,56 +0,0 @@ -//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AsmMacroIoLib.h>
-#include <Library/ArmCpuLib.h>
-#include <Library/ArmGicLib.h>
-#include <Library/PcdLib.h>
-#include <Chipset/ArmV7.h>
-
- INCLUDE AsmMacroIoLib.inc
-
- EXPORT ArmCpuSynchronizeWait
- IMPORT CArmCpuSynchronizeWait
- // Dirty hack to get the Fixed value of GicDistributorBase
- IMPORT _gPcd_FixedAtBuild_PcdGicDistributorBase
-
- PRESERVE8
- AREA ArmCortexA15Helper, CODE, READONLY
-
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ArmCpuSynchronizeWait
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- beq ArmWaitGicDistributorEnabled
- // Case when the stack has been set up
- push {r1,lr}
- LoadConstantToReg (CArmCpuSynchronizeWait, r1)
- blx r1
- pop {r1,lr}
- bx lr
-
-
-// IN None
-ArmWaitGicDistributorEnabled
- LoadConstantToReg (_gPcd_FixedAtBuild_PcdGicDistributorBase, r0)
- ldr r0, [r0]
-_WaitGicDistributor
- ldr r1, [r0, #ARM_GIC_ICDDCR]
- cmp r1, #1
- bne _WaitGicDistributor
- bx lr
-
- END
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c index a3af3a8c5..95ab073e1 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c @@ -1,6 +1,6 @@ /** @file
- Copyright (c) 2011, ARM Limited. All rights reserved.
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,40 +15,12 @@ #include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
-#include <Library/ArmGicLib.h>
#include <Library/ArmV7ArchTimerLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
-#include <Chipset/ArmV7.h>
-
-VOID
-ArmCpuSynchronizeSignal (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
- // Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor
- // to be enabled (done by the Sec module itself) as a way to know when the Init Boot
- // Mem as been initialized
- } else {
- // Send SGI to all Secondary core to wake them up from WFI state.
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
- }
-}
-
-VOID
-CArmCpuSynchronizeWait (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- // Waiting for the SGI from the primary core
- ArmCallWFI ();
-
- // Acknowledge the interrupt and send End of Interrupt signal.
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
-}
+#include <Chipset/ArmCortexA15.h>
VOID
ArmCpuSetup (
@@ -69,10 +41,11 @@ ArmCpuSetup ( // if security extensions are implemented.
ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
- /*// If MPCore then Enable the SCU
if (ArmIsMpCore()) {
- ArmEnableScu ();
- }*/
+ // Turn on SMP coherency
+ ArmSetAuxCrBit (A15_FEATURE_SMP);
+ }
+
}
@@ -81,8 +54,6 @@ ArmCpuSetupSmpNonSecure ( IN UINTN MpId
)
{
- //ArmSetAuxCrBit (A15_FEATURE_SMP);
-
/*// Make the SCU accessible in Non Secure world
if (IS_PRIMARY_CORE(MpId)) {
ScuBase = ArmGetScuBaseAddress();
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf index 69ecfb109..bcf7f6bfb 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf @@ -1,5 +1,5 @@ #/* @file
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -25,14 +25,11 @@ [LibraryClasses]
ArmLib
- ArmGicSecLib
IoLib
PcdLib
[Sources.common]
ArmCortexA15Lib.c
- ArmCortexA15Helper.asm | RVCT
- ArmCortexA15Helper.S | GCC
[FeaturePcd]
@@ -40,7 +37,4 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c new file mode 100644 index 000000000..716a3d0a4 --- /dev/null +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c @@ -0,0 +1,47 @@ +/** @file + + Copyright (c) 2011-2012, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/ArmLib.h> +#include <Library/ArmCpuLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> + +#include <Chipset/ArmCortexA5.h> + +VOID +ArmCpuSetup ( + IN UINTN MpId + ) +{ + // Enable SWP instructions + ArmEnableSWPInstruction (); + + // Enable program flow prediction, if supported. + ArmEnableBranchPrediction (); + + // If MPCore then Enable the SCU + if (ArmIsMpCore()) { + // Signals the Cortex-A5 processor is taking part in coherency + ArmSetAuxCrBit (A5_FEATURE_SMP); + } +} + + +VOID +ArmCpuSetupSmpNonSecure ( + IN UINTN MpId + ) +{ +} diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf new file mode 100644 index 000000000..36ae596b2 --- /dev/null +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf @@ -0,0 +1,38 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmCortexA5Lib + FILE_GUID = c9709ea3-1beb-4806-889a-8a1d5e5e1697 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmCpuLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + ArmLib + IoLib + PcdLib + +[Sources.common] + ArmCortexA5Lib.c + +[FeaturePcd] + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c index d755f6824..e0ba1fab8 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c @@ -20,24 +20,6 @@ #include <Chipset/ArmV7.h>
VOID
-ArmCpuSynchronizeWait (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- // The CortexA8 is a Unicore CPU. We must not use Synchronization functions
- ASSERT(0);
-}
-
-VOID
-ArmCpuSynchronizeSignal (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- // The CortexA8 is a Unicore CPU. We must not use Synchronization functions
- ASSERT(0);
-}
-
-VOID
ArmCpuSetup (
IN UINTN MpId
)
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S index c69c8d44c..5db586192 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S @@ -1,5 +1,5 @@ //
-// Copyright (c) 2011, ARM Limited. All rights reserved.
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -18,24 +18,7 @@ .text
.align 3
-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)
GCC_ASM_EXPORT(ArmGetScuBaseAddress)
-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)
-
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ASM_PFX(ArmCpuSynchronizeWait):
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- beq ASM_PFX(ArmWaitScuEnabled)
- // Case when the stack has been set up
- push {r1,lr}
- LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)
- blx r1
- pop {r1,lr}
- bx lr
// IN None
// OUT r0 = SCU Base Address
@@ -45,14 +28,3 @@ ASM_PFX(ArmGetScuBaseAddress): // offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
bx lr
-
-ASM_PFX(ArmWaitScuEnabled):
- // Read Configuration Base Address Register. ArmCBar cannot be called to get
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the
- // offset 0x0000 from the Private Memory Region.
- mrc p15, 4, r0, c15, c0, 0
- add r0, r0, #A9_SCU_CONTROL_OFFSET
- ldr r0, [r0]
- cmp r0, #1
- bne ASM_PFX(ArmWaitScuEnabled)
- bx lr
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm index ef5015c18..7150834b0 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm @@ -1,5 +1,5 @@ //
-// Copyright (c) 2011, ARM Limited. All rights reserved.
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -17,28 +17,11 @@ INCLUDE AsmMacroIoLib.inc
- EXPORT ArmCpuSynchronizeWait
EXPORT ArmGetScuBaseAddress
- IMPORT CArmCpuSynchronizeWait
PRESERVE8
AREA ArmCortexA9Helper, CODE, READONLY
-// VOID
-// ArmCpuSynchronizeWait (
-// IN ARM_CPU_SYNCHRONIZE_EVENT Event
-// );
-ArmCpuSynchronizeWait
- cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- // The SCU enabled is the event to tell us the Init Boot Memory is initialized
- beq ArmWaitScuEnabled
- // Case when the stack has been set up
- push {r1,lr}
- LoadConstantToReg (CArmCpuSynchronizeWait, r1)
- blx r1
- pop {r1,lr}
- bx lr
-
// IN None
// OUT r0 = SCU Base Address
ArmGetScuBaseAddress
@@ -48,15 +31,4 @@ ArmGetScuBaseAddress mrc p15, 4, r0, c15, c0, 0
bx lr
-ArmWaitScuEnabled
- // Read Configuration Base Address Register. ArmCBar cannot be called to get
- // the Configuration BAR as a stack is not necessary setup. The SCU is at the
- // offset 0x0000 from the Private Memory Region.
- mrc p15, 4, r0, c15, c0, 0
- add r0, r0, #A9_SCU_CONTROL_OFFSET
- ldr r0, [r0]
- cmp r0, #1
- bne ArmWaitScuEnabled
- bx lr
-
END
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c index 7c5c3ee6a..8d9530cee 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c @@ -1,6 +1,6 @@ /** @file
- Copyright (c) 2011, ARM Limited. All rights reserved.
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,40 +15,12 @@ #include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
-#include <Library/ArmGicLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmCortexA9.h>
VOID
-ArmCpuSynchronizeSignal (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
- // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
- // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
- // Mem as been initialized
- } else {
- // Send SGI to all Secondary core to wake them up from WFI state.
- ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
- }
-}
-
-VOID
-CArmCpuSynchronizeWait (
- IN ARM_CPU_SYNCHRONIZE_EVENT Event
- )
-{
- // Waiting for the SGI from the primary core
- ArmCallWFI ();
-
- // Acknowledge the interrupt and send End of Interrupt signal.
- ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
-}
-
-VOID
ArmEnableScu (
VOID
)
@@ -76,6 +48,9 @@ ArmCpuSetup ( // If MPCore then Enable the SCU
if (ArmIsMpCore()) {
+ // Signals the Cortex-A9 processor is taking part in coherency
+ ArmSetAuxCrBit (A9_FEATURE_SMP);
+
ArmEnableScu ();
}
}
@@ -88,8 +63,6 @@ ArmCpuSetupSmpNonSecure ( {
INTN ScuBase;
- ArmSetAuxCrBit (A9_FEATURE_SMP);
-
// Make the SCU accessible in Non Secure world
if (IS_PRIMARY_CORE(MpId)) {
ScuBase = ArmGetScuBaseAddress();
diff --git a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf index a03efd237..866736f6f 100644 --- a/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf +++ b/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf @@ -1,5 +1,5 @@ #/* @file
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,6 @@ [LibraryClasses]
ArmLib
- ArmGicSecLib
IoLib
PcdLib
@@ -39,6 +38,3 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore
-
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S b/edk2/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S index 96bd68246..96bd68246 100644 --- a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S +++ b/edk2/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S diff --git a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm b/edk2/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm index 4af58339b..4af58339b 100644 --- a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm +++ b/edk2/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm diff --git a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S b/edk2/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S index 86d2a7135..86d2a7135 100644 --- a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S +++ b/edk2/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S diff --git a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm b/edk2/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm index 736d479bf..c3f494ae3 100644 --- a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm +++ b/edk2/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm @@ -59,9 +59,7 @@ This is the stack constructed by the exception handler (low address to high addr IMPORT CommonCExceptionHandler
PRESERVE8
- AREA DxeExceptionHandlers, CODE, READONLY
-
- ALIGN 32
+ AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5
//
// This code gets copied to the ARM vector table
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf index 9a3b8e8af..b471e4ac2 100644 --- a/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf +++ b/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf @@ -3,7 +3,7 @@ # DXE CPU driver
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -24,24 +24,26 @@ ENTRY_POINT = CpuDxeInitialize
-[Sources.ARM]
+[Sources.Common]
CpuDxe.c
CpuDxe.h
CpuMpCore.c
- Exception.c
#
# Prior to ARMv6 we have multiple stacks, one per mode
#
-# ExceptionSupport.asm | RVCT
-# ExceptionSupport.S | GCC
+# ArmV4/ExceptionSupport.asm | RVCT
+# ArmV4/ExceptionSupport.S | GCC
#
# ARMv6 or later uses a single stack via srs/stm instructions
#
- ExceptionSupport.ARMv6.asm | RVCT
- ExceptionSupport.ARMv6.S | GCC
- Mmu.c
+
+[Sources.ARM]
+ Mmu.c
+ Exception.c
+ ArmV6/ExceptionSupport.asm | RVCT
+ ArmV6/ExceptionSupport.S | GCC
[Packages]
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/Mmu.c b/edk2/ArmPkg/Drivers/CpuDxe/Mmu.c index f54350b5a..dcc7b682c 100644 --- a/edk2/ArmPkg/Drivers/CpuDxe/Mmu.c +++ b/edk2/ArmPkg/Drivers/CpuDxe/Mmu.c @@ -749,14 +749,14 @@ ConvertSectionToPages ( DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
- // obtain page table base
+ // Obtain page table base
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
- // calculate index into first level translation table for start of modification
+ // Calculate index into first level translation table for start of modification
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
- // get section attributes and convert to page attributes
+ // Get section attributes and convert to page attributes
SectionDescriptor = FirstLevelTable[FirstLevelIdx];
PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(SectionDescriptor,0);
@@ -765,7 +765,7 @@ ConvertSectionToPages ( PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(SectionDescriptor);
PageDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(SectionDescriptor);
- // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
+ // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);
if (EFI_ERROR(Status)) {
return Status;
@@ -773,18 +773,18 @@ ConvertSectionToPages ( PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
- // write the page table entries out
+ // Write the page table entries out
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
}
- // flush d-cache so descriptors make it back to uncached memory for subsequent table walks
+ // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE);
- // formulate page table entry, Domain=0, NS=0
+ // Formulate page table entry, Domain=0, NS=0
PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
- // write the page table entry out, repalcing section entry
+ // Write the page table entry out, replacing section entry
FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
return EFI_SUCCESS;
diff --git a/edk2/ArmPkg/Drivers/PL390Gic/PL390Gic.c b/edk2/ArmPkg/Drivers/PL390Gic/PL390Gic.c index 9da5cc4b5..8a10d113f 100644 --- a/edk2/ArmPkg/Drivers/PL390Gic/PL390Gic.c +++ b/edk2/ArmPkg/Drivers/PL390Gic/PL390Gic.c @@ -1,6 +1,6 @@ /** @file
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -15,57 +15,56 @@ #include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
+#include <Library/PcdLib.h>
-VOID
+UINTN
EFIAPI
-ArmGicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList
+ArmGicGetMaxNumInterrupts (
+ IN INTN GicDistributorBase
)
{
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
+ return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
}
-UINT32
+VOID
EFIAPI
-ArmGicAcknowledgeSgiFrom (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId
+ArmGicSendSgiTo (
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
)
{
- INTN InterruptId;
-
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
-
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
- return 1;
- } else {
- return 0;
- }
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
}
-UINT32
+RETURN_STATUS
EFIAPI
-ArmGicAcknowledgeSgi2From (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId,
- IN INTN SgiId
+ArmGicAcknowledgeInterrupt (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *CoreId,
+ OUT UINTN *InterruptId
)
{
- INTN InterruptId;
+ UINT32 Interrupt;
+
+ // Read the Interrupt Acknowledge Register
+ Interrupt = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
- InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+ // Check if it is a valid interrupt ID
+ if ((Interrupt & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {
+ // Got a valid SGI number hence signal End of Interrupt by writing to ICCEOIR
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Interrupt);
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
- return 1;
+ if (CoreId) {
+ *CoreId = (Interrupt >> 10) & 0x7;
+ }
+ if (InterruptId) {
+ *InterruptId = Interrupt & 0x3FF;
+ }
+ return RETURN_SUCCESS;
} else {
- return 0;
+ return RETURN_INVALID_PARAMETER;
}
}
diff --git a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index 329298850..1a8239e73 100644 --- a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR> Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR> Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -26,6 +27,7 @@ Abstract: #include <Library/BaseLib.h> #include <Library/DebugLib.h> #include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> #include <Library/UefiBootServicesTableLib.h> #include <Library/UefiLib.h> #include <Library/PcdLib.h> @@ -35,18 +37,6 @@ Abstract: #include <Protocol/Cpu.h> #include <Protocol/HardwareInterrupt.h> -// number of 32-bit registers needed to represent those interrupts as a bit -// (used for enable set, enable clear, pending set, pending clear, and active regs) -#define ARM_GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32) - -// number of 32-bit registers needed to represent those interrupts as two bits -// (used for configuration reg) -#define ARM_GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16) - -// number of 32-bit registers needed to represent interrupts as 8-bit priority field -// (used for priority regs) -#define ARM_GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4) - #define ARM_GIC_DEFAULT_PRIORITY 0x80 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol; @@ -56,7 +46,10 @@ extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol; // EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; -HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[FixedPcdGet32(PcdGicNumInterrupts)]; +// Maximum Number of Interrupts +UINTN mGicNumInterrupts = 0; + +HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL; /** Register Handler for the specified interrupt source. @@ -77,7 +70,7 @@ RegisterInterruptSource ( IN HARDWARE_INTERRUPT_HANDLER Handler ) { - if (Source > PcdGet32(PcdGicNumInterrupts)) { + if (Source > mGicNumInterrupts) { ASSERT(FALSE); return EFI_UNSUPPORTED; } @@ -120,16 +113,16 @@ EnableInterruptSource ( UINT32 RegOffset; UINTN RegShift; - if (Source > PcdGet32(PcdGicNumInterrupts)) { + if (Source > mGicNumInterrupts) { ASSERT(FALSE); return EFI_UNSUPPORTED; } - // calculate enable register offset and bit position + // Calculate enable register offset and bit position RegOffset = Source / 32; RegShift = Source % 32; - // write set-enable register + // Write set-enable register MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift); return EFI_SUCCESS; @@ -155,7 +148,7 @@ DisableInterruptSource ( UINT32 RegOffset; UINTN RegShift; - if (Source > PcdGet32(PcdGicNumInterrupts)) { + if (Source > mGicNumInterrupts) { ASSERT(FALSE); return EFI_UNSUPPORTED; } @@ -192,7 +185,7 @@ GetInterruptSourceState ( UINT32 RegOffset; UINTN RegShift; - if (Source > PcdGet32(PcdGicNumInterrupts)) { + if (Source > mGicNumInterrupts) { ASSERT(FALSE); return EFI_UNSUPPORTED; } @@ -228,7 +221,7 @@ EndOfInterrupt ( IN HARDWARE_INTERRUPT_SOURCE Source ) { - if (Source > PcdGet32(PcdGicNumInterrupts)) { + if (Source > mGicNumInterrupts) { ASSERT(FALSE); return EFI_UNSUPPORTED; } @@ -259,9 +252,10 @@ IrqInterruptHandler ( HARDWARE_INTERRUPT_HANDLER InterruptHandler; GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR); - //TODO: Comment me - if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) { - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, GicInterrupt); + + // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt). + if (GicInterrupt >= mGicNumInterrupts) { + // The special interrupt do not need to be acknowledge return; } @@ -311,11 +305,11 @@ ExitBootServicesEvent ( UINTN Index; // Acknowledge all pending interrupts - for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) { + for (Index = 0; Index < mGicNumInterrupts; Index++) { DisableInterruptSource (&gHardwareInterruptProtocol, Index); } - for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) { + for (Index = 0; Index < mGicNumInterrupts; Index++) { EndOfInterrupt (&gHardwareInterruptProtocol, Index); } @@ -349,11 +343,21 @@ InterruptDxeInitialize ( UINT32 RegOffset; UINTN RegShift; EFI_CPU_ARCH_PROTOCOL *Cpu; + UINT32 CpuTarget; + // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0 + DEBUG_CODE_BEGIN(); + if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) { + DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n")); + } + DEBUG_CODE_END(); + // Make sure the Interrupt Controller Protocol is not already installed in the system. ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); - for (Index = 0; Index < PcdGet32(PcdGicNumInterrupts); Index++) { + mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase)); + + for (Index = 0; Index < mGicNumInterrupts; Index++) { DisableInterruptSource (&gHardwareInterruptProtocol, Index); // Set Priority @@ -366,9 +370,11 @@ InterruptDxeInitialize ( ); } - // Configure interrupts for cpu 0 - for (Index = 0; Index < ARM_GIC_NUM_REG_PER_INT_BYTES; Index++) { - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101); + // Configure interrupts for Primary Cpu + CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId)); + CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8); + for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) { + MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget); } // Set binary point reg to 0x7 (no preemption) @@ -383,7 +389,8 @@ InterruptDxeInitialize ( // Enable gic distributor MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1); - ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers)); + // Initialize the array for the Interrupt Handlers + gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts); Status = gBS->InstallMultipleProtocolInterfaces ( &gHardwareInterruptHandle, diff --git a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf index 48ae8ba82..b63216ee9 100644 --- a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf +++ b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf @@ -1,6 +1,8 @@ #/** @file # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR> +# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at @@ -22,6 +24,7 @@ [Sources.common] + PL390Gic.c PL390GicDxe.c [Packages] @@ -35,6 +38,7 @@ UefiBootServicesTableLib DebugLib PrintLib + MemoryAllocationLib UefiDriverEntryPoint IoLib @@ -45,7 +49,9 @@ [FixedPcd.common] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - gArmTokenSpaceGuid.PcdGicNumInterrupts + + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdGicPrimaryCoreId [Depex] gEfiCpuArchProtocolGuid diff --git a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicLib.inf b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicLib.inf index cae5c2b24..4eb6ffbdb 100644 --- a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicLib.inf +++ b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicLib.inf @@ -1,5 +1,5 @@ #/* @file
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
diff --git a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSec.c index 57ae14150..e47e23d58 100644 --- a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSec.c +++ b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSec.c @@ -1,6 +1,6 @@ /** @file
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -12,7 +12,9 @@ *
**/
-#include <Uefi.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
@@ -23,12 +25,14 @@ VOID
EFIAPI
ArmGicSetupNonSecure (
+ IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
)
{
UINTN InterruptId;
UINTN CachedPriorityMask;
+ UINTN Index;
CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
@@ -45,15 +49,46 @@ ArmGicSetupNonSecure ( MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
}
- // Ensure all GIC interrupts are Non-Secure
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
+ if (IS_PRIMARY_CORE(MpId)) {
+ // Ensure all GIC interrupts are Non-Secure
+ for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
+ }
+ } else {
+ // The secondary cores only set the Non Secure bit to their banked PPIs
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
+ }
// Ensure all interrupts can get through the priority mask
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
}
+/*
+ * This function configures the interrupts set by the mask to be secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicSetSecureInterrupts (
+ IN UINTN GicDistributorBase,
+ IN UINTN* GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
+ )
+{
+ UINTN Index;
+ UINT32 InterruptStatus;
+
+ // We must not have more interrupts defined by the mask than the number of available interrupts
+ ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
+
+ // Set all the interrupts defined by the mask as Secure
+ for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
+ InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
+ }
+}
+
VOID
EFIAPI
ArmGicEnableInterruptInterface (
@@ -64,7 +99,7 @@ ArmGicEnableInterruptInterface ( MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
// Enable CPU interface in Secure world
- // Enable CPU inteface in Non-secure World
+ // Enable CPU interface in Non-secure World
// Signal Secure Interrupts to CPU using FIQ line *
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
ARM_GIC_ICCICR_ENABLE_SECURE |
@@ -74,6 +109,19 @@ ArmGicEnableInterruptInterface ( VOID
EFIAPI
+ArmGicDisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ UINT32 ControlValue;
+
+ // Disable CPU interface in Secure world and Non-secure World
+ ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
+}
+
+VOID
+EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
)
diff --git a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf index fdec5c68d..73faa39b6 100644 --- a/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf +++ b/edk2/ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf @@ -1,5 +1,5 @@ #/* @file
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -17,7 +17,7 @@ FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
MODULE_TYPE = SEC
VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmGicSecLib
+ LIBRARY_CLASS = ArmGicLib
[Sources]
PL390Gic.c
@@ -26,3 +26,13 @@ [Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[FixedPcd.common]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c index 90dcec456..50de7668e 100644 --- a/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -137,14 +137,14 @@ TimerDriverSetTimerPeriod ( { UINT64 TimerTicks; - // always disable the timer + // Always disable the timer ArmArchTimerDisableTimer (); if (TimerPeriod != 0) { // Convert TimerPeriod to micro sec units TimerTicks = DivU64x32 (TimerPeriod, 10); - TimerTicks = MultU64x32 (TimerPeriod, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000)); + TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000)); ArmArchTimerSetTimerVal((UINTN)TimerTicks); diff --git a/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c b/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c index a9d1c37c5..e6604ba0e 100644 --- a/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c +++ b/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c @@ -263,18 +263,22 @@ FileDelete ( Fcb = SEMIHOST_FCB_FROM_THIS(File);
- // Get the filename from the Fcb
- NameSize = AsciiStrLen (Fcb->FileName);
- FileName = AllocatePool (NameSize + 1);
+ if (!Fcb->IsRoot) {
+ // Get the filename from the Fcb
+ NameSize = AsciiStrLen (Fcb->FileName);
+ FileName = AllocatePool (NameSize + 1);
- AsciiStrCpy (FileName, Fcb->FileName);
+ AsciiStrCpy (FileName, Fcb->FileName);
- // Close the file if it's open. Disregard return status,
- // since it might give an error if the file isn't open.
- File->Close (File);
-
- // Call the semihost interface to delete the file.
- Status = SemihostFileRemove (FileName);
+ // Close the file if it's open. Disregard return status,
+ // since it might give an error if the file isn't open.
+ File->Close (File);
+
+ // Call the semihost interface to delete the file.
+ Status = SemihostFileRemove (FileName);
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
return Status;
}
@@ -358,14 +362,19 @@ FileSetPosition ( Fcb = SEMIHOST_FCB_FROM_THIS(File);
- Status = SemihostFileLength (Fcb->SemihostHandle, &Length);
- if (!EFI_ERROR(Status) && (Length < Position)) {
- Position = Length;
- }
+ if (!Fcb->IsRoot) {
+ Status = SemihostFileLength (Fcb->SemihostHandle, &Length);
+ if (!EFI_ERROR(Status) && (Length < Position)) {
+ Position = Length;
+ }
- Status = SemihostFileSeek (Fcb->SemihostHandle, (UINT32)Position);
- if (!EFI_ERROR(Status)) {
+ Status = SemihostFileSeek (Fcb->SemihostHandle, (UINT32)Position);
+ if (!EFI_ERROR(Status)) {
+ Fcb->Position = Position;
+ }
+ } else {
Fcb->Position = Position;
+ Status = EFI_SUCCESS;
}
return Status;
diff --git a/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h b/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h index 7907a1101..a9b200b2a 100644 --- a/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h +++ b/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h @@ -17,35 +17,13 @@ #define __SEMIHOST_FS_H__
EFI_STATUS
-SemihostFsSupported(
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
- );
-
-EFI_STATUS
-SemihostFsStart(
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
- );
-
-EFI_STATUS
-SemihostFsStop(
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
- );
-
-EFI_STATUS
-VolumeOpen(
+VolumeOpen (
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root
);
EFI_STATUS
-FileOpen(
+FileOpen (
IN EFI_FILE *File,
OUT EFI_FILE **NewHandle,
IN CHAR16 *FileName,
@@ -54,7 +32,7 @@ FileOpen( );
EFI_STATUS
-FileClose(
+FileClose (
IN EFI_FILE *File
);
@@ -64,33 +42,33 @@ FileDelete( );
EFI_STATUS
-FileRead(
+FileRead (
IN EFI_FILE *File,
IN OUT UINTN *BufferSize,
OUT VOID *Buffer
);
EFI_STATUS
-FileWrite(
+FileWrite (
IN EFI_FILE *File,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
);
EFI_STATUS
-FileGetPosition(
+FileGetPosition (
IN EFI_FILE *File,
OUT UINT64 *Position
);
EFI_STATUS
-FileSetPosition(
+FileSetPosition (
IN EFI_FILE *File,
IN UINT64 Position
);
EFI_STATUS
-FileGetInfo(
+FileGetInfo (
IN EFI_FILE *File,
IN EFI_GUID *InformationType,
IN OUT UINTN *BufferSize,
@@ -98,7 +76,7 @@ FileGetInfo( );
EFI_STATUS
-FileSetInfo(
+FileSetInfo (
IN EFI_FILE *File,
IN EFI_GUID *InformationType,
IN UINTN BufferSize,
@@ -106,7 +84,7 @@ FileSetInfo( );
EFI_STATUS
-FileFlush(
+FileFlush (
IN EFI_FILE *File
);
diff --git a/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf b/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf index 608b36b5c..25b728948 100644 --- a/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf +++ b/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf @@ -1,4 +1,3 @@ - #/** @file # Support a Semi Host file system over a debuggers JTAG # @@ -22,7 +21,6 @@ ENTRY_POINT = SemihostFsEntryPoint - [Sources.ARM] Arm/SemihostFs.c diff --git a/edk2/ArmPkg/Include/AsmMacroIoLib.h b/edk2/ArmPkg/Include/AsmMacroIoLib.h index a4ae22dca..c8692fcfd 100644 --- a/edk2/ArmPkg/Include/AsmMacroIoLib.h +++ b/edk2/ArmPkg/Include/AsmMacroIoLib.h @@ -122,7 +122,7 @@ // Convert the (ClusterId,CoreId) into a Core Position
// We assume there are 4 cores per cluster
-#define GetCorePositionInStack(Pos, MpId, Tmp) \
+#define GetCorePositionFromMpId(Pos, MpId, Tmp) \
lsr Pos, MpId, #6 ; \
and Tmp, MpId, #3 ; \
add Pos, Pos, Tmp
@@ -144,6 +144,21 @@ _SetPrimaryStackInitGlobals: ; \ b _SetPrimaryStackInitGlobals ; \
_SetPrimaryStackEnd:
+// Initialize the Global Variable with '0'
+#define InitializePrimaryStack(GlobalSize, Tmp1) \
+ and Tmp1, GlobalSize, #7 ; \
+ rsbne Tmp1, Tmp1, #8 ; \
+ add GlobalSize, GlobalSize, Tmp1 ; \
+ ; \
+ mov Tmp1, sp ; \
+ sub sp, GlobalSize ; \
+ mov GlobalSize, #0x0 ; \
+_InitializePrimaryStackLoop: ; \
+ cmp Tmp1, sp ; \
+ bls _InitializePrimaryStackEnd ; \
+ str GlobalSize, [Tmp1], #-4 ; \
+ b _InitializePrimaryStackLoop ; \
+_InitializePrimaryStackEnd:
#elif defined (__GNUC__)
@@ -193,7 +208,7 @@ _SetPrimaryStackEnd: #define LoadConstantToReg(Data, Reg) \
ldr Reg, =Data
-#define GetCorePositionInStack(Pos, MpId, Tmp) \
+#define GetCorePositionFromMpId(Pos, MpId, Tmp) \
lsr Pos, MpId, #6 ; \
and Tmp, MpId, #3 ; \
add Pos, Pos, Tmp
@@ -213,6 +228,22 @@ _SetPrimaryStackInitGlobals: ; \ b _SetPrimaryStackInitGlobals ; \
_SetPrimaryStackEnd:
+// Initialize the Global Variable with '0'
+#define InitializePrimaryStack(GlobalSize, Tmp1) \
+ and Tmp1, GlobalSize, #7 ; \
+ rsbne Tmp1, Tmp1, #8 ; \
+ add GlobalSize, GlobalSize, Tmp1 ; \
+ ; \
+ mov Tmp1, sp ; \
+ sub sp, GlobalSize ; \
+ mov GlobalSize, #0x0 ; \
+_InitializePrimaryStackLoop: ; \
+ cmp Tmp1, sp ; \
+ bls _InitializePrimaryStackEnd ; \
+ str GlobalSize, [Tmp1], #-4 ; \
+ b _InitializePrimaryStackLoop ; \
+_InitializePrimaryStackEnd:
+
#else
//
@@ -274,10 +305,13 @@ _SetPrimaryStackEnd: // conditional load testing eq flag
#define LoadConstantToRegIfEq(Data, Reg) LoadConstantToRegIfEqMacro Data, Reg
-#define GetCorePositionInStack(Pos, MpId, Tmp) GetCorePositionInStack Pos, MpId, Tmp
+#define GetCorePositionFromMpId(Pos, MpId, Tmp) GetCorePositionFromMpId Pos, MpId, Tmp
#define SetPrimaryStack(StackTop,GlobalSize,Tmp) SetPrimaryStack StackTop, GlobalSize, Tmp
+// Initialize the Global Variable with '0'
+#define InitializePrimaryStack(GlobalSize, Tmp1) InitializePrimaryStack GlobalSize, Tmp1
+
#endif
#endif
diff --git a/edk2/ArmPkg/Include/AsmMacroIoLib.inc b/edk2/ArmPkg/Include/AsmMacroIoLib.inc index a847579a3..1ca99fdd1 100644 --- a/edk2/ArmPkg/Include/AsmMacroIoLib.inc +++ b/edk2/ArmPkg/Include/AsmMacroIoLib.inc @@ -81,7 +81,7 @@ MEND
MACRO
- GetCorePositionInStack $Pos, $MpId, $Tmp
+ GetCorePositionFromMpId $Pos, $MpId, $Tmp
lsr $Pos, $MpId, #6
and $Tmp, $MpId, #3
add $Pos, $Pos, $Tmp
@@ -104,8 +104,25 @@ _SetPrimaryStackInitGlobals beq _SetPrimaryStackEnd
str $GlobalSize, [$Tmp], #4
b _SetPrimaryStackInitGlobals
-
_SetPrimaryStackEnd
MEND
+ MACRO
+ InitializePrimaryStack $GlobalSize, $Tmp1
+ and $Tmp1, $GlobalSize, #7
+ rsbne $Tmp1, $Tmp1, #8
+ add $GlobalSize, $GlobalSize, $Tmp1
+
+ mov $Tmp1, sp
+ sub sp, $GlobalSize
+ ; Set all the global variables to 0
+ mov $GlobalSize, #0x0
+_InitializePrimaryStackLoop
+ cmp $Tmp1, sp
+ bls _InitializePrimaryStackEnd
+ str $GlobalSize, [$Tmp1], #-4
+ b _InitializePrimaryStackLoop
+_InitializePrimaryStackEnd
+ MEND
+
END
diff --git a/edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h b/edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h index 8ae43c735..ba24bcb62 100644 --- a/edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h +++ b/edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h @@ -1,6 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -38,8 +39,7 @@ #define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
-#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)
-#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
@@ -86,27 +86,27 @@ #define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK(Secure) (TT_DESCRIPTOR_TYPE_SECTION | \
- (Secure ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(Secure) (TT_DESCRIPTOR_TYPE_SECTION | \
- (Secure ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
-#define TT_DESCRIPTOR_SECTION_UNCACHED(Secure) (TT_DESCRIPTOR_TYPE_SECTION | \
- (Secure ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_TYPE_SECTION | \
+ (NonSecure ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_TYPE_SECTION | \
+ (NonSecure ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
+#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_TYPE_SECTION | \
+ (NonSecure ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
diff --git a/edk2/ArmPkg/Include/Chipset/ArmCortexA15.h b/edk2/ArmPkg/Include/Chipset/ArmCortexA15.h new file mode 100644 index 000000000..5f7156789 --- /dev/null +++ b/edk2/ArmPkg/Include/Chipset/ArmCortexA15.h @@ -0,0 +1,25 @@ +/** @file
+
+ Copyright (c) 2012, ARM Limited. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_CORTEX_A15_H__
+#define __ARM_CORTEX_A15_H__
+
+#include <Chipset/ArmV7.h>
+
+//
+// Cortex A15 feature bit definitions
+//
+#define A15_FEATURE_SMP (1<<6)
+
+#endif
diff --git a/edk2/ArmPkg/Include/Chipset/ArmCortexA5.h b/edk2/ArmPkg/Include/Chipset/ArmCortexA5.h new file mode 100644 index 000000000..c9122709f --- /dev/null +++ b/edk2/ArmPkg/Include/Chipset/ArmCortexA5.h @@ -0,0 +1,59 @@ +/** @file + + Copyright (c) 2011, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_CORTEX_A5_H__ +#define __ARM_CORTEX_A5_H__ + +#include <Chipset/ArmV7.h> + +// +// Cortex A5 feature bit definitions +// +#define A5_FEATURE_PARITY (1<<9) +#define A5_FEATURE_AOW (1<<8) +#define A5_FEATURE_EXCL (1<<7) +#define A5_FEATURE_SMP (1<<6) +#define A5_FEATURE_FOZ (1<<3) +#define A5_FEATURE_DPREF (1<<2) +#define A5_FEATURE_HINT (1<<1) +#define A5_FEATURE_FWD (1<<0) + +// +// Cortex A5 Watchdog +// +#define ARM_A5_WATCHDOG_REGION 0x600 + +#define ARM_A5_WATCHDOG_LOAD_REGISTER 0x20 +#define ARM_A5_WATCHDOG_CONTROL_REGISTER 0x28 + +#define ARM_A5_WATCHDOG_WATCHDOG_MODE (1 << 3) +#define ARM_A5_WATCHDOG_TIMER_MODE (0 << 3) +#define ARM_A5_WATCHDOG_SINGLE_SHOT (0 << 1) +#define ARM_A5_WATCHDOG_AUTORELOAD (1 << 1) +#define ARM_A5_WATCHDOG_ENABLE 1 + +// +// SCU register offsets & masks +// +#define A5_SCU_CONTROL_OFFSET 0x0 +#define A5_SCU_CONFIG_OFFSET 0x4 +#define A5_SCU_INVALL_OFFSET 0xC +#define A5_SCU_FILT_START_OFFSET 0x40 +#define AA5SCU_FILT_END_OFFSET 0x44 +#define A5_SCU_SACR_OFFSET 0x50 +#define A5_SCU_SSACR_OFFSET 0x54 + + +#endif + diff --git a/edk2/ArmPkg/Include/Chipset/ArmV7.h b/edk2/ArmPkg/Include/Chipset/ArmV7.h index bb306a5f4..3d1b4eea4 100644 --- a/edk2/ArmPkg/Include/Chipset/ArmV7.h +++ b/edk2/ArmPkg/Include/Chipset/ArmV7.h @@ -57,6 +57,8 @@ #define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A5 0xC05
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
+
VOID
EFIAPI
ArmEnableSWPInstruction (
diff --git a/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h b/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h index 581cd9572..380ab9f22 100644 --- a/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -1,6 +1,6 @@ /** @file
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -66,8 +66,7 @@ #define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
-#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)
-#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
@@ -166,34 +165,34 @@ #define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
-#define TT_DESCRIPTOR_SECTION_DEVICE(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
-#define TT_DESCRIPTOR_SECTION_UNCACHED(Secure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
- ((Secure) ? TT_DESCRIPTOR_SECTION_NS_SECURE : TT_DESCRIPTOR_SECTION_NS_NON_SECURE ) | \
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
+#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
+#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
diff --git a/edk2/ArmPkg/Include/Library/ArmCpuLib.h b/edk2/ArmPkg/Include/Library/ArmCpuLib.h index 8de5aad63..6f92b111d 100644 --- a/edk2/ArmPkg/Include/Library/ArmCpuLib.h +++ b/edk2/ArmPkg/Include/Library/ArmCpuLib.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2011, ARM Limited. All rights reserved. + Copyright (c) 2011-2012, ARM Limited. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -15,24 +15,6 @@ #ifndef __ARMCPU_LIB__ #define __ARMCPU_LIB__ -// These are #define and not enum to be used in assembly files -#define ARM_CPU_EVENT_DEFAULT 0 -#define ARM_CPU_EVENT_BOOT_MEM_INIT 1 -#define ARM_CPU_EVENT_SECURE_INIT 2 - -typedef UINTN ARM_CPU_SYNCHRONIZE_EVENT; - - -VOID -ArmCpuSynchronizeWait ( - IN ARM_CPU_SYNCHRONIZE_EVENT Event - ); - -VOID -ArmCpuSynchronizeSignal ( - IN ARM_CPU_SYNCHRONIZE_EVENT Event - ); - VOID ArmCpuSetup ( IN UINTN MpId diff --git a/edk2/ArmPkg/Include/Library/ArmGicLib.h b/edk2/ArmPkg/Include/Library/ArmGicLib.h index 78bba23ba..6da072807 100644 --- a/edk2/ArmPkg/Include/Library/ArmGicLib.h +++ b/edk2/ArmPkg/Include/Library/ArmGicLib.h @@ -1,6 +1,6 @@ /** @file
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -72,48 +72,64 @@ //
-// GIC SEC interfaces
+// GIC Secure interfaces
//
VOID
EFIAPI
ArmGicSetupNonSecure (
+ IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
+ArmGicSetSecureInterrupts (
+ IN UINTN GicDistributorBase,
+ IN UINTN* GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
+ );
+
+VOID
+EFIAPI
ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
+ArmGicDisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
);
+UINTN
+EFIAPI
+ArmGicGetMaxNumInterrupts (
+ IN INTN GicDistributorBase
+ );
+
VOID
EFIAPI
ArmGicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
- IN INTN CPUTargetList
- );
-
-UINT32
-EFIAPI
-ArmGicAcknowledgeSgiFrom (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId
+ IN INTN CPUTargetList,
+ IN INTN SgiId
);
-UINT32
+RETURN_STATUS
EFIAPI
-ArmGicAcknowledgeSgi2From (
- IN INTN GicInterruptInterfaceBase,
- IN INTN CoreId,
- IN INTN SgiId
+ArmGicAcknowledgeInterrupt (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *CoreId,
+ OUT UINTN *InterruptId
);
UINTN
diff --git a/edk2/ArmPkg/Include/Library/ArmLib.h b/edk2/ArmPkg/Include/Library/ArmLib.h index c8f0d94ca..23beb2427 100644 --- a/edk2/ArmPkg/Include/Library/ArmLib.h +++ b/edk2/ArmPkg/Include/Library/ArmLib.h @@ -1,6 +1,7 @@ /** @file Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -47,15 +48,21 @@ typedef struct { UINTN InstructionCacheLineLength; } ARM_CACHE_INFO; +/** + * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. + * + * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only + * be used in Secure World to distinguished Secure to Non-Secure memory. + */ typedef enum { ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, - ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, - ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, - ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH, + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH, ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, - ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE } ARM_MEMORY_REGION_ATTRIBUTES; #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) @@ -70,24 +77,50 @@ typedef struct { typedef VOID (*CACHE_OPERATION)(VOID); typedef VOID (*LINE_OPERATION)(UINTN); +// +// ARM Processor Mode +// typedef enum { ARM_PROCESSOR_MODE_USER = 0x10, ARM_PROCESSOR_MODE_FIQ = 0x11, ARM_PROCESSOR_MODE_IRQ = 0x12, ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, ARM_PROCESSOR_MODE_ABORT = 0x17, + ARM_PROCESSOR_MODE_HYP = 0x1A, ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, ARM_PROCESSOR_MODE_SYSTEM = 0x1F, ARM_PROCESSOR_MODE_MASK = 0x1F } ARM_PROCESSOR_MODE; +// +// ARM Cpu IDs +// +#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24) +#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24) +#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24) +#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24) +#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24) +#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24) + +#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4) +#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4) + +// +// ARM MP Core IDs +// #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) -#define GET_CORE_ID(MpId) ((MpId) & 0x3) -#define GET_CLUSTER_ID(MpId) (((MpId) >> 8) & 0x3C) +#define ARM_CORE_MASK 0xFF +#define ARM_CLUSTER_MASK (0xFF << 8) +#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK) +#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8) // Get the position of the core for the Stack Offset (4 Core per Cluster) // Position = (ClusterId * 4) + CoreId -#define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3)) -#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0x3) +#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK)) +#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) ARM_CACHE_TYPE EFIAPI @@ -437,6 +470,24 @@ ArmSetAuxCrBit ( VOID EFIAPI +ArmUnsetAuxCrBit ( + IN UINT32 Bits + ); + +VOID +EFIAPI +ArmCallSEV ( + VOID + ); + +VOID +EFIAPI +ArmCallWFE ( + VOID + ); + +VOID +EFIAPI ArmCallWFI ( VOID ); @@ -447,9 +498,15 @@ ArmReadMpidr ( VOID ); +UINT32 +EFIAPI +ArmReadCpacr ( + VOID + ); + VOID EFIAPI -ArmWriteCPACR ( +ArmWriteCpacr ( IN UINT32 Access ); @@ -459,22 +516,46 @@ ArmEnableVFP ( VOID ); +UINT32 +EFIAPI +ArmReadNsacr ( + VOID + ); + VOID EFIAPI ArmWriteNsacr ( IN UINT32 SetWayFormat ); +UINT32 +EFIAPI +ArmReadScr ( + VOID + ); + VOID EFIAPI ArmWriteScr ( IN UINT32 SetWayFormat ); +UINT32 +EFIAPI +ArmReadMVBar ( + VOID + ); + VOID EFIAPI -ArmWriteVMBar ( +ArmWriteMVBar ( IN UINT32 VectorMonitorBase ); +UINT32 +EFIAPI +ArmReadSctlr ( + VOID + ); + #endif // __ARM_LIB__ diff --git a/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c index d4602738e..8c1fe415d 100644 --- a/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c +++ b/edk2/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c @@ -54,7 +54,7 @@ TimerConstructor ( ASSERT (TimerFreq);
} else {
- DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, Hence cann't use this library \n"));
+ DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library can not be used.\n"));
ASSERT (0);
}
@@ -79,7 +79,7 @@ MicroSecondDelay ( UINT64 TimerTicks64;
UINT64 SystemCounterVal;
- // Calculate counter ticks that can represent requsted delay
+ // Calculate counter ticks that can represent requested delay
TimerTicks64 = MultU64x32 (MicroSeconds, TICKS_PER_MICRO_SEC);
// Read System Counter value
@@ -106,7 +106,7 @@ MicroSecondDelay ( @param NanoSeconds The minimum number of nanoseconds to delay.
- @return The value of NanoSeconds inputted.
+ @return The value of NanoSeconds inputed.
**/
UINTN
diff --git a/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf b/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf index c63a4dfe2..56ba2d2f3 100644 --- a/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf +++ b/edk2/ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf @@ -31,7 +31,6 @@ ArmPkg/ArmPkg.dec
[LibraryClasses]
- UefiLib
BaseLib
PrintLib
DebugLib
diff --git a/edk2/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/edk2/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index 4764b4237..074e3c125 100755 --- a/edk2/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/edk2/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -102,7 +102,9 @@ DmaMap ( }
// If the mapped buffer is not an uncached buffer
- if (GcdDescriptor.Attributes != EFI_MEMORY_UC) {
+ if ( (GcdDescriptor.Attributes != EFI_MEMORY_WC) &&
+ (GcdDescriptor.Attributes != EFI_MEMORY_UC) )
+ {
//
// If the buffer does not fill entire cache lines we must double buffer into
// uncached memory. Device (PCI) address becomes uncached page.
@@ -129,7 +131,7 @@ DmaMap ( if ((Operation == MapOperationBusMasterRead) || (Operation == MapOperationBusMasterCommonBuffer)) {
// In case the buffer is used for instance to send command to a PCI controller, we must ensure the memory is uncached
- Status = gDS->SetMemorySpaceAttributes (ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB), ALIGN_VALUE(*NumberOfBytes,BASE_4KB), EFI_MEMORY_UC);
+ Status = gDS->SetMemorySpaceAttributes (ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB), ALIGN_VALUE(*NumberOfBytes,BASE_4KB), EFI_MEMORY_WC);
ASSERT_EFI_ERROR (Status);
}
}
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c index 1257be8cf..86427035e 100644 --- a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c +++ b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c @@ -39,13 +39,13 @@ FillTranslationTable ( case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1); break; default: diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c index 6b698a335..7c3a384a9 100644 --- a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c +++ b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c @@ -40,9 +40,9 @@ FillTranslationTable ( case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED; break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK: - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH: - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: ASSERT(0); // Trustzone is not supported on ARMv5 default: Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED; diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm index 39d6c8593..a5ff6b261 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm @@ -97,4 +97,4 @@ ReadCLIDR mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
-END
+ END
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c index 1cba12d30..7835b414c 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c @@ -83,7 +83,7 @@ ArmArchTimerReadReg ( case CnthpTval: case CnthpCtl: case CnthpCval: - DEBUG ((EFI_D_ERROR, "The register is related to Hyperviser Mode. Can't perform requested operation\n ")); + DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n ")); break; default: diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index 69f360c3a..6fa770edb 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -41,19 +41,19 @@ PopulateLevel2PageTable ( switch (Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
break;
default:
@@ -146,16 +146,16 @@ FillTranslationTable ( case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
break;
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
break;
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
break;
- case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
break;
default:
@@ -214,7 +214,7 @@ ArmConfigureMmu ( *TranslationTableBase = (VOID *)TranslationTable;
}
- if (TranslationTableBase != NULL) {
+ if (TranslationTableSize != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
}
@@ -245,20 +245,20 @@ ArmConfigureMmu ( // Translate the Memory Attributes into Translation Table Register Attributes
if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED)) {
+ (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
TTBRAttributes = TTBR_NON_CACHEABLE;
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK)) {
+ (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
- (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH)) {
+ (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;
} else {
//TODO: We should raise an error here
TTBRAttributes = TTBR_NON_CACHEABLE;
}
- ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & 0xFFFFC000) | (TTBRAttributes & 0x7F)));
+ ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 5ac355240..910e50e40 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -42,6 +42,7 @@ GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation) GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
+GCC_ASM_EXPORT (ArmReadVBar)
GCC_ASM_EXPORT (ArmWriteVBar)
GCC_ASM_EXPORT (ArmEnableVFP)
GCC_ASM_EXPORT (ArmCallWFI)
@@ -330,6 +331,11 @@ ASM_PFX(ArmInstructionSynchronizationBarrier): isb
bx LR
+ASM_PFX(ArmReadVBar):
+ # Set the Address of the Vector Table in the VBAR register
+ mrc p15, 0, r0, c12, c0, 0
+ bx lr
+
ASM_PFX(ArmWriteVBar):
# Set the Address of the Vector Table in the VBAR register
mcr p15, 0, r0, c12, c0, 0
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 28a4564ac..803540059 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -39,6 +39,7 @@ EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
+ EXPORT ArmReadVBar
EXPORT ArmWriteVBar
EXPORT ArmEnableVFP
EXPORT ArmCallWFI
@@ -324,6 +325,11 @@ ArmInstructionSynchronizationBarrier isb
bx LR
+ArmReadVBar
+ // Set the Address of the Vector Table in the VBAR register
+ mrc p15, 0, r0, c12, c0, 0
+ bx lr
+
ArmWriteVBar
// Set the Address of the Vector Table in the VBAR register
mcr p15, 0, r0, c12, c0, 0
@@ -341,6 +347,7 @@ ArmEnableVFP orr r0, r0, #0x00f00000
// Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2
+ isb
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000
mcr p10,#0x7,r0,c8,c0,#0
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c b/edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c index ae1b78560..a7b9551ba 100644 --- a/edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c +++ b/edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c @@ -1,6 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -70,3 +71,13 @@ ArmSetAuxCrBit ( ArmWriteAuxCr(val);
}
+VOID
+EFIAPI
+ArmUnsetAuxCrBit (
+ IN UINT32 Bits
+ )
+{
+ UINT32 val = ArmReadAuxCr();
+ val &= ~Bits;
+ ArmWriteAuxCr(val);
+}
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S index edd94d299..b19185412 100644 --- a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S +++ b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -32,14 +32,21 @@ GCC_ASM_EXPORT(ArmSetTTBR0) GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead)
-GCC_ASM_EXPORT(ArmWriteCPACR)
+GCC_ASM_EXPORT(ArmReadCpacr)
+GCC_ASM_EXPORT(ArmWriteCpacr)
GCC_ASM_EXPORT(ArmWriteAuxCr)
GCC_ASM_EXPORT(ArmReadAuxCr)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
+GCC_ASM_EXPORT(ArmReadNsacr)
GCC_ASM_EXPORT(ArmWriteNsacr)
+GCC_ASM_EXPORT(ArmReadScr)
GCC_ASM_EXPORT(ArmWriteScr)
-GCC_ASM_EXPORT(ArmWriteVMBar)
+GCC_ASM_EXPORT(ArmReadMVBar)
+GCC_ASM_EXPORT(ArmWriteMVBar)
+GCC_ASM_EXPORT(ArmCallWFE)
+GCC_ASM_EXPORT(ArmCallSEV)
+GCC_ASM_EXPORT(ArmReadSctlr)
#------------------------------------------------------------------------------
@@ -86,8 +93,13 @@ ASM_PFX(CPSRRead): mrs r0, cpsr
bx lr
-ASM_PFX(ArmWriteCPACR):
+ASM_PFX(ArmReadCpacr):
+ mrc p15, 0, r0, c1, c0, 2
+ bx lr
+
+ASM_PFX(ArmWriteCpacr):
mcr p15, 0, r0, c1, c0, 2
+ isb
bx lr
ASM_PFX(ArmWriteAuxCr):
@@ -133,16 +145,40 @@ ASM_PFX(ArmInvalidateTlb): isb
bx lr
+ASM_PFX(ArmReadNsacr):
+ mrc p15, 0, r0, c1, c1, 2
+ bx lr
+
ASM_PFX(ArmWriteNsacr):
mcr p15, 0, r0, c1, c1, 2
bx lr
+ASM_PFX(ArmReadScr):
+ mrc p15, 0, r0, c1, c1, 0
+ bx lr
+
ASM_PFX(ArmWriteScr):
mcr p15, 0, r0, c1, c1, 0
bx lr
-ASM_PFX(ArmWriteVMBar):
+ASM_PFX(ArmReadMVBar):
+ mrc p15, 0, r0, c12, c0, 1
+ bx lr
+
+ASM_PFX(ArmWriteMVBar):
mcr p15, 0, r0, c12, c0, 1
bx lr
+ASM_PFX(ArmCallWFE):
+ wfe
+ bx lr
+
+ASM_PFX(ArmCallSEV):
+ sev
+ bx lr
+
+ASM_PFX(ArmReadSctlr):
+ mrc p15, 0, R0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+ bx lr
+
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm index 3f603873f..fd0f332bd 100644 --- a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm +++ b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm @@ -1,7 +1,7 @@ //------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011, ARM Limited. All rights reserved.
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -32,14 +32,21 @@ EXPORT ArmSetDomainAccessControl
EXPORT CPSRMaskInsert
EXPORT CPSRRead
- EXPORT ArmWriteCPACR
+ EXPORT ArmReadCpacr
+ EXPORT ArmWriteCpacr
EXPORT ArmWriteAuxCr
EXPORT ArmReadAuxCr
EXPORT ArmInvalidateTlb
EXPORT ArmUpdateTranslationTableEntry
+ EXPORT ArmReadNsacr
EXPORT ArmWriteNsacr
+ EXPORT ArmReadScr
EXPORT ArmWriteScr
- EXPORT ArmWriteVMBar
+ EXPORT ArmReadMVBar
+ EXPORT ArmWriteMVBar
+ EXPORT ArmCallWFE
+ EXPORT ArmCallSEV
+ EXPORT ArmReadSctlr
AREA ArmLibSupport, CODE, READONLY
@@ -86,8 +93,13 @@ CPSRRead mrs r0, cpsr
bx lr
-ArmWriteCPACR
+ArmReadCpacr
+ mrc p15, 0, r0, c1, c0, 2
+ bx lr
+
+ArmWriteCpacr
mcr p15, 0, r0, c1, c0, 2
+ isb
bx lr
ArmWriteAuxCr
@@ -133,16 +145,40 @@ ArmInvalidateTlb isb
bx lr
+ArmReadNsacr
+ mrc p15, 0, r0, c1, c1, 2
+ bx lr
+
ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr
+ArmReadScr
+ mrc p15, 0, r0, c1, c1, 0
+ bx lr
+
ArmWriteScr
mcr p15, 0, r0, c1, c1, 0
bx lr
-ArmWriteVMBar
+ArmReadMVBar
+ mrc p15, 0, r0, c12, c0, 1
+ bx lr
+
+ArmWriteMVBar
mcr p15, 0, r0, c12, c0, 1
bx lr
+ArmCallWFE
+ wfe
+ blx lr
+
+ArmCallSEV
+ sev
+ blx lr
+
+ArmReadSctlr
+ mrc p15, 0, R0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
+ bx lr
+
END
diff --git a/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S b/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S index 8a61a6b44..49ebf3c2f 100755 --- a/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S +++ b/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S @@ -58,7 +58,6 @@ L31: orr r4, r4, r4, LSL #8
orr r4, r4, r4, LSL #16
mov r5, r4
- mov r5, r4
mov r6, r4
mov r7, r4
mov r8, r4
@@ -79,4 +78,4 @@ L43: cmp r1, #0
bne L34
ldmfd sp!, {r4-r11, pc}
-
\ No newline at end of file +
diff --git a/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm b/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm index 7222cf9b7..3cc753ccc 100755 --- a/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm +++ b/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm @@ -57,7 +57,6 @@ L31 orr r4, r4, r4, LSL #8
orr r4, r4, r4, LSL #16
mov r5, r4
- mov r5, r4
mov r6, r4
mov r7, r4
mov r8, r4
@@ -80,4 +79,3 @@ L43 ldmfd sp!, {r4-r11, pc}
END
-
\ No newline at end of file diff --git a/edk2/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf b/edk2/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf index 9a7b18b25..7d82b12ab 100755 --- a/edk2/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf +++ b/edk2/ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf @@ -32,7 +32,7 @@ #
-[Sources.ARM]
+[Sources.Common]
ScanMem64Wrapper.c
ScanMem32Wrapper.c
ScanMem16Wrapper.c
@@ -47,6 +47,8 @@ MemLibGeneric.c
MemLibGuid.c
MemLibInternals.h
+
+[Sources.ARM]
Arm/CopyMem.asm
Arm/CopyMem.S
Arm/SetMem.asm
diff --git a/edk2/ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c b/edk2/ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c index d4e504a01..1d90a8bca 100755 --- a/edk2/ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c +++ b/edk2/ArmPkg/Library/BaseMemoryLibStm/MemLibGuid.c @@ -81,17 +81,7 @@ CompareGuid ( IN CONST GUID *Guid2
)
{
- UINT64 LowPartOfGuid1;
- UINT64 LowPartOfGuid2;
- UINT64 HighPartOfGuid1;
- UINT64 HighPartOfGuid2;
-
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
-
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
+ return (CompareMem(Guid1, Guid2, sizeof(GUID)) == 0) ? TRUE : FALSE;
}
/**
diff --git a/edk2/ArmPkg/Library/BaseMemoryLibVstm/MemLibGuid.c b/edk2/ArmPkg/Library/BaseMemoryLibVstm/MemLibGuid.c index d4e504a01..748c80ead 100755 --- a/edk2/ArmPkg/Library/BaseMemoryLibVstm/MemLibGuid.c +++ b/edk2/ArmPkg/Library/BaseMemoryLibVstm/MemLibGuid.c @@ -81,17 +81,7 @@ CompareGuid ( IN CONST GUID *Guid2
)
{
- UINT64 LowPartOfGuid1;
- UINT64 LowPartOfGuid2;
- UINT64 HighPartOfGuid1;
- UINT64 HighPartOfGuid2;
-
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
-
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
+ return (CompareMem(Guid1, Guid2, sizeof(GUID) == 0)) ? TRUE : FALSE;
}
/**
diff --git a/edk2/ArmPkg/Library/BdsLib/BdsAppLoader.c b/edk2/ArmPkg/Library/BdsLib/BdsAppLoader.c index 4f359cda1..2d7f96e28 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsAppLoader.c +++ b/edk2/ArmPkg/Library/BdsLib/BdsAppLoader.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License diff --git a/edk2/ArmPkg/Library/BdsLib/BdsFilePath.c b/edk2/ArmPkg/Library/BdsLib/BdsFilePath.c index 88596c7c6..a8b77a3d2 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsFilePath.c +++ b/edk2/ArmPkg/Library/BdsLib/BdsFilePath.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License diff --git a/edk2/ArmPkg/Library/BdsLib/BdsHelper.c b/edk2/ArmPkg/Library/BdsLib/BdsHelper.c index d971a76b7..29cc12bd3 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsHelper.c +++ b/edk2/ArmPkg/Library/BdsLib/BdsHelper.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -43,6 +43,8 @@ ShutdownUefiBootServices ( MemoryMap = NULL; MemoryMapSize = 0; + Pages = 0; + do { Status = gBS->GetMemoryMap ( &MemoryMapSize, @@ -66,17 +68,18 @@ ShutdownUefiBootServices ( &DescriptorSize, &DescriptorVersion ); - // Don't do anything between the GetMemoryMap() and ExitBootServices() - if (!EFI_ERROR (Status)) { - Status = gBS->ExitBootServices (gImageHandle, MapKey); - if (EFI_ERROR (Status)) { - FreePages (MemoryMap, Pages); - MemoryMap = NULL; - MemoryMapSize = 0; - } + } + + // Don't do anything between the GetMemoryMap() and ExitBootServices() + if (!EFI_ERROR(Status)) { + Status = gBS->ExitBootServices (gImageHandle, MapKey); + if (EFI_ERROR(Status)) { + FreePages (MemoryMap, Pages); + MemoryMap = NULL; + MemoryMapSize = 0; } } - } while (EFI_ERROR (Status)); + } while (EFI_ERROR(Status)); return Status; } diff --git a/edk2/ArmPkg/Library/BdsLib/BdsInternal.h b/edk2/ArmPkg/Library/BdsLib/BdsInternal.h index 80d21b21e..85f9f4159 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsInternal.h +++ b/edk2/ArmPkg/Library/BdsLib/BdsInternal.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -31,6 +31,7 @@ #include <Library/PrintLib.h> #include <Library/UefiRuntimeServicesTableLib.h> +#include <Guid/ArmMpCoreInfo.h> #include <Guid/GlobalVariable.h> #include <Guid/FileInfo.h> @@ -41,7 +42,7 @@ #include <Protocol/LoadFile.h> #include <Protocol/PxeBaseCode.h> -#include "BdsLinuxLoader.h" +#include <Uefi.h> typedef BOOLEAN (*BDS_FILE_LOADER_SUPPORT) ( IN EFI_DEVICE_PATH *DevicePath, @@ -94,22 +95,4 @@ BdsLoadImage ( OUT UINTN *FileSize ); -EFI_STATUS -PrepareAtagList ( - IN CONST CHAR8* CommandLineString, - IN EFI_PHYSICAL_ADDRESS InitrdImage, - IN UINTN InitrdImageSize, - OUT EFI_PHYSICAL_ADDRESS *AtagBase, - OUT UINT32 *AtagSize - ); - -EFI_STATUS -PrepareFdt ( - IN CONST CHAR8* CommandLineString, - IN EFI_PHYSICAL_ADDRESS InitrdImage, - IN UINTN InitrdImageSize, - IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase, - IN OUT UINT32 *FdtBlobSize - ); - #endif diff --git a/edk2/ArmPkg/Library/BdsLib/BdsLib.inf b/edk2/ArmPkg/Library/BdsLib/BdsLib.inf index b3cab21d1..9dee03a79 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsLib.inf +++ b/edk2/ArmPkg/Library/BdsLib/BdsLib.inf @@ -1,5 +1,6 @@ #/* @file -# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -67,10 +68,10 @@ gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdArmMachineType + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset + gArmTokenSpaceGuid.PcdArmLinuxKernelFixedOffset gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset -[Pcd] - [Depex] TRUE diff --git a/edk2/ArmPkg/Library/BdsLib/BdsLinuxAtag.c b/edk2/ArmPkg/Library/BdsLib/BdsLinuxAtag.c index 8c16bc0ec..b59df0762 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsLinuxAtag.c +++ b/edk2/ArmPkg/Library/BdsLib/BdsLinuxAtag.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -13,6 +13,7 @@ **/ #include "BdsInternal.h" +#include "BdsLinuxLoader.h" // Point to the current ATAG STATIC LINUX_ATAG *mLinuxKernelCurrentAtag; @@ -80,6 +81,22 @@ SetupCmdlineTag ( STATIC VOID +SetupInitrdTag ( + IN UINT32 InitrdImage, + IN UINT32 InitrdImageSize + ) +{ + mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_INITRD2); + mLinuxKernelCurrentAtag->header.type = ATAG_INITRD2; + + mLinuxKernelCurrentAtag->body.initrd2_tag.start = InitrdImage; + mLinuxKernelCurrentAtag->body.initrd2_tag.size = InitrdImageSize; + + // Move pointer to next tag + mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag); +} +STATIC +VOID SetupEndTag ( VOID ) @@ -114,7 +131,7 @@ PrepareAtagList ( AtagStartAddress = LINUX_ATAG_MAX_OFFSET; Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(ATAG_MAX_SIZE), &AtagStartAddress); if (EFI_ERROR(Status)) { - DEBUG ((EFI_D_ERROR,"Failed to allocate Atag at 0x%lX (%r)\n",AtagStartAddress,Status)); + DEBUG ((EFI_D_WARN, "Warning: Failed to allocate Atag at 0x%lX (%r). The Atag will be allocated somewhere else in System Memory.\n", AtagStartAddress, Status)); Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(ATAG_MAX_SIZE), &AtagStartAddress); ASSERT_EFI_ERROR(Status); } @@ -141,14 +158,7 @@ PrepareAtagList ( } if (InitrdImageSize > 0 && InitrdImage != 0) { - mLinuxKernelCurrentAtag->header.size = tag_size(LINUX_ATAG_INITRD2); - mLinuxKernelCurrentAtag->header.type = ATAG_INITRD2; - - mLinuxKernelCurrentAtag->body.initrd2_tag.start = (UINT32)InitrdImage; - mLinuxKernelCurrentAtag->body.initrd2_tag.size = (UINT32)InitrdImageSize; - - // Move pointer to next tag - mLinuxKernelCurrentAtag = next_tag_address(mLinuxKernelCurrentAtag); + SetupInitrdTag ((UINT32)InitrdImage, (UINT32)InitrdImageSize); } // End of tags diff --git a/edk2/ArmPkg/Library/BdsLib/BdsLinuxFdt.c b/edk2/ArmPkg/Library/BdsLib/BdsLinuxFdt.c index 2b1296a98..fa06287b1 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsLinuxFdt.c +++ b/edk2/ArmPkg/Library/BdsLib/BdsLinuxFdt.c @@ -1,357 +1,368 @@ -/** @file -* -* Copyright (c) 2011-2012, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include <Library/PcdLib.h> -#include <libfdt.h> - -#include "BdsInternal.h" - -#define LINUX_FDT_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset)) - -#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) -#define PALIGN(p, a) ((void *)(ALIGN((unsigned long)(p), (a)))) -#define GET_CELL(p) (p += 4, *((const UINT32 *)(p-4))) - -STATIC -UINTN -IsPrintableString ( - IN CONST VOID* data, - IN UINTN len - ) -{ - CONST CHAR8 *s = data; - CONST CHAR8 *ss; - - // zero length is not - if (len == 0) { - return 0; - } - - // must terminate with zero - if (s[len - 1] != '\0') { - return 0; - } - - ss = s; - while (*s/* && isprint(*s)*/) { - s++; - } - - // not zero, or not done yet - if (*s != '\0' || (s + 1 - ss) < len) { - return 0; - } - - return 1; -} - -STATIC -VOID -PrintData ( - IN CONST CHAR8* data, - IN UINTN len - ) -{ - UINTN i; - CONST CHAR8 *p = data; - - // no data, don't print - if (len == 0) - return; - - if (IsPrintableString (data, len)) { - Print(L" = \"%a\"", (const char *)data); - } else if ((len % 4) == 0) { - Print(L" = <"); - for (i = 0; i < len; i += 4) { - Print(L"0x%08x%a", fdt32_to_cpu(GET_CELL(p)),i < (len - 4) ? " " : ""); - } - Print(L">"); - } else { - Print(L" = ["); - for (i = 0; i < len; i++) - Print(L"%02x%a", *p++, i < len - 1 ? " " : ""); - Print(L"]"); - } -} - -VOID -DebugDumpFdt ( - IN VOID* FdtBlob - ) -{ - struct fdt_header *bph; - UINT32 off_dt; - UINT32 off_str; - CONST CHAR8* p_struct; - CONST CHAR8* p_strings; - CONST CHAR8* p; - CONST CHAR8* s; - CONST CHAR8* t; - UINT32 tag; - UINTN sz; - UINTN depth; - UINTN shift; - UINT32 version; - - depth = 0; - shift = 4; - - bph = FdtBlob; - off_dt = fdt32_to_cpu(bph->off_dt_struct); - off_str = fdt32_to_cpu(bph->off_dt_strings); - p_struct = (CONST CHAR8*)FdtBlob + off_dt; - p_strings = (CONST CHAR8*)FdtBlob + off_str; - version = fdt32_to_cpu(bph->version); - - p = p_struct; - while ((tag = fdt32_to_cpu(GET_CELL(p))) != FDT_END) { - - //printf("tag: 0x%08x (%d)\n", tag, p - p_struct); - - if (tag == FDT_BEGIN_NODE) { - s = p; - p = PALIGN(p + AsciiStrLen (s) + 1, 4); - - if (*s == '\0') - s = "/"; - - Print(L"%*s%a {\n", depth * shift, L" ", s); - - depth++; - continue; - } - - if (tag == FDT_END_NODE) { - depth--; - - Print(L"%*s};\n", depth * shift, L" "); - continue; - } - - if (tag == FDT_NOP) { - Print(L"%*s// [NOP]\n", depth * shift, L" "); - continue; - } - - if (tag != FDT_PROP) { - Print(L"%*s ** Unknown tag 0x%08x\n", depth * shift, L" ", tag); - break; - } - sz = fdt32_to_cpu(GET_CELL(p)); - s = p_strings + fdt32_to_cpu(GET_CELL(p)); - if (version < 16 && sz >= 8) - p = PALIGN(p, 8); - t = p; - - p = PALIGN(p + sz, 4); - - Print(L"%*s%a", depth * shift, L" ", s); - PrintData(t, sz); - Print(L";\n"); - } -} - -typedef struct { - UINTN Base; - UINTN Size; -} FdtRegion; - -EFI_STATUS -PrepareFdt ( - IN CONST CHAR8* CommandLineString, - IN EFI_PHYSICAL_ADDRESS InitrdImage, - IN UINTN InitrdImageSize, - IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase, - IN OUT UINT32 *FdtBlobSize - ) -{ - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS NewFdtBlobBase; - UINTN NewFdtBlobSize; - VOID* fdt; - INTN err; - INTN node; - INTN cpu_node; - INTN lenp; - CONST VOID* BootArg; - EFI_PHYSICAL_ADDRESS InitrdImageStart; - EFI_PHYSICAL_ADDRESS InitrdImageEnd; - FdtRegion Region; - UINTN Index; - CHAR8 Name[10]; - LIST_ENTRY ResourceList; - BDS_SYSTEM_MEMORY_RESOURCE *Resource; - ARM_PROCESSOR_TABLE *ArmProcessorTable; - ARM_CORE_INFO *ArmCoreInfoTable; - UINT32 MpId; - UINT32 ClusterId; - UINT32 CoreId; - UINT64 CpuReleaseAddr; - - err = fdt_check_header ((VOID*)(UINTN)(*FdtBlobBase)); - if (err != 0) { - Print (L"ERROR: Device Tree header not valid (err:%d)\n", err); - return EFI_INVALID_PARAMETER; - } - - // Allocate memory for the new FDT - NewFdtBlobBase = LINUX_FDT_MAX_OFFSET; - NewFdtBlobSize = *FdtBlobSize + FDT_ADDITIONAL_ENTRIES_SIZE; - Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); - if (EFI_ERROR(Status)) { - DEBUG ((EFI_D_WARN, "Warning: Failed to allocate Fdt below 0x%lX (%r). The Fdt will be allocated somewhere else in System Memory.\n",NewFdtBlobBase,Status)); - Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); - ASSERT_EFI_ERROR(Status); - goto FAIL_NEW_FDT; - } - - // Load the Original FDT tree into the new region - fdt = (VOID*)(UINTN)NewFdtBlobBase; - err = fdt_open_into((VOID*)(UINTN)(*FdtBlobBase), fdt, NewFdtBlobSize); - if (err) { - DEBUG((EFI_D_ERROR, "fdt_open_into(): %a\n", fdt_strerror(err))); - Status = EFI_INVALID_PARAMETER; - goto FAIL_NEW_FDT; - } - -#if 0 - DEBUG_CODE_BEGIN(); - DebugDumpFdt (fdt); - DEBUG_CODE_END(); -#endif - - node = fdt_subnode_offset(fdt, 0, "chosen"); - if (node < 0) { - // The 'chosen' node does not exist, create it - node = fdt_add_subnode(fdt, 0, "chosen"); - if (node < 0) { - DEBUG((EFI_D_ERROR,"Error on finding 'chosen' node\n")); - Status = EFI_INVALID_PARAMETER; - goto FAIL_NEW_FDT; - } - } - - DEBUG_CODE_BEGIN(); - BootArg = fdt_getprop(fdt, node, "bootargs", &lenp); - if (BootArg != NULL) { - DEBUG((EFI_D_ERROR,"BootArg: %a\n",BootArg)); - } - DEBUG_CODE_END(); - - // Set Linux CmdLine - if ((CommandLineString != NULL) && (AsciiStrLen (CommandLineString) > 0)) { - err = fdt_setprop(fdt, node, "bootargs", CommandLineString, AsciiStrSize(CommandLineString)); - if (err) { - DEBUG((EFI_D_ERROR,"Fail to set new 'bootarg' (err:%d)\n",err)); - } - } - - // Set Linux Initrd - if (InitrdImageSize != 0) { - InitrdImageStart = cpu_to_fdt64 (InitrdImage); - err = fdt_setprop(fdt, node, "linux,initrd-start", &InitrdImageStart, sizeof(EFI_PHYSICAL_ADDRESS)); - if (err) { - DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err)); - } - InitrdImageEnd = cpu_to_fdt64 (InitrdImage + InitrdImageSize); - err = fdt_setprop(fdt, node, "linux,initrd-end", &InitrdImageEnd, sizeof(EFI_PHYSICAL_ADDRESS)); - if (err) { - DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err)); - } - } - - // Set Physical memory setup if does not exist - node = fdt_subnode_offset(fdt, 0, "memory"); - if (node < 0) { - // The 'chosen' node does not exist, create it - node = fdt_add_subnode(fdt, 0, "memory"); - if (node >= 0) { - fdt_setprop_string(fdt, node, "name", "memory"); - fdt_setprop_string(fdt, node, "device_type", "memory"); - - GetSystemMemoryResources (&ResourceList); - Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceList.ForwardLink; - - if (sizeof(UINTN) == sizeof(UINT32)) { - Region.Base = cpu_to_fdt32((UINTN)Resource->PhysicalStart); - Region.Size = cpu_to_fdt32((UINTN)Resource->ResourceLength); - } else { - Region.Base = cpu_to_fdt64((UINTN)Resource->PhysicalStart); - Region.Size = cpu_to_fdt64((UINTN)Resource->ResourceLength); - } - - err = fdt_setprop(fdt, node, "reg", &Region, sizeof(Region)); - if (err) { - DEBUG((EFI_D_ERROR,"Fail to set new 'memory region' (err:%d)\n",err)); - } - } - } - - // Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms - for (Index=0; Index < gST->NumberOfTableEntries; Index++) { - // Check for correct GUID type - if (CompareGuid (&gArmMpCoreInfoGuid, &(gST->ConfigurationTable[Index].VendorGuid))) { - MpId = ArmReadMpidr (); - ClusterId = GET_CLUSTER_ID(MpId); - CoreId = GET_CORE_ID(MpId); - - node = fdt_subnode_offset(fdt, 0, "cpus"); - if (node < 0) { - // Create the /cpus node - node = fdt_add_subnode(fdt, 0, "cpus"); - fdt_setprop_string(fdt, node, "name", "cpus"); - fdt_setprop_cell(fdt, node, "#address-cells", 1); - fdt_setprop_cell(fdt, node, "#size-cells", 0); - } - - // Get pointer to ARM processor table - ArmProcessorTable = (ARM_PROCESSOR_TABLE *)gST->ConfigurationTable[Index].VendorTable; - ArmCoreInfoTable = ArmProcessorTable->ArmCpus; - - for (Index = 0; Index < ArmProcessorTable->NumberOfEntries; Index++) { - if (((ArmCoreInfoTable[Index].ClusterId != ClusterId) || (ArmCoreInfoTable[Index].CoreId != CoreId))) { - AsciiSPrint (Name, 10, "cpu@%d", Index); - cpu_node = fdt_subnode_offset(fdt, node, Name); - if (cpu_node < 0) { - cpu_node = fdt_add_subnode(fdt, node, Name); - } - fdt_setprop_string(fdt, cpu_node, "device-type", "cpu"); - fdt_setprop_string(fdt, cpu_node, "enable-method", "spin-table"); - fdt_setprop_string(fdt, cpu_node, "status", "disabled"); - CpuReleaseAddr = cpu_to_fdt64(ArmCoreInfoTable[Index].MailboxSetAddress); - fdt_setprop(fdt, cpu_node, "cpu-release-addr", &CpuReleaseAddr, sizeof(CpuReleaseAddr)); - } - } - break; - } - } - -#if 0 - DEBUG_CODE_BEGIN(); - DebugDumpFdt (fdt); - DEBUG_CODE_END(); -#endif - - *FdtBlobBase = NewFdtBlobBase; - *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(NewFdtBlobBase));; - return EFI_SUCCESS; - -FAIL_NEW_FDT: - *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(*FdtBlobBase)); - // Return success even if we failed to update the FDT blob. The original one is still valid. - return EFI_SUCCESS; -} - - +/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/PcdLib.h>
+#include <libfdt.h>
+
+#include "BdsInternal.h"
+#include "BdsLinuxLoader.h"
+
+#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1))
+#define PALIGN(p, a) ((void *)(ALIGN((unsigned long)(p), (a))))
+#define GET_CELL(p) (p += 4, *((const UINT32 *)(p-4)))
+
+STATIC
+UINTN
+IsPrintableString (
+ IN CONST VOID* data,
+ IN UINTN len
+ )
+{
+ CONST CHAR8 *s = data;
+ CONST CHAR8 *ss;
+
+ // Zero length is not
+ if (len == 0) {
+ return 0;
+ }
+
+ // Must terminate with zero
+ if (s[len - 1] != '\0') {
+ return 0;
+ }
+
+ ss = s;
+ while (*s/* && isprint(*s)*/) {
+ s++;
+ }
+
+ // Not zero, or not done yet
+ if (*s != '\0' || (s + 1 - ss) < len) {
+ return 0;
+ }
+
+ return 1;
+}
+
+STATIC
+VOID
+PrintData (
+ IN CONST CHAR8* data,
+ IN UINTN len
+ )
+{
+ UINTN i;
+ CONST CHAR8 *p = data;
+
+ // No data, don't print
+ if (len == 0)
+ return;
+
+ if (IsPrintableString (data, len)) {
+ Print(L" = \"%a\"", (const char *)data);
+ } else if ((len % 4) == 0) {
+ Print(L" = <");
+ for (i = 0; i < len; i += 4) {
+ Print(L"0x%08x%a", fdt32_to_cpu(GET_CELL(p)),i < (len - 4) ? " " : "");
+ }
+ Print(L">");
+ } else {
+ Print(L" = [");
+ for (i = 0; i < len; i++)
+ Print(L"%02x%a", *p++, i < len - 1 ? " " : "");
+ Print(L"]");
+ }
+}
+
+VOID
+DebugDumpFdt (
+ IN VOID* FdtBlob
+ )
+{
+ struct fdt_header *bph;
+ UINT32 off_dt;
+ UINT32 off_str;
+ CONST CHAR8* p_struct;
+ CONST CHAR8* p_strings;
+ CONST CHAR8* p;
+ CONST CHAR8* s;
+ CONST CHAR8* t;
+ UINT32 tag;
+ UINTN sz;
+ UINTN depth;
+ UINTN shift;
+ UINT32 version;
+
+ depth = 0;
+ shift = 4;
+
+ bph = FdtBlob;
+ off_dt = fdt32_to_cpu(bph->off_dt_struct);
+ off_str = fdt32_to_cpu(bph->off_dt_strings);
+ p_struct = (CONST CHAR8*)FdtBlob + off_dt;
+ p_strings = (CONST CHAR8*)FdtBlob + off_str;
+ version = fdt32_to_cpu(bph->version);
+
+ p = p_struct;
+ while ((tag = fdt32_to_cpu(GET_CELL(p))) != FDT_END) {
+ if (tag == FDT_BEGIN_NODE) {
+ s = p;
+ p = PALIGN(p + AsciiStrLen (s) + 1, 4);
+
+ if (*s == '\0')
+ s = "/";
+
+ Print(L"%*s%a {\n", depth * shift, L" ", s);
+
+ depth++;
+ continue;
+ }
+
+ if (tag == FDT_END_NODE) {
+ depth--;
+
+ Print(L"%*s};\n", depth * shift, L" ");
+ continue;
+ }
+
+ if (tag == FDT_NOP) {
+ Print(L"%*s// [NOP]\n", depth * shift, L" ");
+ continue;
+ }
+
+ if (tag != FDT_PROP) {
+ Print(L"%*s ** Unknown tag 0x%08x\n", depth * shift, L" ", tag);
+ break;
+ }
+ sz = fdt32_to_cpu(GET_CELL(p));
+ s = p_strings + fdt32_to_cpu(GET_CELL(p));
+ if (version < 16 && sz >= 8)
+ p = PALIGN(p, 8);
+ t = p;
+
+ p = PALIGN(p + sz, 4);
+
+ Print(L"%*s%a", depth * shift, L" ", s);
+ PrintData(t, sz);
+ Print(L";\n");
+ }
+}
+
+typedef struct {
+ UINTN Base;
+ UINTN Size;
+} FdtRegion;
+
+EFI_STATUS
+PrepareFdt (
+ IN CONST CHAR8* CommandLineArguments,
+ IN EFI_PHYSICAL_ADDRESS InitrdImage,
+ IN UINTN InitrdImageSize,
+ IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+ IN OUT UINT32 *FdtBlobSize
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS NewFdtBlobBase;
+ UINTN NewFdtBlobSize;
+ VOID* fdt;
+ INTN err;
+ INTN node;
+ INTN cpu_node;
+ INTN lenp;
+ CONST VOID* BootArg;
+ EFI_PHYSICAL_ADDRESS InitrdImageStart;
+ EFI_PHYSICAL_ADDRESS InitrdImageEnd;
+ FdtRegion Region;
+ UINTN Index;
+ CHAR8 Name[10];
+ LIST_ENTRY ResourceList;
+ BDS_SYSTEM_MEMORY_RESOURCE *Resource;
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINT32 MpId;
+ UINT32 ClusterId;
+ UINT32 CoreId;
+ UINT64 CpuReleaseAddr;
+
+ err = fdt_check_header ((VOID*)(UINTN)(*FdtBlobBase));
+ if (err != 0) {
+ Print (L"ERROR: Device Tree header not valid (err:%d)\n", err);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Allocate memory for the new FDT
+ //
+ NewFdtBlobSize = fdt_totalsize((VOID*)(UINTN)(*FdtBlobBase)) + FDT_ADDITIONAL_ENTRIES_SIZE;
+
+ // Try below a watermark address
+ Status = EFI_NOT_FOUND;
+ if (PcdGet32(PcdArmLinuxFdtMaxOffset) != 0) {
+ NewFdtBlobBase = LINUX_FDT_MAX_OFFSET;
+ Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_WARN, "Warning: Failed to load FDT below address 0x%lX (%r). Will try again at a random address anywhere.\n", NewFdtBlobBase, Status));
+ }
+ }
+
+ // Try anywhere there is available space
+ if (EFI_ERROR(Status)) {
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
+ if (EFI_ERROR(Status)) {
+ ASSERT_EFI_ERROR(Status);
+ goto FAIL_NEW_FDT;
+ } else {
+ DEBUG ((EFI_D_WARN, "WARNING: Loaded FDT at random address 0x%lX.\nWARNING: There is a risk of accidental overwriting by other code/data.\n", NewFdtBlobBase));
+ }
+ }
+
+ // Load the Original FDT tree into the new region
+ fdt = (VOID*)(UINTN)NewFdtBlobBase;
+ err = fdt_open_into((VOID*)(UINTN)(*FdtBlobBase), fdt, NewFdtBlobSize);
+ if (err) {
+ DEBUG((EFI_D_ERROR, "fdt_open_into(): %a\n", fdt_strerror(err)));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_NEW_FDT;
+ }
+
+ DEBUG_CODE_BEGIN();
+ //DebugDumpFdt (fdt);
+ DEBUG_CODE_END();
+
+ node = fdt_subnode_offset(fdt, 0, "chosen");
+ if (node < 0) {
+ // The 'chosen' node does not exist, create it
+ node = fdt_add_subnode(fdt, 0, "chosen");
+ if (node < 0) {
+ DEBUG((EFI_D_ERROR,"Error on finding 'chosen' node\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_NEW_FDT;
+ }
+ }
+
+ DEBUG_CODE_BEGIN();
+ BootArg = fdt_getprop(fdt, node, "bootargs", &lenp);
+ if (BootArg != NULL) {
+ DEBUG((EFI_D_ERROR,"BootArg: %a\n",BootArg));
+ }
+ DEBUG_CODE_END();
+
+ // Set Linux CmdLine
+ if ((CommandLineArguments != NULL) && (AsciiStrLen (CommandLineArguments) > 0)) {
+ err = fdt_setprop(fdt, node, "bootargs", CommandLineArguments, AsciiStrSize(CommandLineArguments));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'bootarg' (err:%d)\n",err));
+ }
+ }
+
+ // Set Linux Initrd
+ if (InitrdImageSize != 0) {
+ InitrdImageStart = cpu_to_fdt64 (InitrdImage);
+ err = fdt_setprop(fdt, node, "linux,initrd-start", &InitrdImageStart, sizeof(EFI_PHYSICAL_ADDRESS));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err));
+ }
+ InitrdImageEnd = cpu_to_fdt64 (InitrdImage + InitrdImageSize);
+ err = fdt_setprop(fdt, node, "linux,initrd-end", &InitrdImageEnd, sizeof(EFI_PHYSICAL_ADDRESS));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err));
+ }
+ }
+
+ // Set Physical memory setup if does not exist
+ node = fdt_subnode_offset(fdt, 0, "memory");
+ if (node < 0) {
+ // The 'memory' node does not exist, create it
+ node = fdt_add_subnode(fdt, 0, "memory");
+ if (node >= 0) {
+ fdt_setprop_string(fdt, node, "name", "memory");
+ fdt_setprop_string(fdt, node, "device_type", "memory");
+
+ GetSystemMemoryResources (&ResourceList);
+ Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceList.ForwardLink;
+
+ if (sizeof(UINTN) == sizeof(UINT32)) {
+ Region.Base = cpu_to_fdt32((UINTN)Resource->PhysicalStart);
+ Region.Size = cpu_to_fdt32((UINTN)Resource->ResourceLength);
+ } else {
+ Region.Base = cpu_to_fdt64((UINTN)Resource->PhysicalStart);
+ Region.Size = cpu_to_fdt64((UINTN)Resource->ResourceLength);
+ }
+
+ err = fdt_setprop(fdt, node, "reg", &Region, sizeof(Region));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'memory region' (err:%d)\n",err));
+ }
+ }
+ }
+
+ // Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms
+ for (Index=0; Index < gST->NumberOfTableEntries; Index++) {
+ // Check for correct GUID type
+ if (CompareGuid (&gArmMpCoreInfoGuid, &(gST->ConfigurationTable[Index].VendorGuid))) {
+ MpId = ArmReadMpidr ();
+ ClusterId = GET_CLUSTER_ID(MpId);
+ CoreId = GET_CORE_ID(MpId);
+
+ node = fdt_subnode_offset(fdt, 0, "cpus");
+ if (node < 0) {
+ // Create the /cpus node
+ node = fdt_add_subnode(fdt, 0, "cpus");
+ fdt_setprop_string(fdt, node, "name", "cpus");
+ fdt_setprop_cell(fdt, node, "#address-cells", 1);
+ fdt_setprop_cell(fdt, node, "#size-cells", 0);
+ }
+
+ // Get pointer to ARM processor table
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE *)gST->ConfigurationTable[Index].VendorTable;
+ ArmCoreInfoTable = ArmProcessorTable->ArmCpus;
+
+ for (Index = 0; Index < ArmProcessorTable->NumberOfEntries; Index++) {
+ AsciiSPrint (Name, 10, "cpu@%d", Index);
+ cpu_node = fdt_subnode_offset(fdt, node, Name);
+ if (cpu_node < 0) {
+ cpu_node = fdt_add_subnode(fdt, node, Name);
+ fdt_setprop_string(fdt, cpu_node, "device-type", "cpu");
+ fdt_setprop(fdt, cpu_node, "reg", &Index, sizeof(Index));
+ }
+
+ fdt_setprop_string(fdt, cpu_node, "enable-method", "spin-table");
+ CpuReleaseAddr = cpu_to_fdt64(ArmCoreInfoTable[Index].MailboxSetAddress);
+ fdt_setprop(fdt, cpu_node, "cpu-release-addr", &CpuReleaseAddr, sizeof(CpuReleaseAddr));
+
+ // If it is not the primary core than the cpu should be disabled
+ if (((ArmCoreInfoTable[Index].ClusterId != ClusterId) || (ArmCoreInfoTable[Index].CoreId != CoreId))) {
+ fdt_setprop_string(fdt, cpu_node, "status", "disabled");
+ }
+ }
+ break;
+ }
+ }
+
+ DEBUG_CODE_BEGIN();
+ //DebugDumpFdt (fdt);
+ DEBUG_CODE_END();
+
+ *FdtBlobBase = NewFdtBlobBase;
+ *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(NewFdtBlobBase));
+ return EFI_SUCCESS;
+
+FAIL_NEW_FDT:
+ *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(*FdtBlobBase));
+ // Return success even if we failed to update the FDT blob. The original one is still valid.
+ return EFI_SUCCESS;
+}
+
+
diff --git a/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.c b/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.c index f9a145f4b..cc54343fa 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.c +++ b/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.c @@ -13,6 +13,7 @@ **/ #include "BdsInternal.h" +#include "BdsLinuxLoader.h" #define ALIGN32_BELOW(addr) ALIGN_POINTER(addr - 32,32) @@ -29,8 +30,8 @@ PreparePlatformHardware ( ArmDisableDataCache(); // Invalidate and disable the Instruction cache - ArmInvalidateInstructionCache (); ArmDisableInstructionCache (); + ArmInvalidateInstructionCache (); // Turn off MMU ArmDisableMmu(); @@ -63,9 +64,15 @@ StartLinux ( // This is necessary because the ARM Linux kernel requires // the FTD / ATAG List to reside entirely inside the first 1MB of // physical memory. - if ((UINTN)KernelParamsAddress > LINUX_ATAG_MAX_OFFSET) { - //Note: There is no requirement on the alignment - KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_ATAG_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize); + //Note: There is no requirement on the alignment + if (MachineType != ARM_FDT_MACHINE_TYPE) { + if (((UINTN)KernelParamsAddress > LINUX_ATAG_MAX_OFFSET) && (KernelParamsSize < PcdGet32(PcdArmLinuxAtagMaxOffset))) { + KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_ATAG_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize); + } + } else { + if (((UINTN)KernelParamsAddress > LINUX_FDT_MAX_OFFSET) && (KernelParamsSize < PcdGet32(PcdArmLinuxFdtMaxOffset))) { + KernelParamsAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)CopyMem (ALIGN32_BELOW(LINUX_FDT_MAX_OFFSET - KernelParamsSize), (VOID*)(UINTN)KernelParamsAddress, KernelParamsSize); + } } if ((UINTN)LinuxImage > LINUX_KERNEL_MAX_OFFSET) { @@ -122,7 +129,7 @@ Exit: Start a Linux kernel from a Device Path @param LinuxKernel Device Path to the Linux Kernel - @param Parameters Linux kernel agruments + @param Parameters Linux kernel arguments @param Fdt Device Path to the Flat Device Tree @retval EFI_SUCCESS All drivers have been connected @@ -134,14 +141,14 @@ EFI_STATUS BdsBootLinuxAtag ( IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath, IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath, - IN CONST CHAR8* Arguments + IN CONST CHAR8* CommandLineArguments ) { EFI_STATUS Status; UINT32 LinuxImageSize; UINT32 InitrdImageSize = 0; - UINT32 KernelParamsSize; - EFI_PHYSICAL_ADDRESS KernelParamsAddress; + UINT32 AtagSize; + EFI_PHYSICAL_ADDRESS AtagBase; EFI_PHYSICAL_ADDRESS LinuxImage; EFI_PHYSICAL_ADDRESS InitrdImage; @@ -180,20 +187,20 @@ BdsBootLinuxAtag ( // // By setting address=0 we leave the memory allocation to the function - Status = PrepareAtagList (Arguments, InitrdImage, InitrdImageSize, &KernelParamsAddress, &KernelParamsSize); + Status = PrepareAtagList (CommandLineArguments, InitrdImage, InitrdImageSize, &AtagBase, &AtagSize); if (EFI_ERROR(Status)) { Print(L"ERROR: Can not prepare ATAG list. Status=0x%X\n", Status); return Status; } - return StartLinux (LinuxImage, LinuxImageSize, KernelParamsAddress, KernelParamsSize, PcdGet32(PcdArmMachineType)); + return StartLinux (LinuxImage, LinuxImageSize, AtagBase, AtagSize, PcdGet32(PcdArmMachineType)); } /** Start a Linux kernel from a Device Path @param LinuxKernel Device Path to the Linux Kernel - @param Parameters Linux kernel agruments + @param Parameters Linux kernel arguments @param Fdt Device Path to the Flat Device Tree @retval EFI_SUCCESS All drivers have been connected @@ -205,21 +212,18 @@ EFI_STATUS BdsBootLinuxFdt ( IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath, IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath, - IN CONST CHAR8* Arguments, + IN CONST CHAR8* CommandLineArguments, IN EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath ) { EFI_STATUS Status; UINT32 LinuxImageSize; UINT32 InitrdImageSize = 0; - UINT32 KernelParamsSize; - EFI_PHYSICAL_ADDRESS KernelParamsAddress; - UINT32 FdtMachineType; + UINT32 FdtBlobSize; + EFI_PHYSICAL_ADDRESS FdtBlobBase; EFI_PHYSICAL_ADDRESS LinuxImage; EFI_PHYSICAL_ADDRESS InitrdImage; - FdtMachineType = 0xFFFFFFFF; - PERF_START (NULL, "BDS", NULL, 0); // Load the Linux kernel from a device path @@ -249,21 +253,22 @@ BdsBootLinuxFdt ( } } - // Load the FDT binary from a device path - KernelParamsAddress = LINUX_ATAG_MAX_OFFSET; - Status = BdsLoadImage (FdtDevicePath, AllocateMaxAddress, &KernelParamsAddress, &KernelParamsSize); + // Load the FDT binary from a device path. The FDT will be reloaded later to a more appropriate location for the Linux kernel. + FdtBlobBase = 0; + Status = BdsLoadImage (FdtDevicePath, AllocateAnyPages, &FdtBlobBase, &FdtBlobSize); if (EFI_ERROR(Status)) { Print (L"ERROR: Did not find Device Tree blob.\n"); return Status; } + // Update the Fdt with the Initrd information. The FDT will increase in size. // By setting address=0 we leave the memory allocation to the function - Status = PrepareFdt (Arguments, InitrdImage, InitrdImageSize, &KernelParamsAddress, &KernelParamsSize); + Status = PrepareFdt (CommandLineArguments, InitrdImage, InitrdImageSize, &FdtBlobBase, &FdtBlobSize); if (EFI_ERROR(Status)) { - Print(L"ERROR: Can not load Linux kernel with Device Tree. Status=0x%X\n", Status); + Print(L"ERROR: Can not load kernel with FDT. Status=%r\n", Status); return Status; } - - return StartLinux (LinuxImage, LinuxImageSize, KernelParamsAddress, KernelParamsSize, FdtMachineType); + + return StartLinux (LinuxImage, LinuxImageSize, FdtBlobBase, FdtBlobSize, ARM_FDT_MACHINE_TYPE); } diff --git a/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.h b/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.h index 9e45e03a8..a9b7037d1 100644 --- a/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.h +++ b/edk2/ArmPkg/Library/BdsLib/BdsLinuxLoader.h @@ -15,21 +15,26 @@ #ifndef __BDSLINUXLOADER_H #define __BDSLINUXLOADER_H -#include <Guid/ArmMpCoreInfo.h> - #define LINUX_UIMAGE_SIGNATURE 0x56190527 - -#define LINUX_ATAG_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset)) #define LINUX_KERNEL_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxKernelMaxOffset)) - -// Size allocated for the Atag list -#define ATAG_MAX_SIZE 0x3000 +#define LINUX_ATAG_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset)) +#define LINUX_FDT_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset)) // Additional size that could be used for FDT entries added by the UEFI OS Loader // Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes) // + system memory region (20bytes) + mp_core entries (200 bytes) #define FDT_ADDITIONAL_ENTRIES_SIZE 0x300 +#define ARM_FDT_MACHINE_TYPE 0xFFFFFFFF + +typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase); + +// +// ATAG Definitions +// + +#define ATAG_MAX_SIZE 0x3000 + /* ATAG : list of possible tags */ #define ATAG_NONE 0x00000000 #define ATAG_CORE 0x54410001 @@ -43,7 +48,9 @@ #define ATAG_CMDLINE 0x54410009 #define ATAG_ARM_MP_CORE 0x5441000A -/* structures for each atag */ +#define next_tag_address(t) ((LINUX_ATAG*)((UINT32)(t) + (((t)->header.size) << 2) )) +#define tag_size(type) ((UINT32)((sizeof(LINUX_ATAG_HEADER) + sizeof(type)) >> 2)) + typedef struct { UINT32 size; /* length of tag in words including this header */ UINT32 type; /* tag type */ @@ -128,9 +135,22 @@ typedef struct { } body; } LINUX_ATAG; -typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase); - -#define next_tag_address(t) ((LINUX_ATAG*)((UINT32)(t) + (((t)->header.size) << 2) )) -#define tag_size(type) ((UINT32)((sizeof(LINUX_ATAG_HEADER) + sizeof(type)) >> 2)) +EFI_STATUS +PrepareAtagList ( + IN CONST CHAR8* CommandLineString, + IN EFI_PHYSICAL_ADDRESS InitrdImage, + IN UINTN InitrdImageSize, + OUT EFI_PHYSICAL_ADDRESS *AtagBase, + OUT UINT32 *AtagSize + ); + +EFI_STATUS +PrepareFdt ( + IN CONST CHAR8* CommandLineArguments, + IN EFI_PHYSICAL_ADDRESS InitrdImage, + IN UINTN InitrdImageSize, + IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase, + IN OUT UINT32 *FdtBlobSize + ); #endif diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm index 2d901c3a6..d567cd54e 100755 --- a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm +++ b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm @@ -55,3 +55,5 @@ __aeabi_memclr4 mov r2, r1 mov r1, #0 b __aeabi_memset + + END diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm index da3ea3e31..9aefa808d 100644 --- a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm +++ b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm @@ -15,6 +15,7 @@ EXPORT __aeabi_uread4
+ EXPORT __aeabi_uread8
AREA Uread4, CODE, READONLY
@@ -35,4 +36,31 @@ __aeabi_uread4 orr r0, r1, r0, lsl #24
bx lr
+;
+;UINT64
+;EFIAPI
+;__aeabi_uread8 (
+; IN VOID *Pointer
+; );
+;
+__aeabi_uread8
+ mov r3, r0
+
+ ldrb r1, [r3]
+ ldrb r2, [r3, #1]
+ orr r1, r1, r2, lsl #8
+ ldrb r2, [r3, #2]
+ orr r1, r1, r2, lsl #16
+ ldrb r0, [r3, #3]
+ orr r0, r1, r0, lsl #24
+
+ ldrb r1, [r3, #4]
+ ldrb r2, [r3, #5]
+ orr r1, r1, r2, lsl #8
+ ldrb r2, [r3, #6]
+ orr r1, r1, r2, lsl #16
+ ldrb r2, [r3, #7]
+ orr r1, r1, r2, lsl #24
+
+ bx lr
END
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm index deb018932..a456ea250 100644 --- a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm +++ b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm @@ -14,6 +14,7 @@ EXPORT __aeabi_uwrite4 + EXPORT __aeabi_uwrite8 AREA Uwrite4, CODE, READONLY @@ -35,6 +36,33 @@ __aeabi_uwrite4 mov r2, r0, lsr #24 strb r2, [r1, #3] bx lr - + +; +;UINT64 +;EFIAPI +;__aeabi_uwrite8 ( +; IN UINT64 Data, //r0-r1 +; IN VOID *Pointer //r2 +; ); +; +; +__aeabi_uwrite8 + mov r3, r0, lsr #8 + strb r0, [r2] + strb r3, [r2, #1] + mov r3, r0, lsr #16 + strb r3, [r2, #2] + mov r3, r0, lsr #24 + strb r3, [r2, #3] + + mov r3, r1, lsr #8 + strb r1, [r2, #4] + strb r3, [r2, #5] + mov r3, r1, lsr #16 + strb r3, [r2, #6] + mov r3, r1, lsr #24 + strb r3, [r2, #7] + bx lr + END diff --git a/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentException.S b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentException.S new file mode 100644 index 000000000..3c1738676 --- /dev/null +++ b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentException.S @@ -0,0 +1,276 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#include <Library/PcdLib.h> + +/* + +This is the stack constructed by the exception handler (low address to high address) + # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM + Reg Offset + === ====== + R0 0x00 # stmfd SP!,{R0-R12} + R1 0x04 + R2 0x08 + R3 0x0c + R4 0x10 + R5 0x14 + R6 0x18 + R7 0x1c + R8 0x20 + R9 0x24 + R10 0x28 + R11 0x2c + R12 0x30 + SP 0x34 # reserved via adding 0x20 (32) to the SP + LR 0x38 + PC 0x3c + CPSR 0x40 + DFSR 0x44 + DFAR 0x48 + IFSR 0x4c + IFAR 0x50 + + LR 0x54 # SVC Link register (we need to restore it) + + LR 0x58 # pushed by srsfd + CPSR 0x5c + + */ + +GCC_ASM_EXPORT(DebugAgentVectorTable) +GCC_ASM_IMPORT(DefaultExceptionHandler) + +.text +#if !defined(__APPLE__) +.fpu neon @ makes vpush/vpop assemble +#endif +.align 5 + + +// +// This code gets copied to the ARM vector table +// ExceptionHandlersStart - ExceptionHandlersEnd gets copied +// +ASM_PFX(DebugAgentVectorTable): + b ASM_PFX(ResetEntry) + b ASM_PFX(UndefinedInstructionEntry) + b ASM_PFX(SoftwareInterruptEntry) + b ASM_PFX(PrefetchAbortEntry) + b ASM_PFX(DataAbortEntry) + b ASM_PFX(ReservedExceptionEntry) + b ASM_PFX(IrqEntry) + b ASM_PFX(FiqEntry) + +ASM_PFX(ResetEntry): + srsdb #0x13! @ Store return state on SVC stack + @ We are already in SVC mode + + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#0 @ ExceptionType + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(UndefinedInstructionEntry): + sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry + srsdb #0x13! @ Store return state on SVC stack + cps #0x13 @ Switch to SVC for common stack + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#1 @ ExceptionType + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(SoftwareInterruptEntry): + sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry + srsdb #0x13! @ Store return state on SVC stack + @ We are already in SVC mode + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#2 @ ExceptionType + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(PrefetchAbortEntry): + sub LR,LR,#4 + srsdb #0x13! @ Store return state on SVC stack + cps #0x13 @ Switch to SVC for common stack + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#3 @ ExceptionType + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(DataAbortEntry): + sub LR,LR,#8 + srsdb #0x13! @ Store return state on SVC stack + cps #0x13 @ Switch to SVC for common stack + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#4 + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(ReservedExceptionEntry): + srsdb #0x13! @ Store return state on SVC stack + cps #0x13 @ Switch to SVC for common stack + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#5 + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(IrqEntry): + sub LR,LR,#4 + srsdb #0x13! @ Store return state on SVC stack + cps #0x13 @ Switch to SVC for common stack + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + + mov R0,#6 @ ExceptionType + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +ASM_PFX(FiqEntry): + sub LR,LR,#4 + srsdb #0x13! @ Store return state on SVC stack + cps #0x13 @ Switch to SVC for common stack + stmfd SP!,{LR} @ Store the link register for the current mode + sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR + stmfd SP!,{R0-R12} @ Store the register state + @ Since we have already switch to SVC R8_fiq - R12_fiq + @ never get used or saved + mov R0,#7 @ ExceptionType + ldr R1,ASM_PFX(CommonExceptionEntry) + bx R1 + +// +// This gets patched by the C code that patches in the vector table +// +ASM_PFX(CommonExceptionEntry): + .word ASM_PFX(AsmCommonExceptionEntry) + +ASM_PFX(ExceptionHandlersEnd): + +// +// This code runs from CpuDxe driver loaded address. It is patched into +// CommonExceptionEntry. +// +ASM_PFX(AsmCommonExceptionEntry): + mrc p15, 0, R1, c6, c0, 2 @ Read IFAR + str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR + + mrc p15, 0, R1, c5, c0, 1 @ Read IFSR + str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR + + mrc p15, 0, R1, c6, c0, 0 @ Read DFAR + str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR + + mrc p15, 0, R1, c5, c0, 0 @ Read DFSR + str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR + + ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack + str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR + + add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR + and R3, R1, #0x1f @ Check CPSR to see if User or System Mode + cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df)) + cmpne R3, #0x10 @ + stmeqed R2, {lr}^ @ save unbanked lr + @ else + stmneed R2, {lr} @ save SVC lr + + + ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd + @ Check to see if we have to adjust for Thumb entry + sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) { + cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb + bhi NoAdjustNeeded + + tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry + addne R5, R5, #2 @ PC += 2@ + str R5,[SP,#0x58] @ Update LR value pused by srsfd + +NoAdjustNeeded: + + str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC + + sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack + str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP + + @ R0 is ExceptionType + mov R1,SP @ R1 is SystemContext + +#if (FixedPcdGet32(PcdVFPEnabled)) + vpush {d0-d15} @ save vstm registers in case they are used in optimizations +#endif + +/* +VOID +EFIAPI +DefaultExceptionHandler ( + IN EFI_EXCEPTION_TYPE ExceptionType, R0 + IN OUT EFI_SYSTEM_CONTEXT SystemContext R1 + ) + +*/ + blx ASM_PFX(DefaultExceptionHandler) @ Call exception handler + +#if (FixedPcdGet32(PcdVFPEnabled)) + vpop {d0-d15} +#endif + + ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR + mcr p15, 0, R1, c5, c0, 1 @ Write IFSR + + ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR + mcr p15, 0, R1, c5, c0, 0 @ Write DFSR + + ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC + str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored + + ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR + str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored + + add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry + add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR + and R1, R1, #0x1f @ Check to see if User or System Mode + cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f)) + cmpne R1, #0x10 @ + ldmeqed R2, {lr}^ @ restore unbanked lr + @ else + ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR} + + ldmfd SP!,{R0-R12} @ Restore general purpose registers + @ Exception handler can not change SP + + add SP,SP,#0x20 @ Clear out the remaining stack space + ldmfd SP!,{LR} @ restore the link register for this context + rfefd SP! @ return from exception via srsfd stack slot + diff --git a/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentException.asm b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentException.asm new file mode 100644 index 000000000..f281c0603 --- /dev/null +++ b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentException.asm @@ -0,0 +1,273 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+#include <Library/PcdLib.h>
+
+/*
+
+This is the stack constructed by the exception handler (low address to high address)
+ # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
+ Reg Offset
+ === ======
+ R0 0x00 # stmfd SP!,{R0-R12}
+ R1 0x04
+ R2 0x08
+ R3 0x0c
+ R4 0x10
+ R5 0x14
+ R6 0x18
+ R7 0x1c
+ R8 0x20
+ R9 0x24
+ R10 0x28
+ R11 0x2c
+ R12 0x30
+ SP 0x34 # reserved via adding 0x20 (32) to the SP
+ LR 0x38
+ PC 0x3c
+ CPSR 0x40
+ DFSR 0x44
+ DFAR 0x48
+ IFSR 0x4c
+ IFAR 0x50
+
+ LR 0x54 # SVC Link register (we need to restore it)
+
+ LR 0x58 # pushed by srsfd
+ CPSR 0x5c
+
+ */
+
+ EXPORT DebugAgentVectorTable
+ IMPORT DefaultExceptionHandler
+
+ PRESERVE8
+ AREA DebugAgentException, CODE, READONLY, CODEALIGN, ALIGN=5
+
+//
+// This code gets copied to the ARM vector table
+// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
+//
+DebugAgentVectorTable FUNCTION
+ b ResetEntry
+ b UndefinedInstructionEntry
+ b SoftwareInterruptEntry
+ b PrefetchAbortEntry
+ b DataAbortEntry
+ b ReservedExceptionEntry
+ b IrqEntry
+ b FiqEntry
+ ENDFUNC
+
+ResetEntry
+ srsfd #0x13! ; Store return state on SVC stack
+ ; We are already in SVC mode
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#0 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+UndefinedInstructionEntry
+ sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
+ srsfd #0x13! ; Store return state on SVC stack
+ cps #0x13 ; Switch to SVC for common stack
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#1 ; ExceptionType
+ ldr R1,CommonExceptionEntry;
+ bx R1
+
+SoftwareInterruptEntry
+ sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
+ srsfd #0x13! ; Store return state on SVC stack
+ ; We are already in SVC mode
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#2 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+PrefetchAbortEntry
+ sub LR,LR,#4
+ srsfd #0x13! ; Store return state on SVC stack
+ cps #0x13 ; Switch to SVC for common stack
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#3 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+DataAbortEntry
+ sub LR,LR,#8
+ srsfd #0x13! ; Store return state on SVC stack
+ cps #0x13 ; Switch to SVC for common stack
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#4 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+ReservedExceptionEntry
+ srsfd #0x13! ; Store return state on SVC stack
+ cps #0x13 ; Switch to SVC for common stack
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#5 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+IrqEntry
+ sub LR,LR,#4
+ srsfd #0x13! ; Store return state on SVC stack
+ cps #0x13 ; Switch to SVC for common stack
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+
+ mov R0,#6 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+FiqEntry
+ sub LR,LR,#4
+ srsfd #0x13! ; Store return state on SVC stack
+ cps #0x13 ; Switch to SVC for common stack
+ stmfd SP!,{LR} ; Store the link register for the current mode
+ sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
+ stmfd SP!,{R0-R12} ; Store the register state
+ ; Since we have already switch to SVC R8_fiq - R12_fiq
+ ; never get used or saved
+ mov R0,#7 ; ExceptionType
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+//
+// This gets patched by the C code that patches in the vector table
+//
+CommonExceptionEntry
+ dcd AsmCommonExceptionEntry
+
+ExceptionHandlersEnd
+
+//
+// This code runs from CpuDxe driver loaded address. It is patched into
+// CommonExceptionEntry.
+//
+AsmCommonExceptionEntry
+ mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
+ str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
+
+ mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
+ str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
+
+ mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
+ str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
+
+ mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
+ str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
+
+ ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
+ str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
+
+ add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
+ and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
+ cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1df))
+ cmpne R3, #0x10 ;
+ stmeqed R2, {lr}^ ; save unbanked lr
+ ; else
+ stmneed R2, {lr} ; save SVC lr
+
+
+ ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
+ ; Check to see if we have to adjust for Thumb entry
+ sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType ==2)) {
+ cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
+ bhi NoAdjustNeeded
+
+ tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
+ addne R5, R5, #2 ; PC += 2;
+ str R5,[SP,#0x58] ; Update LR value pused by srsfd
+
+NoAdjustNeeded
+
+ str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
+
+ sub R1, SP, #0x60 ; We pused 0x60 bytes on the stack
+ str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
+
+ ; R0 is ExceptionType
+ mov R1,SP ; R1 is SystemContext
+
+#if (FixedPcdGet32(PcdVFPEnabled))
+ vpush {d0-d15} ; save vstm registers in case they are used in optimizations
+#endif
+
+/*
+VOID
+EFIAPI
+DefaultExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType, R0
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
+ )
+
+*/
+ blx DefaultExceptionHandler ; Call exception handler
+
+#if (FixedPcdGet32(PcdVFPEnabled))
+ vpop {d0-d15}
+#endif
+
+ ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
+ mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
+
+ ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
+ mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
+
+ ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
+ str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
+
+ ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR
+ str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
+
+ add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry
+ add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
+ and R1, R1, #0x1f ; Check to see if User or System Mode
+ cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
+ cmpne R1, #0x10 ;
+ ldmeqed R2, {lr}^ ; restore unbanked lr
+ ; else
+ ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}
+
+ ldmfd SP!,{R0-R12} ; Restore general purpose registers
+ ; Exception handler can not change SP
+
+ add SP,SP,#0x20 ; Clear out the remaining stack space
+ ldmfd SP!,{LR} ; restore the link register for this context
+ rfefd SP! ; return from exception via srsfd stack slot
+
+ END
diff --git a/edk2/ArmPkg/Library/DebugAgentSymbolsOnlyLib/DebugAgentSymbolsOnlyLib.c b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c index 5faac3339..c27d8e7dd 100755..100644 --- a/edk2/ArmPkg/Library/DebugAgentSymbolsOnlyLib/DebugAgentSymbolsOnlyLib.c +++ b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c @@ -1,7 +1,7 @@ /** @file
* Main file supporting the SEC Phase for Versatile Express
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -14,6 +14,7 @@ **/
#include <Uefi.h>
+#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
@@ -28,6 +29,13 @@ #define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
(ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1))
+
+// Vector Table for Sec Phase
+VOID
+DebugAgentVectorTable (
+ VOID
+ );
+
/**
Returns the highest bit set of the State field
@@ -275,6 +283,11 @@ InitializeDebugAgent ( EFI_FFS_FILE_HEADER *FfsHeader;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
+ // Now we've got UART, make the check:
+ // - The Vector table must be 32-byte aligned
+ ASSERT(((UINT32)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ ArmWriteVBar ((UINT32)DebugAgentVectorTable);
+
// We use InitFlag to know if DebugAgent has been intialized from
// Sec (DEBUG_AGENT_INIT_PREMEM_SEC) or PrePi (DEBUG_AGENT_INIT_POSTMEM_SEC)
// modules
diff --git a/edk2/ArmPkg/Library/DebugAgentSymbolsOnlyLib/DebugAgentSymbolsOnlyLib.inf b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf index e2c724082..1cf0b3352 100755..100644 --- a/edk2/ArmPkg/Library/DebugAgentSymbolsOnlyLib/DebugAgentSymbolsOnlyLib.inf +++ b/edk2/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf @@ -1,5 +1,5 @@ #
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -13,22 +13,26 @@ [Defines]
INF_VERSION = 0x00010005
- BASE_NAME = DebugAgentSymbolsOnlyLib
+ BASE_NAME = DebugAgentSymbolsBaseLib
FILE_GUID = 9055e2e0-9b33-11e0-a7d7-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugAgentLib
[Sources.common]
- DebugAgentSymbolsOnlyLib.c
-
+ DebugAgentSymbolsBaseLib.c
+ DebugAgentException.asm | RVCT
+ DebugAgentException.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
+ ArmLib
DebugLib
+ DefaultExceptionHandlerLib
PcdLib
PeCoffExtraActionLib
PeCoffLib
diff --git a/edk2/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c b/edk2/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c index ad75f616e..6459d51cf 100755 --- a/edk2/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c +++ b/edk2/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c @@ -2,6 +2,8 @@ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -82,8 +84,13 @@ PeCoffLoaderRelocateImageExtraAction ( #endif
#ifdef __CC_ARM
+#if (__ARMCC_VERSION < 500000)
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((EFI_D_ERROR, "load /a /ni /np %a &0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
+#else
+ // Print out the command for the DS-5 to load symbols for this image
+ DEBUG ((EFI_D_ERROR, "add-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
+#endif
#elif __GNUC__
// This may not work correctly if you generate PE/COFF directlyas then the Offset would not be required
DEBUG ((EFI_D_ERROR, "add-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
diff --git a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c index 94aacf83a..bb29b95da 100644 --- a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c +++ b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c @@ -2,6 +2,7 @@ Default exception handler
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -14,7 +15,6 @@ **/
#include <Uefi.h>
-#include <Library/UefiLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
@@ -23,67 +23,23 @@ #include <Library/SerialPortLib.h>
#include <Guid/DebugImageInfoTable.h>
-#include <Protocol/DebugSupport.h>
-#include <Protocol/LoadedImage.h>
+#include <Protocol/DebugSupport.h>
+#include <Library/DefaultExceptionHandlerLib.h>
EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *gDebugImageTableHeader = NULL;
-
typedef struct {
UINT32 BIT;
CHAR8 Char;
} CPSR_CHAR;
-
-/**
- Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image
- it came from. As long as the PE/COFF image contains a debug directory entry a
- string can be returned. For ELF and Mach-O images the string points to the Mach-O or ELF
- image. Microsoft tools contain a pointer to the PDB file that contains the debug information.
-
- @param FaultAddress Address to find PE/COFF image for.
- @param ImageBase Return load address of found image
- @param PeCoffSizeOfHeaders Return the size of the PE/COFF header for the image that was found
-
- @retval NULL FaultAddress not in a loaded PE/COFF image.
- @retval Path and file name of PE/COFF image.
-
-**/
CHAR8 *
GetImageName (
IN UINT32 FaultAddress,
OUT UINT32 *ImageBase,
OUT UINT32 *PeCoffSizeOfHeaders
- )
-{
- EFI_DEBUG_IMAGE_INFO *DebugTable;
- UINTN Entry;
- CHAR8 *Address;
-
- DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable;
- if (DebugTable == NULL) {
- return NULL;
- }
-
- Address = (CHAR8 *)(UINTN)FaultAddress;
- for (Entry = 0; Entry < gDebugImageTableHeader->TableSize; Entry++, DebugTable++) {
- if (DebugTable->NormalImage != NULL) {
- if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
- (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
- if ((Address >= (CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
- (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
- *ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
- *PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
- return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
- }
- }
- }
- }
-
- return NULL;
-}
-
+ );
/**
Convert the Current Program Status Register (CPSR) to a string. The string is
@@ -198,7 +154,7 @@ FaultStatusToString ( STATIC CHAR8 *gExceptionTypeString[] = {
"Reset",
"Undefined OpCode",
- "SWI",
+ "SVC",
"Prefetch Abort",
"Data Abort",
"Undefined",
@@ -310,33 +266,3 @@ DefaultExceptionHandler ( // If some one is stepping past the exception handler adjust the PC to point to the next instruction
SystemContext.SystemContextArm->PC += PcAdjust;
}
-
-
-
-
-/**
- The constructor function caches EFI Debug table information for use in the exception handler.
-
-
- @param ImageHandle The firmware allocated handle for the EFI image.
- @param SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-DefaultExceptionHandlerConstructor (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
-
- Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&gDebugImageTableHeader);
- if (EFI_ERROR (Status)) {
- gDebugImageTableHeader = NULL;
- }
- return Status;
-}
diff --git a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerBase.c b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerBase.c new file mode 100644 index 000000000..e68617e1e --- /dev/null +++ b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerBase.c @@ -0,0 +1,35 @@ +/** @file
+
+ Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+
+/**
+
+ @param FaultAddress Address to find PE/COFF image for.
+ @param ImageBase Return load address of found image
+ @param PeCoffSizeOfHeaders Return the size of the PE/COFF header for the image that was found
+
+ @retval NULL FaultAddress not in a loaded PE/COFF image.
+ @retval Path and file name of PE/COFF image.
+
+**/
+CHAR8 *
+GetImageName (
+ IN UINT32 FaultAddress,
+ OUT UINT32 *ImageBase,
+ OUT UINT32 *PeCoffSizeOfHeaders
+ )
+{
+ return NULL;
+}
diff --git a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf index 2388c5c01..120e2de21 100644 --- a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf +++ b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf @@ -1,5 +1,4 @@ #/** @file
-# Semihosting serail port lib
#
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
#
@@ -25,6 +24,7 @@ [Sources.common]
DefaultExceptionHandler.c
+ DefaultExceptionHandlerUefi.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf new file mode 100644 index 000000000..f51d3a0ef --- /dev/null +++ b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf @@ -0,0 +1,37 @@ +#/** @file
+#
+# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DefaultExceptionHandlerBaseLib
+ FILE_GUID = 3d5261d5-5eb7-4559-98e7-475aa9d0dc42
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DefaultExceptionHandlerLib
+
+[Sources.common]
+ DefaultExceptionHandler.c
+ DefaultExceptionHandlerBase.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PrintLib
+ DebugLib
+ PeCoffGetEntryPointLib
+ ArmDisassemblerLib
+ SerialPortLib
diff --git a/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c new file mode 100644 index 000000000..8543ade99 --- /dev/null +++ b/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c @@ -0,0 +1,95 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/UefiLib.h>
+
+#include <Guid/DebugImageInfoTable.h>
+
+extern EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *gDebugImageTableHeader;
+
+/**
+ The constructor function caches EFI Debug table information for use in the exception handler.
+
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+DefaultExceptionHandlerConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&gDebugImageTableHeader);
+ if (EFI_ERROR (Status)) {
+ gDebugImageTableHeader = NULL;
+ }
+ return Status;
+}
+
+/**
+ Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image
+ it came from. As long as the PE/COFF image contains a debug directory entry a
+ string can be returned. For ELF and Mach-O images the string points to the Mach-O or ELF
+ image. Microsoft tools contain a pointer to the PDB file that contains the debug information.
+
+ @param FaultAddress Address to find PE/COFF image for.
+ @param ImageBase Return load address of found image
+ @param PeCoffSizeOfHeaders Return the size of the PE/COFF header for the image that was found
+
+ @retval NULL FaultAddress not in a loaded PE/COFF image.
+ @retval Path and file name of PE/COFF image.
+
+**/
+CHAR8 *
+GetImageName (
+ IN UINT32 FaultAddress,
+ OUT UINT32 *ImageBase,
+ OUT UINT32 *PeCoffSizeOfHeaders
+ )
+{
+ EFI_DEBUG_IMAGE_INFO *DebugTable;
+ UINTN Entry;
+ CHAR8 *Address;
+
+ DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable;
+ if (DebugTable == NULL) {
+ return NULL;
+ }
+
+ Address = (CHAR8 *)(UINTN)FaultAddress;
+ for (Entry = 0; Entry < gDebugImageTableHeader->TableSize; Entry++, DebugTable++) {
+ if (DebugTable->NormalImage != NULL) {
+ if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
+ (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
+ if ((Address >= (CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
+ (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
+ *ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
+ *PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
+ return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
+ }
+ }
+ }
+ }
+
+ return NULL;
+}
diff --git a/edk2/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c b/edk2/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c index ecc04acac..d55608b45 100644 --- a/edk2/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c +++ b/edk2/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c @@ -2,6 +2,8 @@ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -117,7 +119,11 @@ PeCoffLoaderRelocateImageExtraAction ( {
CHAR8 Buffer[256];
+#if (__ARMCC_VERSION < 500000)
AsciiSPrint (Buffer, sizeof(Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
+#else
+ AsciiSPrint (Buffer, sizeof(Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
+#endif
DeCygwinPathIfNeeded (&Buffer[16]);
WriteStringToFile (Buffer, AsciiStrSize (Buffer));
diff --git a/edk2/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c b/edk2/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c index cea6298a8..01b6dc334 100644 --- a/edk2/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c +++ b/edk2/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c @@ -1,219 +1,219 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> - - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -#include <Base.h> - -#include <Library/BaseLib.h> -#include <Library/SemihostLib.h> - -#include "SemihostPrivate.h" - -BOOLEAN -SemihostConnectionSupported ( - VOID - ) -{ - return SEMIHOST_SUPPORTED; -} - -RETURN_STATUS -SemihostFileOpen ( - IN CHAR8 *FileName, - IN UINT32 Mode, - OUT UINT32 *FileHandle - ) -{ - SEMIHOST_FILE_OPEN_BLOCK OpenBlock; - INT32 Result; - - if (FileHandle == NULL) { - return RETURN_INVALID_PARAMETER; - } - - OpenBlock.FileName = FileName; - OpenBlock.Mode = Mode; - OpenBlock.NameLength = AsciiStrLen(FileName); - - Result = Semihost_SYS_OPEN(&OpenBlock); - - if (Result == -1) { - return RETURN_NOT_FOUND; - } else { - *FileHandle = Result; - return RETURN_SUCCESS; - } -} - -RETURN_STATUS -SemihostFileSeek ( - IN UINT32 FileHandle, - IN UINT32 Offset - ) -{ - SEMIHOST_FILE_SEEK_BLOCK SeekBlock; - INT32 Result; - - SeekBlock.Handle = FileHandle; - SeekBlock.Location = Offset; - - Result = Semihost_SYS_SEEK(&SeekBlock); - - if (Result == 0) { - return RETURN_SUCCESS; - } else { - return RETURN_ABORTED; - } -} - -RETURN_STATUS -SemihostFileRead ( - IN UINT32 FileHandle, - IN OUT UINT32 *Length, - OUT VOID *Buffer - ) -{ - SEMIHOST_FILE_READ_WRITE_BLOCK ReadBlock; - UINT32 Result; - - if ((Length == NULL) || (Buffer == NULL)) { - return RETURN_INVALID_PARAMETER; - } - - ReadBlock.Handle = FileHandle; - ReadBlock.Buffer = Buffer; - ReadBlock.Length = *Length; - - Result = Semihost_SYS_READ(&ReadBlock); - - if (Result == *Length) { - return RETURN_ABORTED; - } else { - *Length -= Result; - return RETURN_SUCCESS; - } -} - -RETURN_STATUS -SemihostFileWrite ( - IN UINT32 FileHandle, - IN OUT UINT32 *Length, - IN VOID *Buffer - ) -{ - SEMIHOST_FILE_READ_WRITE_BLOCK WriteBlock; - - if ((Length == NULL) || (Buffer == NULL)) { - return RETURN_INVALID_PARAMETER; - } - - WriteBlock.Handle = FileHandle; - WriteBlock.Buffer = Buffer; - WriteBlock.Length = *Length; - - *Length = Semihost_SYS_WRITE(&WriteBlock); - - return RETURN_SUCCESS; -} - -RETURN_STATUS -SemihostFileClose ( - IN UINT32 FileHandle - ) -{ - INT32 Result = Semihost_SYS_CLOSE(&FileHandle); - - if (Result == -1) { - return RETURN_INVALID_PARAMETER; - } else { - return RETURN_SUCCESS; - } -} - -RETURN_STATUS -SemihostFileLength ( - IN UINT32 FileHandle, - OUT UINT32 *Length - ) -{ - INT32 Result; - - if (Length == NULL) { - return RETURN_INVALID_PARAMETER; - } - - Result = Semihost_SYS_FLEN(&FileHandle); - - if (Result == -1) { - return RETURN_ABORTED; - } else { - *Length = Result; - return RETURN_SUCCESS; - } -} - -RETURN_STATUS -SemihostFileRemove ( - IN CHAR8 *FileName - ) -{ - SEMIHOST_FILE_REMOVE_BLOCK RemoveBlock; - UINT32 Result; - - RemoveBlock.FileName = FileName; - RemoveBlock.NameLength = AsciiStrLen(FileName); - - Result = Semihost_SYS_REMOVE(&RemoveBlock); - - if (Result == 0) { - return RETURN_SUCCESS; - } else { - return RETURN_ABORTED; - } -} - -CHAR8 -SemihostReadCharacter ( - VOID - ) -{ - return Semihost_SYS_READC(); -} - -VOID -SemihostWriteCharacter ( - IN CHAR8 Character - ) -{ - Semihost_SYS_WRITEC(&Character); -} - -VOID -SemihostWriteString ( - IN CHAR8 *String - ) -{ - Semihost_SYS_WRITE0(String); -} - -UINT32 -SemihostSystem ( - IN CHAR8 *CommandLine - ) -{ - SEMIHOST_SYSTEM_BLOCK SystemBlock; - - SystemBlock.CommandLine = CommandLine; - SystemBlock.CommandLength = AsciiStrLen(CommandLine); - - return Semihost_SYS_SYSTEM(&SystemBlock); -} +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Base.h>
+
+#include <Library/BaseLib.h>
+#include <Library/SemihostLib.h>
+
+#include "SemihostPrivate.h"
+
+BOOLEAN
+SemihostConnectionSupported (
+ VOID
+ )
+{
+ return SEMIHOST_SUPPORTED;
+}
+
+RETURN_STATUS
+SemihostFileOpen (
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINT32 *FileHandle
+ )
+{
+ SEMIHOST_FILE_OPEN_BLOCK OpenBlock;
+ INT32 Result;
+
+ if (FileHandle == NULL) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ OpenBlock.FileName = FileName;
+ OpenBlock.Mode = Mode;
+ OpenBlock.NameLength = AsciiStrLen(FileName);
+
+ Result = Semihost_SYS_OPEN(&OpenBlock);
+
+ if (Result == -1) {
+ return RETURN_NOT_FOUND;
+ } else {
+ *FileHandle = Result;
+ return RETURN_SUCCESS;
+ }
+}
+
+RETURN_STATUS
+SemihostFileSeek (
+ IN UINT32 FileHandle,
+ IN UINT32 Offset
+ )
+{
+ SEMIHOST_FILE_SEEK_BLOCK SeekBlock;
+ INT32 Result;
+
+ SeekBlock.Handle = FileHandle;
+ SeekBlock.Location = Offset;
+
+ Result = Semihost_SYS_SEEK(&SeekBlock);
+
+ if (Result == 0) {
+ return RETURN_SUCCESS;
+ } else {
+ return RETURN_ABORTED;
+ }
+}
+
+RETURN_STATUS
+SemihostFileRead (
+ IN UINT32 FileHandle,
+ IN OUT UINT32 *Length,
+ OUT VOID *Buffer
+ )
+{
+ SEMIHOST_FILE_READ_WRITE_BLOCK ReadBlock;
+ UINT32 Result;
+
+ if ((Length == NULL) || (Buffer == NULL)) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ ReadBlock.Handle = FileHandle;
+ ReadBlock.Buffer = Buffer;
+ ReadBlock.Length = *Length;
+
+ Result = Semihost_SYS_READ(&ReadBlock);
+
+ if (Result == *Length) {
+ return RETURN_ABORTED;
+ } else {
+ *Length -= Result;
+ return RETURN_SUCCESS;
+ }
+}
+
+RETURN_STATUS
+SemihostFileWrite (
+ IN UINT32 FileHandle,
+ IN OUT UINT32 *Length,
+ IN VOID *Buffer
+ )
+{
+ SEMIHOST_FILE_READ_WRITE_BLOCK WriteBlock;
+
+ if ((Length == NULL) || (Buffer == NULL)) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ WriteBlock.Handle = FileHandle;
+ WriteBlock.Buffer = Buffer;
+ WriteBlock.Length = *Length;
+
+ *Length = Semihost_SYS_WRITE(&WriteBlock);
+
+ return RETURN_SUCCESS;
+}
+
+RETURN_STATUS
+SemihostFileClose (
+ IN UINT32 FileHandle
+ )
+{
+ INT32 Result = Semihost_SYS_CLOSE(&FileHandle);
+
+ if (Result == -1) {
+ return RETURN_INVALID_PARAMETER;
+ } else {
+ return RETURN_SUCCESS;
+ }
+}
+
+RETURN_STATUS
+SemihostFileLength (
+ IN UINT32 FileHandle,
+ OUT UINT32 *Length
+ )
+{
+ INT32 Result;
+
+ if (Length == NULL) {
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ Result = Semihost_SYS_FLEN(&FileHandle);
+
+ if (Result == -1) {
+ return RETURN_ABORTED;
+ } else {
+ *Length = Result;
+ return RETURN_SUCCESS;
+ }
+}
+
+RETURN_STATUS
+SemihostFileRemove (
+ IN CHAR8 *FileName
+ )
+{
+ SEMIHOST_FILE_REMOVE_BLOCK RemoveBlock;
+ UINT32 Result;
+
+ RemoveBlock.FileName = FileName;
+ RemoveBlock.NameLength = AsciiStrLen(FileName);
+
+ Result = Semihost_SYS_REMOVE(&RemoveBlock);
+
+ if (Result == 0) {
+ return RETURN_SUCCESS;
+ } else {
+ return RETURN_ABORTED;
+ }
+}
+
+CHAR8
+SemihostReadCharacter (
+ VOID
+ )
+{
+ return Semihost_SYS_READC();
+}
+
+VOID
+SemihostWriteCharacter (
+ IN CHAR8 Character
+ )
+{
+ Semihost_SYS_WRITEC(&Character);
+}
+
+VOID
+SemihostWriteString (
+ IN CHAR8 *String
+ )
+{
+ Semihost_SYS_WRITE0(String);
+}
+
+UINT32
+SemihostSystem (
+ IN CHAR8 *CommandLine
+ )
+{
+ SEMIHOST_SYSTEM_BLOCK SystemBlock;
+
+ SystemBlock.CommandLine = CommandLine;
+ SystemBlock.CommandLength = AsciiStrLen(CommandLine);
+
+ return Semihost_SYS_SYSTEM(&SystemBlock);
+}
diff --git a/edk2/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c b/edk2/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c index 657268a28..4db93dbd2 100644 --- a/edk2/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c +++ b/edk2/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c @@ -245,7 +245,7 @@ UncachedInternalAllocateAlignedPages ( gAttributes = Descriptor.Attributes;
}
- Status = gDS->SetMemorySpaceAttributes (Memory, EFI_PAGES_TO_SIZE (Pages), EFI_MEMORY_UC);
+ Status = gDS->SetMemorySpaceAttributes (Memory, EFI_PAGES_TO_SIZE (Pages), EFI_MEMORY_WC);
ASSERT_EFI_ERROR (Status);
return (VOID *)(UINTN)Memory;
diff --git a/edk2/ArmPkg/License.txt b/edk2/ArmPkg/License.txt new file mode 100755 index 000000000..05dbd3606 --- /dev/null +++ b/edk2/ArmPkg/License.txt @@ -0,0 +1,26 @@ +Copyright (c) 2009-2010, Apple Inc. All rights reserved.
+Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
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