1 files changed, 54 insertions, 7 deletions
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 62201cd24..48468e8bc 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
   This local APIC library instance supports x2APIC capable processors
   which have xAPIC and x2APIC modes.
 
-  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -22,13 +22,58 @@
 #include <Library/LocalApicLib.h>
 #include <Library/IoLib.h>
 #include <Library/TimerLib.h>
-#include <Library/PcdLib.h>
 
 //
 // Library internal functions
 //
 
 /**
+  Retrieve the base address of local APIC.
+
+  @return The base address of local APIC.
+
+**/
+UINTN
+EFIAPI
+GetLocalApicBaseAddress (
+  VOID
+  )
+{
+  MSR_IA32_APIC_BASE ApicBaseMsr;
+  
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+  
+  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
+           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
+}
+
+/**
+  Set the base address of local APIC.
+
+  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
+
+  @param[in] BaseAddress   Local APIC base address to be set.
+
+**/
+VOID
+EFIAPI
+SetLocalApicBaseAddress (
+  IN UINTN                BaseAddress
+  )
+{
+  MSR_IA32_APIC_BASE ApicBaseMsr;
+
+  ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
+
+  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+
+  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
+  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+}
+
+/**
   Read from a local APIC register.
 
   This function reads from a local APIC register either in xAPIC or x2APIC mode.
@@ -52,7 +97,7 @@ ReadLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);
 
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
-    return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
+    return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
   } else {
     //
     // DFR is not supported in x2APIC mode.
@@ -95,7 +140,7 @@ WriteLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);
 
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
-    MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
+    MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
   } else {
     //
     // DFR is not supported in x2APIC mode.
@@ -134,6 +179,7 @@ SendIpi (
 {
   UINT64             MsrValue;
   LOCAL_APIC_ICR_LOW IcrLowReg;
+  UINTN              LocalApciBaseAddress;
 
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
     ASSERT (ApicId <= 0xff);
@@ -141,10 +187,11 @@ SendIpi (
     //
     // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
     //
-    MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
-    MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET, IcrLow);
+    LocalApciBaseAddress = GetLocalApicBaseAddress();
+    MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
+    MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
     do {
-      IcrLowReg.Uint32 = MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET);
+      IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
     } while (IcrLowReg.Bits.DeliveryStatus != 0);
   } else {
     //