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Diffstat (limited to 'SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform')
5 files changed, 2924 insertions, 0 deletions
diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/ArmPlatform.h b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/ArmPlatform.h new file mode 100755 index 000000000..4d5f7d86f --- /dev/null +++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/ArmPlatform.h @@ -0,0 +1,692 @@ +/** @file +* Header defining RealView EB constants (Base addresses, sizes, flags) +* +* Copyright (c) 2012, Samsung Electronics Co. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARMPLATFORM_H__ +#define __ARMPLATFORM_H__ + +/******************************************* +// Platform Memory Map +*******************************************/ + +/******************************************* +// Motherboard peripherals +*******************************************/ +//PMU DOMAIN offsets +#define SWRESET_OFFSET (0x400) +#define PMU_DISP1_CONFIGURATION_OFFSET (0x40A0) +#define PMU_DISP1_STATUS_OFFSET (0x40A4) + +#define LOCAL_PWR_ENABLE (0x07) + +#define PMU_MIPI_PHY1_CONTROL_OFFSET (0x0714) + +// SYSTRCL Register +#define ARM_EB_SYSCTRL 0x10001000 + +#define PL011_CONSOLE_UART_SPEED 115200 + +// IRAM & RAM Base Address +#define CONFIG_PHY_SDRAM_BASE (0x40000000) +#define CONFIG_PHY_IRAM_BASE (0x02020000) +#define CONFIG_PHY_UEFI_BASE (CONFIG_PHY_SDRAM_BASE) +#define CONFIG_SECURE_CONTEXT_BASE (CONFIG_PHY_IRAM_BASE + 0x4c00) +#define CONFIG_PHY_TZSW_BASE (CONFIG_PHY_IRAM_BASE + 0x8000) +#define CONFIG_PHY_IRAM_NS_BASE (CONFIG_PHY_IRAM_BASE + 0x2F000) +#define CONFIG_IMAGE_INFO_BASE (CONFIG_PHY_IRAM_NS_BASE + 0x11000) + +// Exynos5250 DMC Base Address : Not used it. +#define Exynos5250_DMC_DELAY 0x3000 +#define Exynos5250_DMC_0_BASE 0x10C00000 +#define Exynos5250_DMC_1_BASE 0x10C10000 + + +// Exynos5250 DMC Base Address +#define DMC_CTRL_BASE 0x10DD0000 + +#define DMC_CONCONTROL 0x00 +#define DMC_MEMCONTROL 0x04 +#define DMC_MEMCONFIG0 0x08 +#define DMC_MEMCONFIG1 0x0C +#define DMC_DIRECTCMD 0x10 +#define DMC_PRECHCONFIG 0x14 +#define DMC_PHYCONTROL0 0x18 +#define DMC_PWRDNCONFIG 0x28 +#define DMC_TIMINGPZQ 0x2C +#define DMC_TIMINGAREF 0x30 +#define DMC_TIMINGROW 0x34 +#define DMC_TIMINGDATA 0x38 +#define DMC_TIMINGPOWER 0x3C +#define DMC_PHYSTATUS 0x40 +#define DMC_CHIPSTATUS_CH0 0x48 +#define DMC_CHIPSTATUS_CH1 0x4C +#define DMC_MRSTATUS 0x54 +#define DMC_QOSCONTROL0 0x60 +#define DMC_QOSCONTROL1 0x68 +#define DMC_QOSCONTROL2 0x70 +#define DMC_QOSCONTROL3 0x78 +#define DMC_QOSCONTROL4 0x80 +#define DMC_QOSCONTROL5 0x88 +#define DMC_QOSCONTROL6 0x90 +#define DMC_QOSCONTROL7 0x98 +#define DMC_QOSCONTROL8 0xA0 +#define DMC_QOSCONTROL9 0xA8 +#define DMC_QOSCONTROL10 0xB0 +#define DMC_QOSCONTROL11 0xB8 +#define DMC_QOSCONTROL12 0xC0 +#define DMC_QOSCONTROL13 0xC8 +#define DMC_QOSCONTROL14 0xD0 +#define DMC_QOSCONTROL15 0xD8 +#define DMC_IVCONTROL 0xF0 +#define DMC_WRTRA_CONFIG 0x00F4 +#define DMC_RDLVL_CONFIG 0x00F8 +#define DMC_BRBRSVCONTROL 0x0100 +#define DMC_BRBRSVCONFIG 0x0104 +#define DMC_BRBQOSCONFIG 0x0108 +#define DMC_MEMBASECONFIG0 0x010C +#define DMC_MEMBASECONFIG1 0x0110 +#define DMC_WRLVL_CONFIG 0x0120 +#define DMC_PMNC_PPC 0xE000 +#define DMC_CNTENS_PPC 0xE010 +#define DMC_CNTENC_PPC 0xE020 +#define DMC_INTENS_PPC 0xE030 +#define DMC_INTENC_PPC 0xE040 +#define DMC_FLAG_PPC 0xE050 +#define DMC_CCNT_PPC 0xE100 +#define DMC_PMCNT0_PPC 0xE110 +#define DMC_PMCNT1_PPC 0xE120 +#define DMC_PMCNT2_PPC 0xE130 +#define DMC_PMCNT3_PPC 0xE140 + +/* PHY Control Register */ +#define PHY0_CTRL_BASE 0x10C00000 +#define PHY1_CTRL_BASE 0x10C10000 + +#define DMC_PHY_CON0 0x00 +#define DMC_PHY_CON1 0x04 +#define DMC_PHY_CON2 0x08 +#define DMC_PHY_CON3 0x0C +#define DMC_PHY_CON4 0x10 +#define DMC_PHY_CON6 0x18 +#define DMC_PHY_CON8 0x20 +#define DMC_PHY_CON10 0x28 +#define DMC_PHY_CON11 0x2C +#define DMC_PHY_CON12 0x30 +#define DMC_PHY_CON13 0x34 +#define DMC_PHY_CON14 0x38 +#define DMC_PHY_CON15 0x3C +#define DMC_PHY_CON16 0x40 +#define DMC_PHY_CON17 0x48 +#define DMC_PHY_CON18 0x4C +#define DMC_PHY_CON19 0x50 +#define DMC_PHY_CON20 0x54 +#define DMC_PHY_CON21 0x58 +#define DMC_PHY_CON22 0x5C +#define DMC_PHY_CON23 0x60 +#define DMC_PHY_CON24 0x64 +#define DMC_PHY_CON25 0x68 +#define DMC_PHY_CON26 0x6C +#define DMC_PHY_CON27 0x70 +#define DMC_PHY_CON28 0x74 +#define DMC_PHY_CON29 0x78 +#define DMC_PHY_CON30 0x7C +#define DMC_PHY_CON31 0x80 +#define DMC_PHY_CON32 0x84 +#define DMC_PHY_CON33 0x88 +#define DMC_PHY_CON34 0x8C +#define DMC_PHY_CON35 0x90 +#define DMC_PHY_CON36 0x94 +#define DMC_PHY_CON37 0x98 +#define DMC_PHY_CON38 0x9C +#define DMC_PHY_CON39 0xA0 +#define DMC_PHY_CON40 0xA4 +#define DMC_PHY_CON41 0xA8 +#define DMC_PHY_CON42 0xAC + + + + + + +// Exynos5250 UART Register +#define Exynos5250_UART_BASE 0x12C10000 + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 + + +#define UARTLCR_H ULCON_OFFSET +#define UARTECR UFCON_OFFSET +#define UARTCR UCON_OFFSET +#define UARTIBRD UBRDIV_OFFSET +#define UARTFBRD UDIVSLOT_OFFSET + +#define UART_TX_EMPTY_FLAG_MASK (0x02) +#define UART_RX_EMPTY_FLAG_MASK (0x01) +// Exynos5250 TZPC Register +#define Exynos5250_TZPC0_BASE 0x10100000 +#define Exynos5250_TZPC1_BASE 0x10110000 +#define Exynos5250_TZPC2_BASE 0x10120000 +#define Exynos5250_TZPC3_BASE 0x10130000 +#define Exynos5250_TZPC4_BASE 0x10140000 +#define Exynos5250_TZPC5_BASE 0x10150000 +#define Exynos5250_TZPC6_BASE 0x10160000 +#define Exynos5250_TZPC7_BASE 0x10170000 +#define Exynos5250_TZPC8_BASE 0x10180000 +#define Exynos5250_TZPC9_BASE 0x10190000 + + +#define TZPC0_OFFSET 0x00000 +#define TZPC1_OFFSET 0x10000 +#define TZPC2_OFFSET 0x20000 +#define TZPC3_OFFSET 0x30000 +#define TZPC4_OFFSET 0x40000 +#define TZPC5_OFFSET 0x50000 +#define TZPC6_OFFSET 0x60000 +#define TZPC7_OFFSET 0x70000 +#define TZPC8_OFFSET 0x80000 +#define TZPC9_OFFSET 0x90000 + +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + + +// Exynos5250 CMU Base Address +#define Exynos5250_CMU_DELAY 0x2000 +#define Exynos5250_CMU_BASE 0x10010000 +#define Exynos5250_CMU_DIV_DMC0 0x10500 + +#define APLL_AFC_ENB 0x1 +#define APLL_AFC 0xC + +/* MPLL_CON1 */ +#define MPLL_AFC_ENB 0x0 +#if defined(CONFIG_CLK_800_330_165) || defined(CONFIG_CLK_1000_330_165) +#define MPLL_AFC 0xD +#elif defined(CONFIG_CLK_1000_400_200) || defined(CONFIG_CLK_1000_200_200) || defined(CONFIG_CLK_800_400_200) +#define MPLL_AFC 0x1C +#endif + +#define EPLL_PDIV 0x3 +#define EPLL_K 0x0 +#define VPLL_PDIV 0x3 +#define VPLL_SDIV 0x2 + +#define VPLL_SSCG_EN 0x0 +#define VPLL_SEL_PF 0x0 +#define VPLL_MRR 0x11 +#define VPLL_MFR 0x0 +#define VPLL_K 0x400 +/********************************************************/ + +/* Set PLL */ +#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL_MOUTAPLL 0 +#define MUX_HPM_SEL_SCLKMPLL 1 +#define MUX_CORE_SEL_MOUTAPLL 0 +#define MUX_CORE_SEL_SCLKMPLL 1 + +/* 0 = FILPLL, 1 = MOUT */ +#define MUX_MPLL_SEL_FILPLL 0 +#define MUX_MPLL_SEL_MOUTMPLLFOUT 1 + +#define MUX_APLL_SEL_FILPLL 0 +#define MUX_APLL_SEL_MOUTMPLLFOUT 1 + +#define CLK_SRC_CPU_VAL_FINPLL ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL <<16) \ + | (MUX_MPLL_SEL_FILPLL << 8) \ + | (MUX_APLL_SEL_FILPLL <<0)) + +#define CLK_SRC_CPU_VAL_MOUTMPLLFOUT ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL <<16) \ + | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8) \ + | (MUX_APLL_SEL_MOUTMPLLFOUT <<0)) + +/* CLK_DIV_CPU0 */ +#define APLL_RATIO 0x1 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define COREM0_RATIO 0x3 +#define CORE_RATIO 0x0 + +/* CLK_DIV_CPU1 */ +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x3 +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) + +/* CLK_SRC_DMC */ +#define MUX_PWI_SEL 0x0 +#define MUX_CORE_TIMERS_SEL 0x0 +#define MUX_DPHY_SEL 0x0 +#define MUX_DMC_BUS_SEL 0x0 +#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL << 16) \ + | (MUX_CORE_TIMERS_SEL << 12) \ + | (MUX_DPHY_SEL << 8) \ + | (MUX_DMC_BUS_SEL << 4)) + +/* CLK_DIV_DMC0 */ +#if defined(CONFIG_CLK_1000_200_200) +#define CORE_TIMERS_RATIO 0x1 +#define COPY2_RATIO 0x3 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x0 +#define DMC_RATIO 0x3 +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 +#else +#define CORE_TIMERS_RATIO 0x1 +#define COPY2_RATIO 0x3 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#define DMC_RATIO 0x1 +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#endif +#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ + | (COPY2_RATIO << 24) \ + | (DMCP_RATIO << 20) \ + | (DMCD_RATIO << 16) \ + | (DMC_RATIO << 12) \ + | (DPHY_RATIO << 8) \ + | (ACP_PCLK_RATIO << 4) \ + | (ACP_RATIO)) + +/* CLK_DIV_DMC1 */ +#define DPM_RATIO 0x1 +#define DVSEM_RATIO 0x1 +#define PWI_RATIO 0x1 +#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ + | (DVSEM_RATIO << 16) \ + | (PWI_RATIO << 8)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166 */ +#define MUX_ACLK_133_SEL 0x0 /* 0 = SCLKMPLL, 1 = SCLKAPLL */ +#define MUX_ACLK_160_SEL 0x0 +#define MUX_ACLK_100_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_VPLL_SEL 0x0 +#define MUX_EPLL_SEL 0x0 + +/* CLK_SRC_TOP1 */ +#define VPLLSRC_SEL 0x0 /* 0 = FINPLL, 1 = SCLKHDMI27M */ + +/* CLK_DIV_TOP */ +#define ONENAND_RATIO 0x0 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x3 +#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ + | (ACLK_133_RATIO << 12) \ + | (ACLK_160_RATIO << 8) \ + | (ACLK_100_RATIO << 4) \ + | (ACLK_200_RATIO)) + +/* CLK_SRC_LEFTBUS */ +#define MUX_GDL_SEL 0x0 +#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL) + +/* CLK_DIV_LEFRBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFRBUS_VAL ((GPL_RATIO << 4) \ + | (GDL_RATIO)) + +/* CLK_SRC_RIGHTBUS */ +#define MUX_GDR_SEL 0x0 +#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL) + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) \ + | (GDR_RATIO)) + +#define PLL_LOCKTIME 0x1C20 + +/* CLK_SRC_PERIL0 */ +#define PWM_SEL 0 +#define UART5_SEL 6 +#define UART4_SEL 6 +#define UART3_SEL 6 +#define UART2_SEL 6 +#define UART1_SEL 6 +#define UART0_SEL 6 +#define CLK_SRC_PERIL0_VAL ((PWM_SEL << 24)\ + | (UART5_SEL << 20) \ + | (UART4_SEL << 16) \ + | (UART3_SEL << 12) \ + | (UART2_SEL<< 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL)) + +/* CLK_DIV_PERIL0 */ +#if defined(CONFIG_CLK_800_330_165) || defined(CONFIG_CLK_1000_330_165) +#define UART5_RATIO 7 +#define UART4_RATIO 7 +#define UART3_RATIO 7 +#define UART2_RATIO 7 +#define UART1_RATIO 7 +#define UART0_RATIO 7 +#elif defined(CONFIG_CLK_1000_400_200) || defined(CONFIG_CLK_1000_200_200) || defined(CONFIG_CLK_800_400_200) +#define UART5_RATIO 8 +#define UART4_RATIO 8 +#define UART3_RATIO 8 +#define UART2_RATIO 8 +#define UART1_RATIO 8 +#define UART0_RATIO 8 +#endif +#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 20) \ + | (UART4_RATIO << 16) \ + | (UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO)) + +#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1))) + +#if defined(CONFIG_CLK_800_330_165) || defined(CONFIG_CLK_1000_330_165) +#define UART_UBRDIV_VAL 0x2B/* (SCLK_UART/(115200*16) -1) */ +#define UART_UDIVSLOT_VAL 0xC /*((((SCLK_UART*10/(115200*16) -10))%10)*16/10)*/ +#elif defined(CONFIG_CLK_1000_400_200) || defined(CONFIG_CLK_1000_200_200) || defined(CONFIG_CLK_800_400_200) +#define UART_UBRDIV_VAL 0x2F /* (SCLK_UART/(115200*16) -1) */ +#define UART_UDIVSLOT_VAL 0x3 /*((((SCLK_UART*10/(115200*16) -10))%10)*16/10)*/ +#endif + +#define UART_115200_IDIV UART_UBRDIV_VAL +#define UART_115200_FDIV UART_UDIVSLOT_VAL + +#define UART_38400_IDIV UART_UBRDIV_VAL +#define UART_38400_FDIV UART_UDIVSLOT_VAL + +#define UART_19200_IDIV UART_UBRDIV_VAL +#define UART_19200_FDIV UART_UDIVSLOT_VAL + +#define UART_LCON_VAL 0x03 +#define UART_ECR_VAL 0x111 +#define UART_CR_VAL 0x3C5 + +// System Configuration Controller register Base addresses +#define SYS_DISP1BLK_CFG_OFFSET (0x0214) +#define FIMDBYPASS_DISP1 (0x01 << 15) + +//FIMD register offsets +#define VIDCON0_OFFSET (0x00) +#define VIDCON1_OFFSET (0x20004)/* Video control 1 */ +#define VIDCON2_OFFSET (0x0008) /* Video control 2 */ +#define VIDTCON0_OFFSET (0x20010) /* Video time control 0 */ +#define VIDTCON1_OFFSET (0x20014) /* Video time control 1 */ +#define VIDTCON2_OFFSET (0x20018) /* Video time control 2 */ +#define SHADOWCON_OFFSET (0x0034) /* Window Shadow control */ +#define WINCON_OFFSET(x) (0x0020 + (x * 0x04)) +#define VIDOSD_A_OFFSET(x) (0x0040 + (x * 0x10)) +#define VIDOSD_B_OFFSET(x) (0x0044 + (x * 0x10)) +#define VIDOSD_C_OFFSET(x) (0x0048 + (x * 0x10)) +#define VIDADDR_START0_OFFSET(x)(0x00A0 + (x * 0x08)) +#define VIDADDR_END0_OFFSET(x) (0x00D0 + (x * 0x08)) +#define VIDADDR_SIZE_OFFSET(x) (0x0100 + (x * 0x04)) + +// MIPI-DSIM register offsets +#define DSIM_STATUS (0x00) +#define DSIM_SWRST (0x04) +#define DSIM_CLKCTRL (0x08) +#define DSIM_TIMEOUT (0x0C) +#define DSIM_CONFIG (0x10) +#define DSIM_ESCMODE (0x14) +#define DSIM_MDRESOL (0x18) +#define DSIM_MVPORCH (0x1C) +#define DSIM_MHPORCH (0x20) +#define DSIM_MSYNC (0x24) +#define DSIM_SDRESOL (0x28) +#define DSIM_INTSRC (0x2C) +#define DSIM_INTMSK (0x30) +#define DSIM_PKTHDR (0x34) +#define DSIM_PAYLOAD (0x38) +#define DSIM_RXFIFO (0x3C) +#define DSIM_FIFOTHLD (0x40) +#define DSIM_FIFOCTRL (0x44) +#define DSIM_MEMACCHR (0x48) +#define DSIM_PLLCTRL (0x4C) +#define DSIM_PLLTMR (0x50) +#define DSIM_PHYACCHR (0x54) +#define DSIM_PHYACCHR1 (0x58) + +// RTC register offset +#define EXYNOS_RTCREG(x) (x) +#define EXYNOS_INTP EXYNOS_RTCREG(0x30) +#define EXYNOS_INTP_ALM (1 << 1) +#define EXYNOS_INTP_TIC (1 << 0) + +#define EXYNOS_RTCCON EXYNOS_RTCREG(0x40) +#define EXYNOS_RTCCON_RTCEN (1<<0) +#define EXYNOS_RTCCON_CLKSEL (1<<1) +#define EXYNOS_RTCCON_CNTSEL (1<<2) +#define EXYNOS_RTCCON_CLKRST (1<<3) +#define EXYNOS_RTCCON_TICEN (1<<8) + +#define EXYNOS_RTCCON_TICMSK (0xF<<7) +#define EXYNOS_RTCCON_TICSHT (7) + +#define EXYNOS_TICNT EXYNOS_RTCREG(0x44) +#define EXYNOS_TICNT_ENABLE (1<<7) + +#define EXYNOS_RTCALM EXYNOS_RTCREG(0x50) +#define EXYNOS_RTCALM_ALMEN (1<<6) +#define EXYNOS_RTCALM_YEAREN (1<<5) +#define EXYNOS_RTCALM_MONEN (1<<4) +#define EXYNOS_RTCALM_DAYEN (1<<3) +#define EXYNOS_RTCALM_HOUREN (1<<2) +#define EXYNOS_RTCALM_MINEN (1<<1) +#define EXYNOS_RTCALM_SECEN (1<<0) + +#define EXYNOS_RTCALM_ALL \ + EXYNOS_RTCALM_ALMEN | EXYNOS_RTCALM_YEAREN | EXYNOS_RTCALM_MONEN |\ + EXYNOS_RTCALM_DAYEN | EXYNOS_RTCALM_HOUREN | EXYNOS_RTCALM_MINEN |\ + EXYNOS_RTCALM_SECEN + + +#define EXYNOS_ALMSEC EXYNOS_RTCREG(0x54) +#define EXYNOS_ALMMIN EXYNOS_RTCREG(0x58) +#define EXYNOS_ALMHOUR EXYNOS_RTCREG(0x5c) + +#define EXYNOS_ALMDAY EXYNOS_RTCREG(0x60) +#define EXYNOS_ALMMON EXYNOS_RTCREG(0x64) +#define EXYNOS_ALMYEAR EXYNOS_RTCREG(0x68) + +//#define EXYNOS_RTCRST EXYNOS_RTCREG(0x6c) + +#define EXYNOS_BCDSEC EXYNOS_RTCREG(0x70) +#define EXYNOS_BCDMIN EXYNOS_RTCREG(0x74) +#define EXYNOS_BCDHOUR EXYNOS_RTCREG(0x78) +#define EXYNOS_BCDDAY EXYNOS_RTCREG(0x7c) +#define EXYNOS_BCDDAYWEEK EXYNOS_RTCREG(0x80) +#define EXYNOS_BCDMON EXYNOS_RTCREG(0x84) +#define EXYNOS_BCDYEAR EXYNOS_RTCREG(0x88) + +// Kimoon add RTC clock gate +#define CLK_GATE_IP_PERIR (0xC960) +#define CLK_RTC_OFFSET (0x1 << 15) +#define CLK_RTC_MASK (0x0 << 15) +#define CLK_RTC_UNMASK (0x1 << 15) + +//#define CLK_DIV_FSYS2 (CLK_BASE + 0xC548) +//#define CLK_DIV_FSYS3 (CLK_BASE + 0xC54C) + + +/******************************************* +* Interrupt Map +*******************************************/ + +// Timer Interrupts +#define Exynos5250_INT_NUM(x) ((x) + 32) + +#define PWM_TIMER0_INTERRUPT_NUM Exynos5250_INT_NUM(36) +#define PWM_TIMER1_INTERRUPT_NUM Exynos5250_INT_NUM(37) +#define PWM_TIMER2_INTERRUPT_NUM Exynos5250_INT_NUM(38) +#define PWM_TIMER3_INTERRUPT_NUM Exynos5250_INT_NUM(39) +#define PWM_TIMER4_INTERRUPT_NUM Exynos5250_INT_NUM(40) + +/******************************************* +* EFI Memory Map in Permanent Memory (DRAM) +*******************************************/ + +//gpio definitions as required by the Embedded gpio module +#define DISTANCE_BTWN_PORTS (0x20) + +#define GPIO_CON (0x00) +#define GPIO_DATAIN (0x04) +#define GPIO_PUD (0x08) +#define GPIO_DRV (0x0C) + +#define GPIO_DATAIN_MASK(x) (1UL << (x)) +#define GPIO_PUD_MASK(x) (3UL << (x*2)) +#define GPIO_DRV_MASK(x) (3UL << (x*2)) +#define GPIO_SFN_MASK(x) (15UL <<(x*4)) + +#define GPIO_SFN_EN(x) (2UL << (x*4)) +#define GPIO_OP_EN(x) (1UL << (x*4)) + +#define GPIO_PUD_DIS(x) (0UL << (x*2)) +#define GPIO_PDN_EN(x) (1UL << (x*2)) +#define GPIO_PUP_EN(x) (3UL << (x*2)) +#define GPIO_DATA_HIGH(x) (1UL << (x)) +#define GPIO_DATA_LOW(x) (0UL << (x)) + +#define GPIO_DRV_SET(strength,pin) (strength << (pin*2)) + +#define PIN0 (0x00) +#define PIN1 (0x01) +#define PIN2 (0x02) +#define PIN3 (0x03) +#define PIN4 (0x04) +#define PIN5 (0x05) +#define PIN6 (0x06) +#define PIN7 (0x07) + +// 0x1140_0000 +#define GPA0 (0x00) +#define GPA1 (0x01) +#define GPA2 (0x02) +#define GPB0 (0x03) +#define GPB1 (0x04) +#define GPB2 (0x05) +#define GPB3 (0x06) +#define GPC0 (0x07) +#define GPC1 (0x08) +#define GPC2 (0x09) +#define GPC3 (0x0A) +#define GPD0 (0x0B) +#define GPD1 (0x0C) +#define GPY0 (0x0D) +#define GPY1 (0x0E) +#define GPY2 (0x0F) +#define GPY3 (0x10) +#define GPY4 (0x11) +#define GPY5 (0x12) +#define GPY6 (0x13) +#define GPX0 (0x60) +#define GPX1 (0x61) +#define GPX2 (0x62) +#define GPX3 (0x63) + +// 0x1340_0000 +#define GPE0 (0x70) +#define GPE1 (0x71) +#define GPF0 (0x72) +#define GPF1 (0x73) +#define GPG0 (0x74) +#define GPG1 (0x75) +#define GPG2 (0x76) +#define GPH0 (0x77) +#define GPH1 (0x78) + +// 0x10D1_0000 +#define GPV0 (0x80) +#define GPV1 (0x81) +// ETC5PUD +#define GPV2 (0x83) +#define GPV3 (0x84) +// ETC8PUD +#define GPV4 (0x86) + +// 0x0386_0000 +#define GPZ (0x90) + +#define LCD_BACKLIGHT GPIO(GPB2,PIN0) +#define LCD_RESET GPIO(GPX1,PIN5) +#define LCD_POWER GPIO(GPX3,PIN0) + +/* SDHC GPIO Pin Configuration for GAIA */ +#define SD_2_EVT1_CLK GPIO(GPC3,PIN0) +#define SD_2_EVT1_CMD GPIO(GPC3,PIN1) +#define SD_2_EVT1_CDn GPIO(GPC3,PIN2) +#define SD_2_EVT1_DATA0 GPIO(GPC3,PIN3) +#define SD_2_EVT1_DATA1 GPIO(GPC3,PIN4) +#define SD_2_EVT1_DATA2 GPIO(GPC3,PIN5) +#define SD_2_EVT1_DATA3 GPIO(GPC3,PIN6) + +#define SD_2_CLK GPIO(GPC2,PIN0) +#define SD_2_CMD GPIO(GPC2,PIN1) +#define SD_2_CDn GPIO(GPC2,PIN2) +#define SD_2_DATA0 GPIO(GPC2,PIN3) +#define SD_2_DATA1 GPIO(GPC2,PIN4) +#define SD_2_DATA2 GPIO(GPC2,PIN5) +#define SD_2_DATA3 GPIO(GPC2,PIN6) +#define SD_2_DATA4 GPIO(GPC3,PIN3) +#define SD_2_DATA5 GPIO(GPC3,PIN4) +#define SD_2_DATA6 GPIO(GPC3,PIN5) +#define SD_2_DATA7 GPIO(GPC3,PIN6) + +/* USB 2.0 GPIO Pin Configuration for GAIA Evt1 */ +#define USB_2_EVT1 GPIO(GPX2,PIN6) + +/* SDHC CH0 GPIO Pin Configuration for GAIA */ +#define SD_0_CLK GPIO(GPC0,PIN0) +#define SD_0_CMD GPIO(GPC0,PIN1) +#define SD_0_CDn GPIO(GPC0,PIN2) +#define SD_0_DATA0 GPIO(GPC0,PIN3) +#define SD_0_DATA1 GPIO(GPC0,PIN4) +#define SD_0_DATA2 GPIO(GPC0,PIN5) +#define SD_0_DATA3 GPIO(GPC0,PIN6) +#define SD_0_DATA4 GPIO(GPC1,PIN0) +#define SD_0_DATA5 GPIO(GPC1,PIN1) +#define SD_0_DATA6 GPIO(GPC1,PIN2) +#define SD_0_DATA7 GPIO(GPC1,PIN3) + + +#define CLK_DIV_FSYS1_OFFSET 0x1054C +#define CLK_DIV_FSYS2_OFFSET 0x10550 + +#endif diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Arndale5250.h b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Arndale5250.h new file mode 100644 index 000000000..0762b8aeb --- /dev/null +++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Arndale5250.h @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * HeungJun Kim <riverful.kim@samsung.com> + * Inki Dae <inki.dae@samsung.com> + * + * Configuation settings for the SAMSUNG ARNDALE board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ +#define CONFIG_ARCH_EXYNOS 1 /* which is in a Exynos Family */ +#define CONFIG_ARCH_EXYNOS5 1 /* which is in a Exynos5 Family */ +#define CONFIG_CPU_EXYNOS5250 1 /* which is in a Exynos5250 */ +#define CONFIG_MACH_SMDK5250 1 /* which is in a ARNDALE */ +#define CONFIG_EVT1 1 /* EVT1 */ +//#define CONFIG_CORTEXA5_ENABLE 1 /* enable coretex-A5(IOP) Booting */ + +#define CONFIG_SECURE_BL1_ONLY +//#define CONFIG_SECURE_BOOT +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_S5PC210S +#define CONFIG_SECURE_ROOTFS +#define CONFIG_SECURE_KERNEL_BASE 0xc0008000 +#define CONFIG_SECURE_KERNEL_SIZE 0x200000 +#define CONFIG_SECURE_ROOTFS_BASE 0xc1000000 +#define CONFIG_SECURE_ROOTFS_SIZE 0x5c2000 +#endif + +//#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_CLK_ARM_1000_APLL_1000 + +#define MCLK_CDREX_533 1 +#define RD_LVL 1 + +/* (Memory Interleaving Size = 1 << IV_SIZE) */ +#define CONFIG_IV_SIZE 0x07 + +#define CONFIG_L2_OFF + +//#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_DISPLAY_CPUINFO +//#define CONFIG_DISPLAY_BOARDINFO +#define BOARD_LATE_INIT + +/* input clock of PLL: ARNDALE has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* Power Management is enabled */ +//#define CONFIG_PM +//#define CONFIG_INVERSE_PMIC_I2C 1 +#define CONFIG_PM_VDD_ARM 1.1 +#define CONFIG_PM_VDD_INT 1.0 +#define CONFIG_PM_VDD_G3D 1.1 +#define CONFIG_PM_VDD_MIF 1.1 +#define CONFIG_PM_VDD_LDO14 1.8 + +/* + * Size of malloc() pool + * 1MB = 0x100000, 0x100000 = 1024 * 1024 + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + /* initial data */ +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 +#define CONFIG_SERIAL_MULTI 1 + +#define CONFIG_USB_OHCI +#undef CONFIG_USB_STORAGE +//#define CONFIG_S3C_USBD +#define CONFIG_EXYNOS_USBD3 + +#define USBD_DOWN_ADDR 0xc0000000 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ + +#define CONFIG_CMD_PING + +#define CONFIG_CMD_USB + +#define CONFIG_CMD_MOVINAND + +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NAND + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MOVI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_SYS_ONENAND_QUIET_TEST + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_S3C_HSMMC + +/* The macro for MMC channel 0 is defined by default and can't be undefined */ + +/* Notice for MSHC[Using of MMC CH4] */ +/* + * If you want MSHC at MMC CH4. + */ + +#define MMC_MAX_CHANNEL 5 + +#define USE_MMC2 +#define USE_MMC4 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + +#define CONFIG_ETHADDR 00:40:5c:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.20 +#define CONFIG_SERVERIP 192.168.0.10 +#define CONFIG_GATEWAYIP 192.168.0.1 + +#define CONFIG_BOOTDELAY 3 +/* Default boot commands for Android booting. */ +#define CONFIG_BOOTCOMMAND "movi read kernel 0 40008000;movi read rootfs 0 41000000 100000;bootm 40008000 41000000" +#define CONFIG_BOOTARGS "" + +#define CONFIG_BOOTCOMMAND2 \ + "mmc erase user 0 1072 1;" \ + "movi r f 1 40000000;emmc open 0;movi w z f 0 40000000;emmc close 0;" \ + "movi r u 1 40000000;emmc open 0;movi w z u 0 40000000;emmc close 0;" \ + "movi r k 1 40000000;movi w k 0 40000000;" \ + "movi r r 1 40000000 100000;movi w r 0 40000000 100000;" \ + "fdisk -c 0;" \ + "movi init 0;" \ + "fatformat mmc 0:1;" \ + "mmc read 1 48000000 20000 a0000;" \ + "fastboot flash system 48000000;" \ + "mmc read 1 48000000 c0000 a0000;" \ + "fastboot flash userdata 48000000;" \ + "mmc read 1 48000000 160000 a0000;" \ + "fastboot flash cache 48000000;" \ + "reset" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "ARNDALE# " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000) + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ + +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE 0x10000000 /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + 2 * SDRAM_BANK_SIZE) /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + 3 * SDRAM_BANK_SIZE) /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + 4 * SDRAM_BANK_SIZE) /* SDRAM Bank #5 */ +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + 5 * SDRAM_BANK_SIZE) /* SDRAM Bank #6 */ +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + 6 * SDRAM_BANK_SIZE) /* SDRAM Bank #7 */ +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + 7 * SDRAM_BANK_SIZE) /* SDRAM Bank #8 */ +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH 1 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ +#define CONFIG_IDENT_STRING " for ARNDALE" + +#define CONFIG_ENABLE_MMU + +#ifdef CONFIG_ENABLE_MMU +#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 +#define virt_to_phys(x) virt_to_phy_exynos5250(x) +#else +#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE +#define virt_to_phys(x) (x) +#endif + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_MAPPED_RAM_BASE + 0x3e00000 +#define CONFIG_PHY_UBOOT_BASE CONFIG_SYS_SDRAM_BASE + 0x3e00000 + +/* + * Fast Boot +*/ +/* Fastboot variables */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (0x48000000) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (0x10000000) /* 256MB */ +#define CFG_FASTBOOT_ADDR_KERNEL (0x40008000) +#define CFG_FASTBOOT_ADDR_RAMDISK (0x40800000) +#define CFG_FASTBOOT_PAGESIZE (2048) // Page size of booting device +#define CFG_FASTBOOT_SDMMC_BLOCKSIZE (512) // Block size of sdmmc +#define CFG_PARTITION_START (0x4000000) + +/* Just one BSP type should be defined. */ +#if defined(CONFIG_CMD_MOVINAND) +#define CONFIG_FASTBOOT +#endif + +#if defined(CONFIG_CMD_MOVINAND) +#define CFG_FASTBOOT_SDMMCBSP +#endif + +/* + * machine type + */ + +#define MACH_TYPE 3774 /* ARNDALE machine ID */ + +#define CONFIG_ENV_OFFSET 0x0007C000 + +/*----------------------------------------------------------------------- + * Boot configuration + */ +#define BOOT_ONENAND 0x1 +#define BOOT_NAND 0x40000 +#define BOOT_MMCSD 0x3 +#define BOOT_NOR 0x4 +#define BOOT_SEC_DEV 0x5 +#define BOOT_EMMC 0x6 +#define BOOT_EMMC_4_4 0x7 + +#define CONFIG_ZIMAGE_BOOT + +#define CONFIG_ENV_IS_IN_AUTO 1 +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_DOS_PARTITION 1 + +//#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) +#define CONFIG_SYS_INIT_SP_ADDR (0x43e00000 - 0x1000000) + +/* + * Ethernet Contoller driver + */ +#define CONFIG_CMD_NET 1 +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x5000000 +#define CONFIG_SMC911X_16_BIT +#endif /* CONFIG_CMD_NET */ + +/* GPIO */ +#define GPIO_BASE 0x11400000 + +#define CFG_PHY_UBOOT_BASE MEMORY_BASE_ADDRESS + 0x3e00000 +#define CFG_PHY_KERNEL_BASE MEMORY_BASE_ADDRESS + 0x8000 + +#define MEMORY_BASE_ADDRESS 0x40000000 + +#endif /* __CONFIG_H */ diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Arndale5250_Val.h b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Arndale5250_Val.h new file mode 100755 index 000000000..d6cdd1d9d --- /dev/null +++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Arndale5250_Val.h @@ -0,0 +1,402 @@ +/* + * (C) Copyright 2012 Samsung Electronics Co. Ltd + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _VAL_ARNDALE5250_H +#define _VAL_ARNDALE5250_H + +#if defined(CONFIG_CLK_ARM_800_APLL_800) + +#define APLL_MDIV 0x64 +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +#elif defined(CONFIG_CLK_ARM_1000_APLL_1000) + +#define APLL_MDIV 0x7D +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +#elif defined(CONFIG_CLK_ARM_1200_APLL_1200) + +#define APLL_MDIV 0x96 +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +#elif defined(CONFIG_CLK_ARM_1400_APLL_1400) + +#define APLL_MDIV 0xAF +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +#elif defined(CONFIG_CLK_ARM_1700_APLL_1700) + +#define APLL_MDIV 0xAF +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 +#endif + +#define MPLL_MDIV 0x64 +#define MPLL_PDIV 0x3 +#define MPLL_SDIV 0x0 + +#define CPLL_MDIV 0xDE +#define CPLL_PDIV 0x4 +#define CPLL_SDIV 0x2 + +#define GPLL_MDIV 0x215 +#define GPLL_PDIV 0xC +#define GPLL_SDIV 0x1 + +/* APLL_CON1 */ +#define APLL_CON1_VAL (0x00203800) + +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x00203800) + +/* CPLL_CON1 */ +#define CPLL_CON1_VAL (0x00203800) + +/* GPLL_CON1 */ +#define GPLL_CON1_VAL (0x00203800) + +#define EPLL_MDIV 0x60 +#define EPLL_PDIV 0x3 +#define EPLL_SDIV 0x3 + +#define EPLL_CON1_VAL 0x00000000 +#define EPLL_CON2_VAL 0x00000080 + +#define VPLL_MDIV 0x96 +#define VPLL_PDIV 0x3 +#define VPLL_SDIV 0x2 + +/* VPLL_CON1, CON2 */ +#define VPLL_CON1_VAL 0x00000000 +#define VPLL_CON2_VAL 0x00000080 + +#define BPLL_MDIV 0x64 +#define BPLL_PDIV 0x3 +#define BPLL_SDIV 0x0 + +/* BPLL_CON1 */ +#define BPLL_CON1_VAL 0x00203800 + +/* Set PLL */ +#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) + +#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV) +#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) +#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV) +#define GPLL_CON0_VAL set_pll(GPLL_MDIV, GPLL_PDIV, GPLL_SDIV) +#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) +#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) +#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV) + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL 0 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 + +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ + | (MUX_CPU_SEL << 16) \ + | (MUX_APLL_SEL)) + +/* CLK_DIV_CPU0 */ +#if defined(CONFIG_CLK_ARM_600_APLL_600) +#define ARM2_RATIO 0x0 +#define APLL_RATIO 0x1 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x2 +#define PERIPH_RATIO 0x7 +#define ACP_RATIO 0x7 +#define CPUD_RATIO 0x1 +#define ARM_RATIO 0x0 + +#elif defined(CONFIG_CLK_ARM_800_APLL_800) + +#define ARM2_RATIO 0x0 +#define APLL_RATIO 0x1 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x3 +#define PERIPH_RATIO 0x7 +#define ACP_RATIO 0x7 +#define CPUD_RATIO 0x2 +#define ARM_RATIO 0x0 + +#elif defined(CONFIG_CLK_ARM_1000_APLL_1000) + +#define ARM2_RATIO 0x0 +#define APLL_RATIO 0x1 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x4 +#define PERIPH_RATIO 0x7 +#define ACP_RATIO 0x7 +#define CPUD_RATIO 0x2 +#define ARM_RATIO 0x0 + +#elif defined(CONFIG_CLK_ARM_1200_APLL_1200) + +#define ARM2_RATIO 0x0 +#define APLL_RATIO 0x3 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x5 +#define PERIPH_RATIO 0x7 +#define ACP_RATIO 0x7 +#define CPUD_RATIO 0x3 +#define ARM_RATIO 0x0 + +#elif defined(CONFIG_CLK_ARM_1400_APLL_1400) + +#define ARM2_RATIO 0x0 +#define APLL_RATIO 0x3 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x6 +#define PERIPH_RATIO 0x7 +#define ACP_RATIO 0x7 +#define CPUD_RATIO 0x3 +#define ARM_RATIO 0x0 + +#elif defined(CONFIG_CLK_ARM_1700_APLL_1700) + +#define ARM2_RATIO 0x0 +#define APLL_RATIO 0x3 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x6 +#define PERIPH_RATIO 0x7 +#define ACP_RATIO 0x7 +#define CPUD_RATIO 0x3 +#define ARM_RATIO 0x0 +#endif + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ + | (APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (ACP_RATIO << 8) \ + | (CPUD_RATIO << 4) \ + | (ARM_RATIO)) + +/* CLK_DIV_CPU1 */ +#define HPM_RATIO 0x2 +#define COPY_RATIO 0x0 + +/* CLK_DIV_CPU1 = 0x00000003 */ +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ + | (COPY_RATIO)) + +/* CLK_SRC_CORE0 */ +#define CLK_SRC_CORE0_VAL 0x00000000 + +/* CLK_SRC_CORE1 */ +#define CLK_SRC_CORE1_VAL 0x100 + +/* CLK_DIV_CORE0 */ +#define CLK_DIV_CORE0_VAL 0x00120000 + +/* CLK_DIV_CORE1 */ +#define CLK_DIV_CORE1_VAL 0x07070700 + +/* CLK_DIV_SYSRGT */ +#define CLK_DIV_SYSRGT_VAL 0x00000111 + +/* CLK_DIV_ACP */ +#define CLK_DIV_ACP_VAL 0x12 + +/* CLK_DIV_SYSLFT */ +#define CLK_DIV_SYSLFT_VAL 0x00000311 + +/* CLK_SRC_CDREX */ +#define CLK_SRC_CDREX_VAL 0x1 + +/* CLK_DIV_CDREX */ +#define MCLK_DPHY_RATIO 0x1 +#define MCLK_CDREX_RATIO 0x1 +#define ACLK_C2C_200_RATIO 0x1 +#define C2C_CLK_400_RATIO 0x1 +#define PCLK_CDREX_RATIO 0x1 +#define ACLK_CDREX_RATIO 0x1 + +#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \ + | (MCLK_CDREX_RATIO << 16) \ + | (ACLK_C2C_200_RATIO << 12) \ + | (C2C_CLK_400_RATIO << 8) \ + | (PCLK_CDREX_RATIO << 4) \ + | (ACLK_CDREX_RATIO)) \ +/* CLK_SRC_TOP0 */ +#define MUX_ACLK_300_GSCL_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID_SEL 0x0 +#define MUX_ACLK_400_G3D_MID_SEL 0x0 +#define MUX_ACLK_333_SEL 0x0 +#define MUX_ACLK_300_DISP1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_ACLK_166_SEL 0x0 +#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ + | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ + | (MUX_ACLK_400_G3D_MID_SEL << 20) \ + | (MUX_ACLK_333_SEL << 16) \ + | (MUX_ACLK_300_DISP1_SEL << 15) \ + | (MUX_ACLK_300_DISP1_MID_SEL << 14) \ + | (MUX_ACLK_200_SEL << 12) \ + | (MUX_ACLK_166_SEL << 8)) + +/* CLK_SRC_TOP1 */ +#define MUX_ACLK_400_G3D_SEL 0x1 +#define MUX_ACLK_400_ISP_SEL 0x0 +#define MUX_ACLK_400_IOP_SEL 0x0 +#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 +#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ + |(MUX_ACLK_400_ISP_SEL << 24) \ + |(MUX_ACLK_400_IOP_SEL << 20) \ + |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ + |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ + |(MUX_ACLK_300_DISP1_MID1_SEL << 8)) + +/* CLK_SRC_TOP2 */ +#define MUX_GPLL_SEL 0x1 +#define MUX_BPLL_USER_SEL 0x0 +#define MUX_MPLL_USER_SEL 0x0 +#define MUX_VPLL_SEL 0x1 +#define MUX_EPLL_SEL 0x1 +#define MUX_CPLL_SEL 0x1 +#define VPLLSRC_SEL 0x0 +#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ + | (MUX_BPLL_USER_SEL << 24) \ + | (MUX_MPLL_USER_SEL << 20) \ + | (MUX_VPLL_SEL << 16) \ + | (MUX_EPLL_SEL << 12) \ + | (MUX_CPLL_SEL << 8) \ + | (VPLLSRC_SEL)) +/* CLK_SRC_TOP3 */ +#define MUX_ACLK_333_SUB_SEL 0x1 +#define MUX_ACLK_400_SUB_SEL 0x1 +#define MUX_ACLK_266_ISP_SUB_SEL 0x1 +#define MUX_ACLK_266_GPS_SUB_SEL 0x0 +#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 +#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 +#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ + | (MUX_ACLK_400_SUB_SEL << 20) \ + | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ + | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ + | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ + | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ + | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ + | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) + +/* CLK_DIV_TOP0 */ +#define ACLK_300_DISP1_RATIO 0x2 +#define ACLK_400_G3D_RATIO 0x0 +#define ACLK_333_RATIO 0x0 +#define ACLK_266_RATIO 0x2 +#define ACLK_200_RATIO 0x3 +#define ACLK_166_RATIO 0x1 +#define ACLK_133_RATIO 0x1 +#define ACLK_66_RATIO 0x5 + +#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \ + | (ACLK_400_G3D_RATIO << 24) \ + | (ACLK_333_RATIO << 20) \ + | (ACLK_266_RATIO << 16) \ + | (ACLK_200_RATIO << 12) \ + | (ACLK_166_RATIO << 8) \ + | (ACLK_133_RATIO << 4) \ + | (ACLK_66_RATIO)) + +/* CLK_DIV_TOP1 */ +#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 +#define ACLK_66_PRE_RATIO 0x1 +#define ACLK_400_ISP_RATIO 0x1 +#define ACLK_400_IOP_RATIO 0x1 +#define ACLK_300_GSCL_RATIO 0x2 + +#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ + | (ACLK_66_PRE_RATIO << 24) \ + | (ACLK_400_ISP_RATIO << 20) \ + | (ACLK_400_IOP_RATIO << 16) \ + | (ACLK_300_GSCL_RATIO << 12)) + +/* APLL_LOCK */ +#define APLL_LOCK_VAL (0x546) +/* MPLL_LOCK */ +#define MPLL_LOCK_VAL (0x546) +/* CPLL_LOCK */ +#define CPLL_LOCK_VAL (0x546) +/* GPLL_LOCK */ +#define GPLL_LOCK_VAL (0x546) +/* EPLL_LOCK */ +#define EPLL_LOCK_VAL (0x3A98) +/* VPLL_LOCK */ +#define VPLL_LOCK_VAL (0x3A98) +/* BPLL_LOCK */ +#define BPLL_LOCK_VAL (0x546) + +/* CLK_SRC_PERIC0 */ +#define PWM_SEL 0 +#define UART3_SEL 6 +#define UART2_SEL 6 +#define UART1_SEL 6 +#define UART0_SEL 6 +/* SRC_CLOCK = SCLK_MPLL */ +#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ + | (UART3_SEL << 12) \ + | (UART2_SEL<< 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL)) + +/* CLK_DIV_PERIL0 */ +#define UART5_RATIO 7 +#define UART4_RATIO 7 +#define UART3_RATIO 7 +#define UART2_RATIO 7 +#define UART1_RATIO 7 +#define UART0_RATIO 7 + +#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO)) +/* CLK_SRC_LEX */ +#define CLK_SRC_LEX_VAL 0x0 + +/* CLK_DIV_LEX */ +#define CLK_DIV_LEX_VAL 0x10 + +/* CLK_DIV_R0X */ +#define CLK_DIV_R0X_VAL 0x10 + +/* CLK_DIV_L0X */ +#define CLK_DIV_R1X_VAL 0x10 + +/* CLK_DIV_ISP0 */ +#define CLK_DIV_ISP0_VAL 0x31 + +/* CLK_DIV_ISP1 */ +#define CLK_DIV_ISP1_VAL 0x0 + +/* CLK_DIV_ISP2 */ +#define CLK_DIV_ISP2_VAL 0x1 + +#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1))) + +#define SCLK_UART MPLL_DEC / (UART1_RATIO+1) + +#define UART_UBRDIV_VAL 0x35 /* (SCLK_UART/(115200*16) -1) */ +#define UART_UDIVSLOT_VAL 0x4 /*((((SCLK_UART*10/(115200*16) -10))%10)*16/10)*/ + +#endif diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Exynos5250.h b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Exynos5250.h new file mode 100644 index 000000000..b0e473d9e --- /dev/null +++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Exynos5250.h @@ -0,0 +1,730 @@ +/* + * (C) Copyright 2012 Samsung Electronics Co. Ltd + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _EXYNOS5250_CPU_H +#define _EXYNOS5250_CPU_H + +/* EXYNOS5250 */ +#define EXYNOS5250_PRO_ID 0x10000000 +#define EXYNOS5250_SYSREG_BASE 0x10050000 +#define EXYNOS5250_POWER_BASE 0x10040000 +#define EXYNOS5250_CLOCK_BASE 0x10010000 +#define EXYNOS5250_SROM_BASE 0x12250000 +#define EXYNOS5250_HSMMC_BASE 0x12200000 +#define EXYNOS5250_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5250_INF_REG_BASE 0x10040800 +#define EXYNOS5250_TZPC_BASE 0x10100000 +#define EXYNOS5250_UART_BASE 0x12C00000 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + + +#define __REG(x) (*(unsigned int *)(x)) + +/* + * CHIP ID + */ +#define CHIP_ID_BASE EXYNOS5250_PRO_ID +#define PRO_ID_OFFSET 0x0 +#define PRO_ID __REG(CHIP_ID_BASE+PRO_ID_OFFSET) + +/* + * SYSREG + */ +#define USB_CFG_OFFSET 0x230 +#define USB_CFG_REG (EXYNOS5250_SYSREG_BASE + USB_CFG_OFFSET) + +/* + * POWER + */ +#define ELFIN_POWER_BASE EXYNOS5250_POWER_BASE +#define OMR_OFFSET 0x0 +#define SW_RST_REG_OFFSET 0x400 +#define SW_RST_REG __REG(EXYNOS5250_POWER_BASE + SW_RST_REG_OFFSET) + +#define INF_REG_BASE EXYNOS5250_INF_REG_BASE + +#define INF_REG0_OFFSET 0x00 +#define INF_REG1_OFFSET 0x04 +#define INF_REG2_OFFSET 0x08 +#define INF_REG3_OFFSET 0x0C +#define INF_REG4_OFFSET 0x10 +#define INF_REG5_OFFSET 0x14 +#define INF_REG6_OFFSET 0x18 +#define INF_REG7_OFFSET 0x1C + +#define INF_REG0_REG __REG(INF_REG_BASE+INF_REG0_OFFSET) +#define INF_REG1_REG __REG(INF_REG_BASE+INF_REG1_OFFSET) +#define INF_REG2_REG __REG(INF_REG_BASE+INF_REG2_OFFSET) +#define INF_REG3_REG __REG(INF_REG_BASE+INF_REG3_OFFSET) +#define INF_REG4_REG __REG(INF_REG_BASE+INF_REG4_OFFSET) +#define INF_REG5_REG __REG(INF_REG_BASE+INF_REG5_OFFSET) +#define INF_REG6_REG __REG(INF_REG_BASE+INF_REG6_OFFSET) +#define INF_REG7_REG __REG(INF_REG_BASE+INF_REG7_OFFSET) + +#define USB_DEVICE_PHY_CONTROL_OFFSET 0x0704 +#define USB_DEVICE_PHY_CONTROL (EXYNOS5250_POWER_BASE+USB_DEVICE_PHY_CONTROL_OFFSET) + +/* Define Mode */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* + * CLOCK + */ +#define ELFIN_CLOCK_BASE EXYNOS5250_CLOCK_BASE + +#define APLL_LOCK_OFFSET 0x00000 +#define APLL_CON0_OFFSET 0x00100 +#define APLL_CON1_OFFSET 0x00104 +#define CLK_SRC_CPU_OFFSET 0x00200 +#define CLK_MUX_STAT_CPU_OFFSET 0x00400 +#define CLK_DIV_CPU0_OFFSET 0x00500 +#define CLK_DIV_CPU1_OFFSET 0x00504 +#define CLK_DIV_STAT_CPU0_OFFSET 0x00600 +#define CLK_DIV_STAT_CPU1_OFFSET 0x00604 +#define CLK_GATE_SCLK_CPU_OFFSET 0x00800 +#define CLKOUT_CMU_CPU_OFFSET 0x00A00 +#define CLKOUT_CMU_CPU_DIV_STAT_OFFSET 0x00A04 +#define ARMCLK_STOPCTRL_OFFSET 0x01000 +#define ATCLK_STOPCTRL_OFFSET 0x01004 +#define PARITYFAIL_STATUS_OFFSET 0x01010 +#define PARITYFAIL_CLEAR_OFFSET 0x01014 +#define PWR_CTRL_OFFSET 0x01020 +#define PWR_CTRL2_OFFSET 0x01024 +#define APLL_CON0_L8_OFFSET 0x01100 +#define APLL_CON0_L7_OFFSET 0x01104 +#define APLL_CON0_L6_OFFSET 0x01108 +#define APLL_CON0_L5_OFFSET 0x0110C +#define APLL_CON0_L4_OFFSET 0x01110 +#define APLL_CON0_L3_OFFSET 0x01114 +#define APLL_CON0_L2_OFFSET 0x01118 +#define APLL_CON0_L1_OFFSET 0x0111C +#define IEM_CONTROL_OFFSET 0x01120 +#define APLL_CON1_L8_OFFSET 0x01200 +#define APLL_CON1_L7_OFFSET 0x01204 +#define APLL_CON1_L6_OFFSET 0x01208 +#define APLL_CON1_L5_OFFSET 0x0120C +#define APLL_CON1_L4_OFFSET 0x01210 +#define APLL_CON1_L3_OFFSET 0x01214 +#define APLL_CON1_L2_OFFSET 0x01218 +#define APLL_CON1_L1_OFFSET 0x0121C +#define CLKDIV_IEM_L8_OFFSET 0x01300 +#define CLKDIV_IEM_L7_OFFSET 0x01304 +#define CLKDIV_IEM_L6_OFFSET 0x01308 +#define CLKDIV_IEM_L5_OFFSET 0x0130C +#define CLKDIV_IEM_L4_OFFSET 0x01310 +#define CLKDIV_IEM_L3_OFFSET 0x01314 +#define CLKDIV_IEM_L2_OFFSET 0x01318 +#define CLKDIV_IEM_L1_OFFSET 0x0131C +#define MPLL_LOCK_OFFSET 0x04000 +#define MPLL_CON0_OFFSET 0x04100 +#define MPLL_CON1_OFFSET 0x04104 +#define CLK_SRC_CORE0_OFFSET 0x04200 +#define CLK_SRC_CORE1_OFFSET 0x04204 +#define CLK_SRC_MASK_CORE0_OFFSET 0x04300 +#define CLK_MUX_STAT_CORE1_OFFSET 0x04404 +#define CLK_DIV_CORE0_OFFSET 0x04500 +#define CLK_DIV_CORE1_OFFSET 0x04504 +#define CLK_DIV_STAT_CORE0_OFFSET 0x04600 +#define CLK_DIV_STAT_CORE1_OFFSET 0x04604 +#define CLK_GATE_IP_CORE_OFFSET 0x04900 +#define CLKOUT_CMU_CORE_OFFSET 0x04A00 +#define CLKOUT_CMU_CORE_DIV_STAT_OFFSET 0x04A04 +#define DCGIDX_MAP0_OFFSET 0x05000 +#define DCGIDX_MAP1_OFFSET 0x05004 +#define DCGIDX_MAP2_OFFSET 0x05008 +#define DCGPERF_MAP0_OFFSET 0x05020 +#define DCGPERF_MAP1_OFFSET 0x05024 +#define DVCIDX_MAP_OFFSET 0x05040 +#define FREQ_CPU_OFFSET 0x05060 +#define FREQ_DPM_OFFSET 0x05064 +#define DVSEMCLK_EN_OFFSET 0x05080 +#define MAXPERF_OFFSET 0x05084 +#define CLK_DIV_ACP_OFFSET 0x08500 +#define CLK_DIV_STAT_ACP_OFFSET 0x08600 +#define CLK_GATE_IP_ACP_OFFSET 0x08800 +#define CLKOUT_CMU_ACP_OFFSET 0x08A00 +#define CLKOUT_CMU_ACP_DIV_STAT_OFFSET 0x08A04 +#define CLK_DIV_ISP0_OFFSET 0x0C300 +#define CLK_DIV_ISP1_OFFSET 0x0C304 +#define CLK_DIV_ISP2_OFFSET 0x0C308 +#define CLK_DIV_STAT_ISP0_OFFSET 0x0C400 +#define CLK_DIV_STAT_ISP1_OFFSET 0x0C404 +#define CLK_DIV_STAT_ISP2_OFFSET 0x0C408 +#define CLK_GATE_IP_ISP0_OFFSET 0x0C800 +#define CLK_GATE_IP_ISP1_OFFSET 0x0C804 +#define CLK_GATE_SCLK_ISP_OFFSET 0x0C900 +#define MCUISP_PWR_CTRL_OFFSET 0x0C910 +#define CLKOUT_CMU_ISP_OFFSET 0x0CA00 +#define CLKOUT_CMU_ISP_DIV_STAT_OFFSET 0x0CA04 +#define CPLL_LOCK_OFFSET 0x10020 +#define EPLL_LOCK_OFFSET 0x10030 +#define VPLL_LOCK_OFFSET 0x10040 +#define CPLL_CON0_OFFSET 0x10120 +#define CPLL_CON1_OFFSET 0x10124 +#define EPLL_CON0_OFFSET 0x10130 +#define EPLL_CON1_OFFSET 0x10134 +#define EPLL_CON2_OFFSET 0x10138 +#define VPLL_CON0_OFFSET 0x10140 +#define VPLL_CON1_OFFSET 0x10144 +#define VPLL_CON2_OFFSET 0x10148 +#define CLK_SRC_TOP0_OFFSET 0x10210 +#define CLK_SRC_TOP1_OFFSET 0x10214 +#define CLK_SRC_TOP2_OFFSET 0x10218 +#define CLK_SRC_TOP3_OFFSET 0x1021C +#define CLK_SRC_GSCL_OFFSET 0x10220 +#define CLK_SRC_DISP1_0_OFFSET 0x1022C +#define CLK_SRC_DISP1_1_OFFSET 0x10230 +#define CLK_SRC_MAU_OFFSET 0x10240 +#define CLK_SRC_FSYS_OFFSET 0x10244 +#define CLK_SRC_PERIC0_OFFSET 0x10250 +#define CLK_SRC_PERIC1_OFFSET 0x10254 +#define SCLK_SRC_ISP_OFFSET 0x10270 +#define CLK_SRC_MASK_TOP_OFFSET 0x10310 +#define CLK_SRC_MASK_GSCL_OFFSET 0x10320 +#define CLK_SRC_MASK_DISP1_0_OFFSET 0x1032C +#define CLK_SRC_MASK_DISP1_1_OFFSET 0x10330 +#define CLK_SRC_MASK_MAU_OFFSET 0x10334 +#define CLK_SRC_MASK_FSYS_OFFSET 0x10340 +#define CLK_SRC_MASK_PERIC0_OFFSET 0x10350 +#define CLK_SRC_MASK_PERIC1_OFFSET 0x10354 +#define SCLK_SRC_MASK_ISP_OFFSET 0x10370 +#define CLK_MUX_STAT_TOP0_OFFSET 0x10410 +#define CLK_MUX_STAT_TOP1_OFFSET 0x10414 +#define CLK_MUX_STAT_TOP2_OFFSET 0x10418 +#define CLK_MUX_STAT_TOP3_OFFSET 0x1041C +#define CLK_DIV_TOP0_OFFSET 0x10510 +#define CLK_DIV_TOP1_OFFSET 0x10514 +#define CLK_DIV_GSCL_OFFSET 0x10520 +#define CLK_DIV_DISP1_0_OFFSET 0x1052C +#define CLK_DIV_DISP1_1_OFFSET 0x10530 +#define CLK_DIV_GEN_OFFSET 0x1053C +#define CLK_DIV_MAU_OFFSET 0x10544 +#define CLK_DIV_FSYS0_OFFSET 0x10548 +#define CLK_DIV_FSYS1_OFFSET 0x1054C +#define CLK_DIV_FSYS2_OFFSET 0x10550 +#define CLK_DIV_FSYS3_OFFSET 0x10554 +#define CLK_DIV_PERIC0_OFFSET 0x10558 +#define CLK_DIV_PERIC1_OFFSET 0x1055C +#define CLK_DIV_PERIC2_OFFSET 0x10560 +#define CLK_DIV_PERIC3_OFFSET 0x10564 +#define CLK_DIV_PERIC4_OFFSET 0x10568 +#define CLK_DIV_PERIC5_OFFSET 0x1056C +#define SCLK_DIV_ISP_OFFSET 0x10580 +#define CLKDIV2_RATIO0_OFFSET 0x10590 +#define CLKDIV2_RATIO1_OFFSET 0x10594 +#define CLKDIV4_RATIO_OFFSET 0x105A0 +#define CLK_DIV_STAT_TOP0_OFFSET 0x10610 +#define CLK_DIV_STAT_TOP1_OFFSET 0x10614 +#define CLK_DIV_STAT_GSCL_OFFSET 0x10620 +#define CLK_DIV_STAT_DISP1_0_OFFSET 0x1062C +#define CLK_DIV_STAT_DISP1_1_OFFSET 0x10630 +#define CLK_DIV_STAT_GEN_OFFSET 0x1063C +#define CLK_DIV_STAT_MAUDIO_OFFSET 0x10644 +#define CLK_DIV_STAT_FSYS0_OFFSET 0x10648 +#define CLK_DIV_STAT_FSYS1_OFFSET 0x1064C +#define CLK_DIV_STAT_FSYS2_OFFSET 0x10650 +#define CLK_DIV_STAT_FSYS3_OFFSET 0x10654 +#define CLK_DIV_STAT_PERIC0_OFFSET 0x10658 +#define CLK_DIV_STAT_PERIC1_OFFSET 0x1065C +#define CLK_DIV_STAT_PERIC2_OFFSET 0x10660 +#define CLK_DIV_STAT_PERIC3_OFFSET 0x10664 +#define CLK_DIV_STAT_PERIC4_OFFSET 0x10668 +#define CLK_DIV_STAT_PERIC5_OFFSET 0x1066C +#define SCLK_DIV_STAT_ISP_OFFSET 0x10680 +#define CLKDIV2_STAT0_OFFSET 0x10690 +#define CLKDIV2_STAT1_OFFSET 0x10694 +#define CLKDIV4_STAT_OFFSET 0x106A0 +#define CLK_GATE_TOP_SCLK_DISP1_OFFSET 0x10828 +#define CLK_GATE_TOP_SCLK_GEN_OFFSET 0x1082C +#define CLK_GATE_TOP_SCLK_MAU_OFFSET 0x1083C +#define CLK_GATE_TOP_SCLK_FSYS_OFFSET 0x10840 +#define CLK_GATE_TOP_SCLK_PERIC_OFFSET 0x10850 +#define CLK_GATE_TOP_SCLK_ISP_OFFSET 0x10870 +#define CLK_GATE_IP_GSCL_OFFSET 0x10920 +#define CLK_GATE_IP_DISP1_OFFSET 0x10928 +#define CLK_GATE_IP_MFC_OFFSET 0x1092C +#define CLK_GATE_IP_G3D_OFFSET 0x10930 +#define CLK_GATE_IP_GEN_OFFSET 0x10934 +#define CLK_GATE_IP_FSYS_OFFSET 0x10944 +#define CLK_GATE_IP_GPS_OFFSET 0x1094C +#define CLK_GATE_IP_PERIC_OFFSET 0x10950 +#define CLK_GATE_IP_PERIS_OFFSET 0x10960 +#define CLK_GATE_BLOCK_OFFSET 0x10980 +#define CLKOUT_CMU_TOP_OFFSET 0x10A00 +#define CLKOUT_CMU_TOP_DIV_STAT_OFFSET 0x10A04 +#define CLK_SRC_LEX_OFFSET 0x14200 +#define CLK_DIV_LEX_OFFSET 0x14500 +#define CLK_DIV_STAT_LEX_OFFSET 0x14600 +#define CLK_GATE_IP_LEX_OFFSET 0x14800 +#define CLKOUT_CMU_LEX_OFFSET 0x14A00 +#define CLKOUT_CMU_LEX_DIV_STAT_OFFSET 0x14A04 +#define CLK_DIV_R0X_OFFSET 0x18500 +#define CLK_DIV_STAT_R0X_OFFSET 0x18600 +#define CLK_GATE_IP_R0X_OFFSET 0x18800 +#define CLKOUT_CMU_R0X_OFFSET 0x18A00 +#define CLKOUT_CMU_R0X_DIV_STAT_OFFSET 0x18A04 +#define CLK_DIV_R1X_OFFSET 0x1C500 +#define CLK_DIV_STAT_R1X_OFFSET 0x1C600 +#define CLK_GATE_IP_R1X_OFFSET 0x1C800 +#define CLKOUT_CMU_R1X_OFFSET 0x1CA00 +#define CLKOUT_CMU_R1X_DIV_STAT_OFFSET 0x1CA04 +#define BPLL_LOCK_OFFSET 0x20010 +#define BPLL_CON0_OFFSET 0x20110 +#define BPLL_CON1_OFFSET 0x20114 +#define CLK_SRC_CDREX_OFFSET 0x20200 +#define CLK_MUX_STAT_CDREX_OFFSET 0x20400 +#define CLK_DIV_CDREX_OFFSET 0x20500 +#define CLK_DIV_CDREX2_OFFSET 0x20504 +#define CLK_DIV_STAT_CDREX_OFFSET 0x20600 +#define CLK_GATE_IP_CDREX_OFFSET 0x20900 +#define C2C_MONITOR_OFFSET 0x20910 +#define DMC_PWR_CTRL 0x20914 +#define DREX2_PAUSE_OFFSET 0x2091C +#define CLKOUT_CMU_CDREX_OFFSET 0x20A00 +#define CLKOUT_CMU_CDREX_DIV_STAT_OFFSET 0x20A04 +#define LPDDR3PHY_CTRL 0x20A10 + +#define CLK_SRC_FSYS __REG(ELFIN_CLOCK_BASE+CLK_SRC_FSYS_OFFSET) +#define CLK_DIV_FSYS1 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS1_OFFSET) +#define CLK_DIV_FSYS2 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS2_OFFSET) +#define CLK_DIV_FSYS3 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS3_OFFSET) +#define APLL_CON0_REG __REG(ELFIN_CLOCK_BASE+APLL_CON0_OFFSET) +#define MPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+MPLL_CON0_OFFSET) +#define EPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+EPLL_CON0_OFFSET) +#define VPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+VPLL_CON0_OFFSET) + +#define FIMD1_SCLKMPLL (0x06) +#define FIMD1_CLK_DIV (0x00) + +#define CLK_GATE_FIMD1_MASK (0x01 << 0x00) +#define CLK_SRC_FIMD1_MASK (0x0F << 0x00) +#define CLK_DIV_FIMD1_MASK (0x0F << 0x00) + +#define CLK_SRC_FIMD1_SEL(x) ((x) << 0x00) +#define CLK_DIV_FIMD1_SEL(x) ((x) << 0x00) +#define CLK_SRC_DISP1_0_UNMASK (0x01 << 0x00) + +#define CLK_GATE_DSIM1_MASK (0x01 << 0x03) + +/* + * TZPC + */ +#define TZPC0_OFFSET 0x00000 +#define TZPC1_OFFSET 0x10000 +#define TZPC2_OFFSET 0x20000 +#define TZPC3_OFFSET 0x30000 +#define TZPC4_OFFSET 0x40000 +#define TZPC5_OFFSET 0x50000 +#define TZPC6_OFFSET 0x60000 +#define TZPC7_OFFSET 0x70000 +#define TZPC8_OFFSET 0x80000 +#define TZPC9_OFFSET 0x90000 + +#define ELFIN_TZPC0_BASE (EXYNOS5250_TZPC_BASE + TZPC0_OFFSET) +#define ELFIN_TZPC1_BASE (EXYNOS5250_TZPC_BASE + TZPC1_OFFSET) +#define ELFIN_TZPC2_BASE (EXYNOS5250_TZPC_BASE + TZPC2_OFFSET) +#define ELFIN_TZPC3_BASE (EXYNOS5250_TZPC_BASE + TZPC3_OFFSET) +#define ELFIN_TZPC4_BASE (EXYNOS5250_TZPC_BASE + TZPC4_OFFSET) +#define ELFIN_TZPC5_BASE (EXYNOS5250_TZPC_BASE + TZPC5_OFFSET) +#define ELFIN_TZPC6_BASE (EXYNOS5250_TZPC_BASE + TZPC6_OFFSET) +#define ELFIN_TZPC7_BASE (EXYNOS5250_TZPC_BASE + TZPC7_OFFSET) +#define ELFIN_TZPC8_BASE (EXYNOS5250_TZPC_BASE + TZPC8_OFFSET) +#define ELFIN_TZPC9_BASE (EXYNOS5250_TZPC_BASE + TZPC9_OFFSET) + +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* + * Memory controller + */ +#define ELFIN_SROM_BASE EXYNOS5250_SROM_BASE + +#define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0) +#define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4) +#define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8) +#define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC) +#define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10) + +/* + * SDRAM Controller + */ + +/* DMC control register */ +#define DMC_CTRL_BASE 0x10DD0000 + +#define DMC_CONCONTROL 0x00 +#define DMC_MEMCONTROL 0x04 +#define DMC_MEMCONFIG0 0x08 +#define DMC_MEMCONFIG1 0x0C +#define DMC_DIRECTCMD 0x10 +#define DMC_PRECHCONFIG 0x14 +#define DMC_PHYCONTROL0 0x18 +#define DMC_PWRDNCONFIG 0x28 +#define DMC_TIMINGPZQ 0x2C +#define DMC_TIMINGAREF 0x30 +#define DMC_TIMINGROW 0x34 +#define DMC_TIMINGDATA 0x38 +#define DMC_TIMINGPOWER 0x3C +#define DMC_PHYSTATUS 0x40 +#define DMC_CHIPSTATUS_CH0 0x48 +#define DMC_CHIPSTATUS_CH1 0x4C +#define DMC_MRSTATUS 0x54 +#define DMC_QOSCONTROL0 0x60 +#define DMC_QOSCONTROL1 0x68 +#define DMC_QOSCONTROL2 0x70 +#define DMC_QOSCONTROL3 0x78 +#define DMC_QOSCONTROL4 0x80 +#define DMC_QOSCONTROL5 0x88 +#define DMC_QOSCONTROL6 0x90 +#define DMC_QOSCONTROL7 0x98 +#define DMC_QOSCONTROL8 0xA0 +#define DMC_QOSCONTROL9 0xA8 +#define DMC_QOSCONTROL10 0xB0 +#define DMC_QOSCONTROL11 0xB8 +#define DMC_QOSCONTROL12 0xC0 +#define DMC_QOSCONTROL13 0xC8 +#define DMC_QOSCONTROL14 0xD0 +#define DMC_QOSCONTROL15 0xD8 +#define DMC_IVCONTROL 0xF0 +#define DMC_WRTRA_CONFIG 0x00F4 +#define DMC_RDLVL_CONFIG 0x00F8 +#define DMC_BRBRSVCONTROL 0x0100 +#define DMC_BRBRSVCONFIG 0x0104 +#define DMC_BRBQOSCONFIG 0x0108 +#define DMC_MEMBASECONFIG0 0x010C +#define DMC_MEMBASECONFIG1 0x0110 +#define DMC_WRLVL_CONFIG 0x0120 +#define DMC_PMNC_PPC 0xE000 +#define DMC_CNTENS_PPC 0xE010 +#define DMC_CNTENC_PPC 0xE020 +#define DMC_INTENS_PPC 0xE030 +#define DMC_INTENC_PPC 0xE040 +#define DMC_FLAG_PPC 0xE050 +#define DMC_CCNT_PPC 0xE100 +#define DMC_PMCNT0_PPC 0xE110 +#define DMC_PMCNT1_PPC 0xE120 +#define DMC_PMCNT2_PPC 0xE130 +#define DMC_PMCNT3_PPC 0xE140 + +/* PHY Control Register */ +#define PHY0_CTRL_BASE 0x10C00000 +#define PHY1_CTRL_BASE 0x10C10000 + +#define DMC_PHY_CON0 0x00 +#define DMC_PHY_CON1 0x04 +#define DMC_PHY_CON2 0x08 +#define DMC_PHY_CON3 0x0C +#define DMC_PHY_CON4 0x10 +#define DMC_PHY_CON6 0x18 +#define DMC_PHY_CON8 0x20 +#define DMC_PHY_CON10 0x28 +#define DMC_PHY_CON11 0x2C +#define DMC_PHY_CON12 0x30 +#define DMC_PHY_CON13 0x34 +#define DMC_PHY_CON14 0x38 +#define DMC_PHY_CON15 0x3C +#define DMC_PHY_CON16 0x40 +#define DMC_PHY_CON17 0x48 +#define DMC_PHY_CON18 0x4C +#define DMC_PHY_CON19 0x50 +#define DMC_PHY_CON20 0x54 +#define DMC_PHY_CON21 0x58 +#define DMC_PHY_CON22 0x5C +#define DMC_PHY_CON23 0x60 +#define DMC_PHY_CON24 0x64 +#define DMC_PHY_CON25 0x68 +#define DMC_PHY_CON26 0x6C +#define DMC_PHY_CON27 0x70 +#define DMC_PHY_CON28 0x74 +#define DMC_PHY_CON29 0x78 +#define DMC_PHY_CON30 0x7C +#define DMC_PHY_CON31 0x80 +#define DMC_PHY_CON32 0x84 +#define DMC_PHY_CON33 0x88 +#define DMC_PHY_CON34 0x8C +#define DMC_PHY_CON35 0x90 +#define DMC_PHY_CON36 0x94 +#define DMC_PHY_CON37 0x98 +#define DMC_PHY_CON38 0x9C +#define DMC_PHY_CON39 0xA0 +#define DMC_PHY_CON40 0xA4 +#define DMC_PHY_CON41 0xA8 +#define DMC_PHY_CON42 0xAC +/* + * UART + */ + +#define UART0_OFFSET 0x00000 +#define UART1_OFFSET 0x10000 +#define UART2_OFFSET 0x20000 +#define UART3_OFFSET 0x30000 +#define UART4_OFFSET 0x40000 + +#if defined(CONFIG_SERIAL0) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART0_OFFSET) +#elif defined(CONFIG_SERIAL1) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART1_OFFSET) +#elif defined(CONFIG_SERIAL2) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART2_OFFSET) +#elif defined(CONFIG_SERIAL3) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART3_OFFSET) +#elif defined(CONFIG_SERIAL4) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART4_OFFSET) +#else +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART0_OFFSET) +#endif + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 +//#define UTRSTAT_TX_EMPTY BIT2 +//#define UTRSTAT_RX_READY BIT0 +#define UART_ERR_MASK 0xF + +/* + * HS MMC + */ +#define HSMMC_0_OFFSET 0x00000 +#define HSMMC_1_OFFSET 0x10000 +#define HSMMC_2_OFFSET 0x20000 +#define HSMMC_3_OFFSET 0x30000 +#define HSMMC_4_OFFSET 0x40000 + +#define ELFIN_HSMMC_0_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_0_OFFSET) +#define ELFIN_HSMMC_1_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_1_OFFSET) +#define ELFIN_HSMMC_2_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_2_OFFSET) +#define ELFIN_HSMMC_3_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_3_OFFSET) +#define ELFIN_HSMMC_4_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_4_OFFSET) + +#define HM_SYSAD (0x00) +#define HM_BLKSIZE (0x04) +#define HM_BLKCNT (0x06) +#define HM_ARGUMENT (0x08) +#define HM_TRNMOD (0x0c) +#define HM_CMDREG (0x0e) +#define HM_RSPREG0 (0x10) +#define HM_RSPREG1 (0x14) +#define HM_RSPREG2 (0x18) +#define HM_RSPREG3 (0x1c) +#define HM_BDATA (0x20) +#define HM_PRNSTS (0x24) +#define HM_HOSTCTL (0x28) +#define HM_PWRCON (0x29) +#define HM_BLKGAP (0x2a) +#define HM_WAKCON (0x2b) +#define HM_CLKCON (0x2c) +#define HM_TIMEOUTCON (0x2e) +#define HM_SWRST (0x2f) +#define HM_NORINTSTS (0x30) +#define HM_ERRINTSTS (0x32) +#define HM_NORINTSTSEN (0x34) +#define HM_ERRINTSTSEN (0x36) +#define HM_NORINTSIGEN (0x38) +#define HM_ERRINTSIGEN (0x3a) +#define HM_ACMD12ERRSTS (0x3c) +#define HM_CAPAREG (0x40) +#define HM_MAXCURR (0x48) +#define HM_CONTROL2 (0x80) +#define HM_CONTROL3 (0x84) +#define HM_CONTROL4 (0x8c) +#define HM_HCVER (0xfe) + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define PWMTIMER_BASE EXYNOS5250_PWMTIMER_BASE + +/* + * USBD3 SFR + */ +#define USBDEVICE3_LINK_BASE 0x12000000 +#define USBDEVICE3_PHYCTRL_BASE 0x12100000 + +//========================== +// Global Registers (Gxxxx) +//========================== +// Global Common Registers +#define rGSBUSCFG0 (USBDEVICE3_LINK_BASE + 0xc100) +#define rGSBUSCFG1 (USBDEVICE3_LINK_BASE + 0xc104) +#define rGTXTHRCFG (USBDEVICE3_LINK_BASE + 0xc108) +#define rGRXTHRCFG (USBDEVICE3_LINK_BASE + 0xc10c) +#define rGCTL (USBDEVICE3_LINK_BASE + 0xc110) +#define rGEVTEN (USBDEVICE3_LINK_BASE + 0xc114) +#define rGSTS (USBDEVICE3_LINK_BASE + 0xc118) +#define rGSNPSID (USBDEVICE3_LINK_BASE + 0xc120) +#define rGGPIO (USBDEVICE3_LINK_BASE + 0xc124) +#define rGUID (USBDEVICE3_LINK_BASE + 0xc128) +#define rGUCTL (USBDEVICE3_LINK_BASE + 0xc12c) +#define rGBUSERRADDR_LO (USBDEVICE3_LINK_BASE + 0xc130) +#define rGBUSERRADDR_HI (USBDEVICE3_LINK_BASE + 0xc134) + +// Global Port to USB Instance Mapping Registers +#define rGPRTBIMAP_LO (USBDEVICE3_LINK_BASE + 0xc138) +#define rGPRTBIMAP_HI (USBDEVICE3_LINK_BASE + 0xc13c) +#define rGPRTBIMAP_HS_LO (USBDEVICE3_LINK_BASE + 0xc180) +#define rGPRTBIMAP_HS_HI (USBDEVICE3_LINK_BASE + 0xc184) +#define rGPRTBIMAP_FS_LO (USBDEVICE3_LINK_BASE + 0xc188) +#define rGPRTBIMAP_FS_HI (USBDEVICE3_LINK_BASE + 0xc18c) + +// Global Hardware Parameter Registers +#define rGHWPARAMS0 (USBDEVICE3_LINK_BASE + 0xc140) // 0x20204000 @c510 +#define rGHWPARAMS1 (USBDEVICE3_LINK_BASE + 0xc144) // 0x0060c93b @c510 +#define rGHWPARAMS2 (USBDEVICE3_LINK_BASE + 0xc148) // 0x12345678 @c510 +#define rGHWPARAMS3 (USBDEVICE3_LINK_BASE + 0xc14c) // 0x10420085 @c510 +#define rGHWPARAMS4 (USBDEVICE3_LINK_BASE + 0xc150) // 0x48820004 @c510 +#define rGHWPARAMS5 (USBDEVICE3_LINK_BASE + 0xc154) // 0x04204108 @c510 +#define rGHWPARAMS6 (USBDEVICE3_LINK_BASE + 0xc158) // 0x04008020 @c510 +#define rGHWPARAMS7 (USBDEVICE3_LINK_BASE + 0xc15c) // 0x018516fe @c510 +#define rGHWPARAMS8 (USBDEVICE3_LINK_BASE + 0xc600) // 0x00000386 @c510 + +// Global Debug Registers +#define rGDBGFIFOSPACE (USBDEVICE3_LINK_BASE + 0xc160) +#define rGDBGLTSSM (USBDEVICE3_LINK_BASE + 0xc164) +#define rGDBGLSPMUX (USBDEVICE3_LINK_BASE + 0xc170) +#define rGDBGLSP (USBDEVICE3_LINK_BASE + 0xc174) +#define rGDBGEPINFO0 (USBDEVICE3_LINK_BASE + 0xc178) +#define rGDBGEPINFO1 (USBDEVICE3_LINK_BASE + 0xc17c) + +// Global PHY Registers +#define rGUSB2PHYCFG (USBDEVICE3_LINK_BASE + 0xc200) +#define rGUSB2I2CCTL (USBDEVICE3_LINK_BASE + 0xc240) +#define rGUSB2PHYACC (USBDEVICE3_LINK_BASE + 0xc280) +#define rGUSB3PIPECTL (USBDEVICE3_LINK_BASE + 0xc2c0) + +// Global FIFO Size Registers (0 <= num <= 15 @510) +#define rGTXFIFOSIZ(num) ((USBDEVICE3_LINK_BASE + 0xc300) + 0x04*num) +#define rGRXFIFOSIZ0 (USBDEVICE3_LINK_BASE + 0xc380) + +// Global Event Buffer Registers (DWC_USB3_DEVICE_NUM_INT = 1 @C510, GHWPARAMS1[20:15]) +#define rGEVNTADR_LO0 (USBDEVICE3_LINK_BASE + 0xc400) +#define rGEVNTADR_HI0 (USBDEVICE3_LINK_BASE + 0xc404) +#define rGEVNTSIZ0 (USBDEVICE3_LINK_BASE + 0xc408) +#define rGEVNTCOUNT0 (USBDEVICE3_LINK_BASE + 0xc40c) + +//========================== +// Device Registers (Dxxxx) +//========================== +// Device Common Registers +#define rDCFG (USBDEVICE3_LINK_BASE + 0xc700) +#define rDCTL (USBDEVICE3_LINK_BASE + 0xc704) +#define rDEVTEN (USBDEVICE3_LINK_BASE + 0xc708) +#define rDSTS (USBDEVICE3_LINK_BASE + 0xc70c) +#define rDGCMDPAR (USBDEVICE3_LINK_BASE + 0xc710) +#define rDGCMD (USBDEVICE3_LINK_BASE + 0xc714) +#define rDALEPENA (USBDEVICE3_LINK_BASE + 0xc720) + +// Device Endpoint Registers (0 <= ep <= 15) +#define rDOEPCMDPAR2(ep) ((USBDEVICE3_LINK_BASE + 0xc800) + 0x20*ep) +#define rDOEPCMDPAR1(ep) ((USBDEVICE3_LINK_BASE + 0xc804) + 0x20*ep) +#define rDOEPCMDPAR0(ep) ((USBDEVICE3_LINK_BASE + 0xc808) + 0x20*ep) +#define rDOEPCMD(ep) ((USBDEVICE3_LINK_BASE + 0xc80c) + 0x20*ep) + +#define rDIEPCMDPAR2(ep) ((USBDEVICE3_LINK_BASE + 0xc810) + 0x20*ep) +#define rDIEPCMDPAR1(ep) ((USBDEVICE3_LINK_BASE + 0xc814) + 0x20*ep) +#define rDIEPCMDPAR0(ep) ((USBDEVICE3_LINK_BASE + 0xc818) + 0x20*ep) +#define rDIEPCMD(ep) ((USBDEVICE3_LINK_BASE + 0xc81c) + 0x20*ep) + +//========================== +// USB DEVICE PHY CONTROL REGISTERS +//========================== +#define EXYNOS_PHY_LINKSYSTEM (USBDEVICE3_PHYCTRL_BASE + 0x04) +#define EXYNOS_PHY_UTMI (USBDEVICE3_PHYCTRL_BASE + 0x08) +#define EXYNOS_PHY_PIPE (USBDEVICE3_PHYCTRL_BASE + 0x0C) +#define EXYNOS_PHY_CLKPWR (USBDEVICE3_PHYCTRL_BASE + 0x10) +#define EXYNOS_PHY_REG0 (USBDEVICE3_PHYCTRL_BASE + 0x14) +#define EXYNOS_PHY_REG1 (USBDEVICE3_PHYCTRL_BASE + 0x18) +#define EXYNOS_PHY_PARAM0 (USBDEVICE3_PHYCTRL_BASE + 0x1C) +#define EXYNOS_PHY_PARAM1 (USBDEVICE3_PHYCTRL_BASE + 0x20) +#define EXYNOS_PHY_TERM (USBDEVICE3_PHYCTRL_BASE + 0x24) +#define EXYNOS_PHY_TEST (USBDEVICE3_PHYCTRL_BASE + 0x28) +#define EXYNOS_PHY_ADP (USBDEVICE3_PHYCTRL_BASE + 0x2C) +#define EXYNOS_PHY_BATCHG (USBDEVICE3_PHYCTRL_BASE + 0x30) +#define EXYNOS_PHY_RESUME (USBDEVICE3_PHYCTRL_BASE + 0x34) + +#endif /* _EXYNOS5250_CPU_H */ diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Exynos5250_Evt1.h b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Exynos5250_Evt1.h new file mode 100755 index 000000000..e229a1377 --- /dev/null +++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform/Exynos5250_Evt1.h @@ -0,0 +1,763 @@ +/* + * (C) Copyright 2012 Samsung Electronics Co. Ltd + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _EXYNOS5250_CPU_H +#define _EXYNOS5250_CPU_H + +/* EXYNOS5250 */ +#define EXYNOS5250_PRO_ID 0x10000000 +#define EXYNOS5250_SYSREG_BASE 0x10050000 +#define EXYNOS5250_POWER_BASE 0x10040000 +#define EXYNOS5250_CLOCK_BASE 0x10010000 +#define EXYNOS5250_SROM_BASE 0x12250000 +#define EXYNOS5250_HSMMC_BASE 0x12200000 +#define EXYNOS5250_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5250_INF_REG_BASE 0x10040800 +#define EXYNOS5250_TZPC_BASE 0x10100000 +#define EXYNOS5250_UART_BASE 0x12C00000 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + + +#define __REG(x) (*(unsigned int *)(x)) + +/* + * CHIP ID + */ +#define CHIP_ID_BASE EXYNOS5250_PRO_ID +#define PRO_ID_OFFSET 0x0 +#define PRO_ID __REG(CHIP_ID_BASE+PRO_ID_OFFSET) +#define PRO_MAINREV ((PRO_ID >> 0x4) & 0x0f) +#define PRO_SUBREV (PRO_ID & 0x0f) +#define PRO_PKGINFO ((PRO_ID >> 0x8) & 0x0f) +#define SCP_TYPE 0x0 +#define POP_TYPE 0x2 + +/* + * SYSREG + */ +#define USB_CFG_OFFSET 0x230 +#define USB_CFG_REG (EXYNOS5250_SYSREG_BASE + USB_CFG_OFFSET) + +/* + * POWER + */ +#define ELFIN_POWER_BASE EXYNOS5250_POWER_BASE +#define OMR_OFFSET 0x0 +#define SW_RST_REG_OFFSET 0x400 +#define SW_RST_REG __REG(EXYNOS5250_POWER_BASE + SW_RST_REG_OFFSET) + +#define FSYS_ARM_CONFIGURATION_OFFSET 0x2200 +#define EFNAND_PHY_CONTROL_OFFSET 0x070C +#define SATA_PHY_CONTROL_OFFSET 0x0724 + +#define INF_REG_BASE EXYNOS5250_INF_REG_BASE + +#define INF_REG0_OFFSET 0x00 +#define INF_REG1_OFFSET 0x04 +#define INF_REG2_OFFSET 0x08 +#define INF_REG3_OFFSET 0x0C +#define INF_REG4_OFFSET 0x10 +#define INF_REG5_OFFSET 0x14 +#define INF_REG6_OFFSET 0x18 +#define INF_REG7_OFFSET 0x1C + +#define INF_REG0_REG __REG(INF_REG_BASE+INF_REG0_OFFSET) +#define INF_REG1_REG __REG(INF_REG_BASE+INF_REG1_OFFSET) +#define INF_REG2_REG __REG(INF_REG_BASE+INF_REG2_OFFSET) +#define INF_REG3_REG __REG(INF_REG_BASE+INF_REG3_OFFSET) +#define INF_REG4_REG __REG(INF_REG_BASE+INF_REG4_OFFSET) +#define INF_REG5_REG __REG(INF_REG_BASE+INF_REG5_OFFSET) +#define INF_REG6_REG __REG(INF_REG_BASE+INF_REG6_OFFSET) +#define INF_REG7_REG __REG(INF_REG_BASE+INF_REG7_OFFSET) + +#define USB_DEVICE_PHY_CONTROL_OFFSET 0x0704 +#define USB_PHY_CONTROL_OFFSET 0x0708 +#define USB_DEVICE_PHY_CONTROL (EXYNOS5250_POWER_BASE+USB_DEVICE_PHY_CONTROL_OFFSET) +#define USB_PHY_CONTROL (EXYNOS5250_POWER_BASE+USB_PHY_CONTROL_OFFSET) + +/* Define Mode */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* + * CLOCK + */ +#define ELFIN_CLOCK_BASE EXYNOS5250_CLOCK_BASE + +#define APLL_LOCK_OFFSET 0x00000 +#define APLL_CON0_OFFSET 0x00100 +#define APLL_CON1_OFFSET 0x00104 +#define CLK_SRC_CPU_OFFSET 0x00200 +#define CLK_MUX_STAT_CPU_OFFSET 0x00400 +#define CLK_DIV_CPU0_OFFSET 0x00500 +#define CLK_DIV_CPU1_OFFSET 0x00504 +#define CLK_DIV_STAT_CPU0_OFFSET 0x00600 +#define CLK_DIV_STAT_CPU1_OFFSET 0x00604 +#define CLK_GATE_SCLK_CPU_OFFSET 0x00800 +#define CLKOUT_CMU_CPU_OFFSET 0x00A00 +#define CLKOUT_CMU_CPU_DIV_STAT_OFFSET 0x00A04 +#define ARMCLK_STOPCTRL_OFFSET 0x01000 +#define PARITYFAIL_STATUS_OFFSET 0x01010 +#define PARITYFAIL_CLEAR_OFFSET 0x01014 +#define PWR_CTRL_OFFSET 0x01020 +#define PWR_CTRL2_OFFSET 0x01024 +#define APLL_CON0_L8_OFFSET 0x01100 +#define APLL_CON0_L7_OFFSET 0x01104 +#define APLL_CON0_L6_OFFSET 0x01108 +#define APLL_CON0_L5_OFFSET 0x0110C +#define APLL_CON0_L4_OFFSET 0x01110 +#define APLL_CON0_L3_OFFSET 0x01114 +#define APLL_CON0_L2_OFFSET 0x01118 +#define APLL_CON0_L1_OFFSET 0x0111C +#define IEM_CONTROL_OFFSET 0x01120 +#define APLL_CON1_L8_OFFSET 0x01200 +#define APLL_CON1_L7_OFFSET 0x01204 +#define APLL_CON1_L6_OFFSET 0x01208 +#define APLL_CON1_L5_OFFSET 0x0120C +#define APLL_CON1_L4_OFFSET 0x01210 +#define APLL_CON1_L3_OFFSET 0x01214 +#define APLL_CON1_L2_OFFSET 0x01218 +#define APLL_CON1_L1_OFFSET 0x0121C +#define CLKDIV_IEM_L8_OFFSET 0x01300 +#define CLKDIV_IEM_L7_OFFSET 0x01304 +#define CLKDIV_IEM_L6_OFFSET 0x01308 +#define CLKDIV_IEM_L5_OFFSET 0x0130C +#define CLKDIV_IEM_L4_OFFSET 0x01310 +#define CLKDIV_IEM_L3_OFFSET 0x01314 +#define CLKDIV_IEM_L2_OFFSET 0x01318 +#define CLKDIV_IEM_L1_OFFSET 0x0131C +#define MPLL_LOCK_OFFSET 0x04000 +#define MPLL_CON0_OFFSET 0x04100 +#define MPLL_CON1_OFFSET 0x04104 +#define CLK_SRC_CORE0_OFFSET 0x04200 +#define CLK_SRC_CORE1_OFFSET 0x04204 +#define CLK_SRC_MASK_CORE0_OFFSET 0x04300 +#define CLK_MUX_STAT_CORE1_OFFSET 0x04404 +#define CLK_DIV_CORE0_OFFSET 0x04500 +#define CLK_DIV_CORE1_OFFSET 0x04504 +#define CLK_DIV_SYSRGT_OFFSET 0x04508 +#define CLK_DIV_STAT_CORE0_OFFSET 0x04600 +#define CLK_DIV_STAT_CORE1_OFFSET 0x04604 +#define CLK_DIV_STAT_SYSRGT_OFFSET 0x04608 +#define CLK_GATE_IP_CORE_OFFSET 0x04900 +#define CLK_GATE_IP_SYSRGT_OFFSET 0x04904 +#define C2C_MONITOR_OFFSET 0x04910 +#define CLKOUT_CMU_CORE_OFFSET 0x04A00 +#define CLKOUT_CMU_CORE_DIV_STAT_OFFSET 0x04A04 +#define DCGIDX_MAP0_OFFSET 0x05000 +#define DCGIDX_MAP1_OFFSET 0x05004 +#define DCGIDX_MAP2_OFFSET 0x05008 +#define DCGPERF_MAP0_OFFSET 0x05020 +#define DCGPERF_MAP1_OFFSET 0x05024 +#define DVCIDX_MAP_OFFSET 0x05040 +#define FREQ_CPU_OFFSET 0x05060 +#define FREQ_DPM_OFFSET 0x05064 +#define DVSEMCLK_EN_OFFSET 0x05080 +#define MAXPERF_OFFSET 0x05084 +#define C2C_CONFIG_OFFSET 0x06000 +#define CLK_DIV_ACP_OFFSET 0x08500 +#define CLK_DIV_STAT_ACP_OFFSET 0x08600 +#define CLK_GATE_IP_ACP_OFFSET 0x08800 +#define CLK_DIV_SYSLFT_OFFSET 0x08900 +#define CLK_DIV_STAT_SYSLFT_OFFSET 0x08910 +#define CLK_GATE_IP_SYSLFT_OFFSET 0x08930 +#define CLKOUT_CMU_ACP_OFFSET 0x08A00 +#define CLKOUT_CMU_ACP_DIV_STAT_OFFSET 0x08A04 +#define UFMC_CONFIG_OFFSET 0x08A10 +#define CLK_DIV_ISP0_OFFSET 0x0C300 +#define CLK_DIV_ISP1_OFFSET 0x0C304 +#define CLK_DIV_ISP2_OFFSET 0x0C308 +#define CLK_DIV_STAT_ISP0_OFFSET 0x0C400 +#define CLK_DIV_STAT_ISP1_OFFSET 0x0C404 +#define CLK_DIV_STAT_ISP2_OFFSET 0x0C408 +#define CLK_GATE_IP_ISP0_OFFSET 0x0C800 +#define CLK_GATE_IP_ISP1_OFFSET 0x0C804 +#define CLK_GATE_SCLK_ISP_OFFSET 0x0C900 +#define MCUISP_PWR_CTRL_OFFSET 0x0C910 +#define CLKOUT_CMU_ISP_OFFSET 0x0CA00 +#define CLKOUT_CMU_ISP_DIV_STAT_OFFSET 0x0CA04 +#define CPLL_LOCK_OFFSET 0x10020 +#define EPLL_LOCK_OFFSET 0x10030 +#define VPLL_LOCK_OFFSET 0x10040 +#define GPLL_LOCK_OFFSET 0x10050 +#define CPLL_CON0_OFFSET 0x10120 +#define CPLL_CON1_OFFSET 0x10124 +#define EPLL_CON0_OFFSET 0x10130 +#define EPLL_CON1_OFFSET 0x10134 +#define EPLL_CON2_OFFSET 0x10138 +#define VPLL_CON0_OFFSET 0x10140 +#define VPLL_CON1_OFFSET 0x10144 +#define VPLL_CON2_OFFSET 0x10148 +#define GPLL_CON0_OFFSET 0x10150 +#define GPLL_CON1_OFFSET 0x10154 +#define CLK_SRC_TOP0_OFFSET 0x10210 +#define CLK_SRC_TOP1_OFFSET 0x10214 +#define CLK_SRC_TOP2_OFFSET 0x10218 +#define CLK_SRC_TOP3_OFFSET 0x1021C +#define CLK_SRC_GSCL_OFFSET 0x10220 +#define CLK_SRC_DISP1_0_OFFSET 0x1022C +#define CLK_SRC_MAU_OFFSET 0x10240 +#define CLK_SRC_FSYS_OFFSET 0x10244 +#define CLK_SRC_GEN_OFFSET 0x10248 +#define CLK_SRC_PERIC0_OFFSET 0x10250 +#define CLK_SRC_PERIC1_OFFSET 0x10254 +#define SCLK_SRC_ISP_OFFSET 0x10270 +#define CLK_SRC_MASK_TOP_OFFSET 0x10310 +#define CLK_SRC_MASK_GSCL_OFFSET 0x10320 +#define CLK_SRC_MASK_DISP1_0_OFFSET 0x1032C +#define CLK_SRC_MASK_DISP1_1_OFFSET 0x10330 +#define CLK_SRC_MASK_MAU_OFFSET 0x10334 +#define CLK_SRC_MASK_FSYS_OFFSET 0x10340 +#define CLK_SRC_MASK_GEN_OFFSET 0x10344 +#define CLK_SRC_MASK_PERIC0_OFFSET 0x10350 +#define CLK_SRC_MASK_PERIC1_OFFSET 0x10354 +#define SCLK_SRC_MASK_ISP_OFFSET 0x10370 +#define CLK_MUX_STAT_TOP0_OFFSET 0x10410 +#define CLK_MUX_STAT_TOP1_OFFSET 0x10414 +#define CLK_MUX_STAT_TOP2_OFFSET 0x10418 +#define CLK_MUX_STAT_TOP3_OFFSET 0x1041C +#define CLK_DIV_TOP0_OFFSET 0x10510 +#define CLK_DIV_TOP1_OFFSET 0x10514 +#define CLK_DIV_GSCL_OFFSET 0x10520 +#define CLK_DIV_DISP1_0_OFFSET 0x1052C +#define CLK_DIV_GEN_OFFSET 0x1053C +#define CLK_DIV_MAU_OFFSET 0x10544 +#define CLK_DIV_FSYS0_OFFSET 0x10548 +#define CLK_DIV_FSYS1_OFFSET 0x1054C +#define CLK_DIV_FSYS2_OFFSET 0x10550 +#define CLK_DIV_PERIC0_OFFSET 0x10558 +#define CLK_DIV_PERIC1_OFFSET 0x1055C +#define CLK_DIV_PERIC2_OFFSET 0x10560 +#define CLK_DIV_PERIC3_OFFSET 0x10564 +#define CLK_DIV_PERIC4_OFFSET 0x10568 +#define CLK_DIV_PERIC5_OFFSET 0x1056C +#define SCLK_DIV_ISP_OFFSET 0x10580 +#define CLKDIV2_RATIO0_OFFSET 0x10590 +#define CLKDIV2_RATIO1_OFFSET 0x10594 +#define CLKDIV4_RATIO_OFFSET 0x105A0 +#define CLK_DIV_STAT_TOP0_OFFSET 0x10610 +#define CLK_DIV_STAT_TOP1_OFFSET 0x10614 +#define CLK_DIV_STAT_GSCL_OFFSET 0x10620 +#define CLK_DIV_STAT_DISP1_0_OFFSET 0x1062C +#define CLK_DIV_STAT_GEN_OFFSET 0x1063C +#define CLK_DIV_STAT_MAU_OFFSET 0x10644 +#define CLK_DIV_STAT_FSYS0_OFFSET 0x10648 +#define CLK_DIV_STAT_FSYS1_OFFSET 0x1064C +#define CLK_DIV_STAT_FSYS2_OFFSET 0x10650 +#define CLK_DIV_STAT_PERIC0_OFFSET 0x10658 +#define CLK_DIV_STAT_PERIC1_OFFSET 0x1065C +#define CLK_DIV_STAT_PERIC2_OFFSET 0x10660 +#define CLK_DIV_STAT_PERIC3_OFFSET 0x10664 +#define CLK_DIV_STAT_PERIC4_OFFSET 0x10668 +#define CLK_DIV_STAT_PERIC5_OFFSET 0x1066C +#define SCLK_DIV_STAT_ISP_OFFSET 0x10680 +#define CLKDIV2_STAT0_OFFSET 0x10690 +#define CLKDIV2_STAT1_OFFSET 0x10694 +#define CLKDIV4_STAT_OFFSET 0x106A0 +#define CLK_GATE_TOP_SCLK_DISP1_OFFSET 0x10828 +#define CLK_GATE_TOP_SCLK_GEN_OFFSET 0x1082C +#define CLK_GATE_TOP_SCLK_MAU_OFFSET 0x1083C +#define CLK_GATE_TOP_SCLK_FSYS_OFFSET 0x10840 +#define CLK_GATE_TOP_SCLK_PERIC_OFFSET 0x10850 +#define CLK_GATE_TOP_SCLK_ISP_OFFSET 0x10870 +#define CLK_GATE_IP_GSCL_OFFSET 0x10920 +#define CLK_GATE_IP_DISP1_OFFSET 0x10928 +#define CLK_GATE_IP_MFC_OFFSET 0x1092C +#define CLK_GATE_IP_G3D_OFFSET 0x10930 +#define CLK_GATE_IP_GEN_OFFSET 0x10934 +#define CLK_GATE_IP_FSYS_OFFSET 0x10944 +#define CLK_GATE_IP_PERIC_OFFSET 0x10950 +#define CLK_GATE_IP_PERIS_OFFSET 0x10960 +#define CLK_GATE_BLOCK_OFFSET 0x10980 +#define MCUIOP_PWR_CTRL_OFFSET 0x109A0 +#define CLKOUT_CMU_TOP_OFFSET 0x10A00 +#define CLKOUT_CMU_TOP_DIV_STAT_OFFSET 0x10A04 +#define CLK_SRC_LEX_OFFSET 0x14200 +#define CLK_MUX_STAT_LEX_OFFSET 0x14400 +#define CLK_DIV_LEX_OFFSET 0x14500 +#define CLK_DIV_STAT_LEX_OFFSET 0x14600 +#define CLK_GATE_IP_LEX_OFFSET 0x14800 +#define CLKOUT_CMU_LEX_OFFSET 0x14A00 +#define CLKOUT_CMU_LEX_DIV_STAT_OFFSET 0x14A04 +#define CLK_DIV_R0X_OFFSET 0x18500 +#define CLK_DIV_STAT_R0X_OFFSET 0x18600 +#define CLK_GATE_IP_R0X_OFFSET 0x18800 +#define CLKOUT_CMU_R0X_OFFSET 0x18A00 +#define CLKOUT_CMU_R0X_DIV_STAT_OFFSET 0x18A04 +#define CLK_DIV_R1X_OFFSET 0x1C500 +#define CLK_DIV_STAT_R1X_OFFSET 0x1C600 +#define CLK_GATE_IP_R1X_OFFSET 0x1C800 +#define CLKOUT_CMU_R1X_OFFSET 0x1CA00 +#define CLKOUT_CMU_R1X_DIV_STAT_OFFSET 0x1CA04 +#define BPLL_LOCK_OFFSET 0x20010 +#define BPLL_CON0_OFFSET 0x20110 +#define BPLL_CON1_OFFSET 0x20114 +#define CLK_SRC_CDREX_OFFSET 0x20200 +#define CLK_MUX_STAT_CDREX_OFFSET 0x20400 +#define CLK_DIV_CDREX_OFFSET 0x20500 +#define CLK_DIV_STAT_CDREX_OFFSET 0x20600 +#define CLK_GATE_IP_CDREX_OFFSET 0x20900 +#define DMC_FREQ_CTRL_OFFSET 0x20914 +#define DREX2_PAUSE_OFFSET 0x2091C +#define CLKOUT_CMU_CDREX_OFFSET 0x20A00 +#define CLKOUT_CMU_CDREX_DIV_STAT_OFFSET 0x20A04 +#define LPDDR3PHY_CTRL 0x20A10 +#define LPDDR3PHY_CTRL_CON0 0x20A14 +#define LPDDR3PHY_CTRL_CON1 0x20A18 +#define LPDDR3PHY_CTRL_CON2 0x20A1C +#define LPDDR3PHY_CTRL_CON3 0x20A20 +#define PLL_DIV2_SEL_OFFSET 0x20A24 + +#define CLK_SRC_FSYS __REG(ELFIN_CLOCK_BASE+CLK_SRC_FSYS_OFFSET) +#define CLK_DIV_FSYS0 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS0_OFFSET) +#define CLK_DIV_FSYS1 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS1_OFFSET) +#define CLK_DIV_FSYS2 __REG(ELFIN_CLOCK_BASE+CLK_DIV_FSYS2_OFFSET) +#define APLL_CON0_REG __REG(ELFIN_CLOCK_BASE+APLL_CON0_OFFSET) +#define MPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+MPLL_CON0_OFFSET) +#define EPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+EPLL_CON0_OFFSET) +#define VPLL_CON0_REG __REG(ELFIN_CLOCK_BASE+VPLL_CON0_OFFSET) + +/* + * TZPC + */ +#define TZPC0_OFFSET 0x00000 +#define TZPC1_OFFSET 0x10000 +#define TZPC2_OFFSET 0x20000 +#define TZPC3_OFFSET 0x30000 +#define TZPC4_OFFSET 0x40000 +#define TZPC5_OFFSET 0x50000 +#define TZPC6_OFFSET 0x60000 +#define TZPC7_OFFSET 0x70000 +#define TZPC8_OFFSET 0x80000 +#define TZPC9_OFFSET 0x90000 + +#define ELFIN_TZPC0_BASE (EXYNOS5250_TZPC_BASE + TZPC0_OFFSET) +#define ELFIN_TZPC1_BASE (EXYNOS5250_TZPC_BASE + TZPC1_OFFSET) +#define ELFIN_TZPC2_BASE (EXYNOS5250_TZPC_BASE + TZPC2_OFFSET) +#define ELFIN_TZPC3_BASE (EXYNOS5250_TZPC_BASE + TZPC3_OFFSET) +#define ELFIN_TZPC4_BASE (EXYNOS5250_TZPC_BASE + TZPC4_OFFSET) +#define ELFIN_TZPC5_BASE (EXYNOS5250_TZPC_BASE + TZPC5_OFFSET) +#define ELFIN_TZPC6_BASE (EXYNOS5250_TZPC_BASE + TZPC6_OFFSET) +#define ELFIN_TZPC7_BASE (EXYNOS5250_TZPC_BASE + TZPC7_OFFSET) +#define ELFIN_TZPC8_BASE (EXYNOS5250_TZPC_BASE + TZPC8_OFFSET) +#define ELFIN_TZPC9_BASE (EXYNOS5250_TZPC_BASE + TZPC9_OFFSET) + +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* + * Memory controller + */ +#define ELFIN_SROM_BASE EXYNOS5250_SROM_BASE + +#define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0) +#define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4) +#define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8) +#define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC) +#define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10) + +/* + * SDRAM Controller + */ + +/* DMC control register */ +#define DMC_CTRL_BASE 0x10DD0000 + +#define DMC_CONCONTROL 0x00 +#define DMC_MEMCONTROL 0x04 +#define DMC_MEMCONFIG0 0x08 +#define DMC_MEMCONFIG1 0x0C +#define DMC_DIRECTCMD 0x10 +#define DMC_PRECHCONFIG 0x14 +#define DMC_PHYCONTROL0 0x18 +#define DMC_PWRDNCONFIG 0x28 +#define DMC_TIMINGPZQ 0x2C +#define DMC_TIMINGAREF 0x30 +#define DMC_TIMINGROW 0x34 +#define DMC_TIMINGDATA 0x38 +#define DMC_TIMINGPOWER 0x3C +#define DMC_PHYSTATUS 0x40 +#define DMC_CHIPSTATUS_CH0 0x48 +#define DMC_CHIPSTATUS_CH1 0x4C +#define DMC_MRSTATUS 0x54 +#define DMC_QOSCONTROL0 0x60 +#define DMC_QOSCONTROL1 0x68 +#define DMC_QOSCONTROL2 0x70 +#define DMC_QOSCONTROL3 0x78 +#define DMC_QOSCONTROL4 0x80 +#define DMC_QOSCONTROL5 0x88 +#define DMC_QOSCONTROL6 0x90 +#define DMC_QOSCONTROL7 0x98 +#define DMC_QOSCONTROL8 0xA0 +#define DMC_QOSCONTROL9 0xA8 +#define DMC_QOSCONTROL10 0xB0 +#define DMC_QOSCONTROL11 0xB8 +#define DMC_QOSCONTROL12 0xC0 +#define DMC_QOSCONTROL13 0xC8 +#define DMC_QOSCONTROL14 0xD0 +#define DMC_QOSCONTROL15 0xD8 +#define DMC_IVCONTROL 0xF0 +#define DMC_WRTRA_CONFIG 0xF4 +#define DMC_RDLVL_CONFIG 0xF8 +#define DMC_BRBRSVCONTROL 0x0100 +#define DMC_BRBRSVCONFIG 0x0104 +#define DMC_BRBQOSCONFIG 0x0108 +#define DMC_MEMBASECONFIG0 0x010C +#define DMC_MEMBASECONFIG1 0x0110 +#define DMC_WRLVLCONFIG0 0x0120 +#define DMC_WRLVLCONFIG1 0x0124 +#define DMC_WRLVLSTATUS 0x0128 +#define DMC_PEREVCONTROL 0x0130 +#define DMC_PEREV0CONFIG 0x0134 +#define DMC_PEREV1CONFIG 0x0138 +#define DMC_PEREV2CONFIG 0x013C +#define DMC_PEREV3CONFIG 0x0140 +#define DMC_CTRL_IO_RDATA_CH0 0x0150 +#define DMC_CTRL_IO_RDATA_CH1 0x0154 +#define DMC_CACAL_CONFIG0 0x0160 +#define DMC_CACAL_CONFIG1 0x0164 +#define DMC_CACAL_STATUS 0x0168 +#define DMC_PMNC_PPC 0xE000 +#define DMC_CNTENS_PPC 0xE010 +#define DMC_CNTENC_PPC 0xE020 +#define DMC_INTENS_PPC 0xE030 +#define DMC_INTENC_PPC 0xE040 +#define DMC_FLAG_PPC 0xE050 +#define DMC_CCNT_PPC 0xE100 +#define DMC_PMCNT0_PPC 0xE110 +#define DMC_PMCNT1_PPC 0xE120 +#define DMC_PMCNT2_PPC 0xE130 +#define DMC_PMCNT3_PPC 0xE140 + +/* PHY Control Register */ +#define PHY0_CTRL_BASE 0x10C00000 +#define PHY1_CTRL_BASE 0x10C10000 + +#define DMC_PHY_CON0 0x00 +#define DMC_PHY_CON1 0x04 +#define DMC_PHY_CON2 0x08 +#define DMC_PHY_CON3 0x0C +#define DMC_PHY_CON4 0x10 +#define DMC_PHY_CON6 0x18 +#define DMC_PHY_CON8 0x20 +#define DMC_PHY_CON10 0x28 +#define DMC_PHY_CON11 0x2C +#define DMC_PHY_CON12 0x30 +#define DMC_PHY_CON13 0x34 +#define DMC_PHY_CON14 0x38 +#define DMC_PHY_CON15 0x3C +#define DMC_PHY_CON16 0x40 +#define DMC_PHY_CON17 0x48 +#define DMC_PHY_CON18 0x4C +#define DMC_PHY_CON19 0x50 +#define DMC_PHY_CON20 0x54 +#define DMC_PHY_CON21 0x58 +#define DMC_PHY_CON22 0x5C +#define DMC_PHY_CON23 0x60 +#define DMC_PHY_CON24 0x64 +#define DMC_PHY_CON25 0x68 +#define DMC_PHY_CON26 0x6C +#define DMC_PHY_CON27 0x70 +#define DMC_PHY_CON28 0x74 +#define DMC_PHY_CON29 0x78 +#define DMC_PHY_CON30 0x7C +#define DMC_PHY_CON31 0x80 +#define DMC_PHY_CON32 0x84 +#define DMC_PHY_CON33 0x88 +#define DMC_PHY_CON34 0x8C +#define DMC_PHY_CON35 0x90 +#define DMC_PHY_CON36 0x94 +#define DMC_PHY_CON37 0x98 +#define DMC_PHY_CON38 0x9C +#define DMC_PHY_CON39 0xA0 +#define DMC_PHY_CON40 0xA4 +#define DMC_PHY_CON41 0xA8 +#define DMC_PHY_CON42 0xAC + + +/* + * FBM + */ +#define DDR_R1_FBM_BASE 0x10c30000 +#define DDR_R0_FBM_BASE 0x10dc0000 + +#define FBM_MODESEL0 0x0 +#define FBM_THRESHOLDSEL0 0x40 + +/* + * UART + */ + +#define UART0_OFFSET 0x00000 +#define UART1_OFFSET 0x10000 +#define UART2_OFFSET 0x20000 +#define UART3_OFFSET 0x30000 + +#if defined(CONFIG_SERIAL0) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART0_OFFSET) +#elif defined(CONFIG_SERIAL1) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART1_OFFSET) +#elif defined(CONFIG_SERIAL2) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART2_OFFSET) +#elif defined(CONFIG_SERIAL3) +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART3_OFFSET) +#else +#define UART_CONSOLE_BASE (EXYNOS5250_UART_BASE + UART0_OFFSET) +#endif + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 +//#define UTRSTAT_TX_EMPTY BIT2 +//#define UTRSTAT_RX_READY BIT0 +#define UART_ERR_MASK 0xF + +/* + * HS MMC + */ +#define HSMMC_0_OFFSET 0x00000 +#define HSMMC_1_OFFSET 0x10000 +#define HSMMC_2_OFFSET 0x20000 +#define HSMMC_3_OFFSET 0x30000 + +#define ELFIN_HSMMC_0_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_0_OFFSET) +#define ELFIN_HSMMC_1_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_1_OFFSET) +#define ELFIN_HSMMC_2_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_2_OFFSET) +#define ELFIN_HSMMC_3_BASE (EXYNOS5250_HSMMC_BASE + HSMMC_3_OFFSET) + +#define HM_SYSAD (0x00) +#define HM_BLKSIZE (0x04) +#define HM_BLKCNT (0x06) +#define HM_ARGUMENT (0x08) +#define HM_TRNMOD (0x0c) +#define HM_CMDREG (0x0e) +#define HM_RSPREG0 (0x10) +#define HM_RSPREG1 (0x14) +#define HM_RSPREG2 (0x18) +#define HM_RSPREG3 (0x1c) +#define HM_BDATA (0x20) +#define HM_PRNSTS (0x24) +#define HM_HOSTCTL (0x28) +#define HM_PWRCON (0x29) +#define HM_BLKGAP (0x2a) +#define HM_WAKCON (0x2b) +#define HM_CLKCON (0x2c) +#define HM_TIMEOUTCON (0x2e) +#define HM_SWRST (0x2f) +#define HM_NORINTSTS (0x30) +#define HM_ERRINTSTS (0x32) +#define HM_NORINTSTSEN (0x34) +#define HM_ERRINTSTSEN (0x36) +#define HM_NORINTSIGEN (0x38) +#define HM_ERRINTSIGEN (0x3a) +#define HM_ACMD12ERRSTS (0x3c) +#define HM_CAPAREG (0x40) +#define HM_MAXCURR (0x48) +#define HM_CONTROL2 (0x80) +#define HM_CONTROL3 (0x84) +#define HM_CONTROL4 (0x8c) +#define HM_HCVER (0xfe) + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define PWMTIMER_BASE EXYNOS5250_PWMTIMER_BASE + +/* + * USBD3 SFR + */ +#define USBDEVICE3_LINK_BASE 0x12000000 +#define USBDEVICE3_PHYCTRL_BASE 0x12100000 + +//========================== +// Global Registers (Gxxxx) +//========================== +// Global Common Registers +#define rGSBUSCFG0 (USBDEVICE3_LINK_BASE + 0xc100) +#define rGSBUSCFG1 (USBDEVICE3_LINK_BASE + 0xc104) +#define rGTXTHRCFG (USBDEVICE3_LINK_BASE + 0xc108) +#define rGRXTHRCFG (USBDEVICE3_LINK_BASE + 0xc10c) +#define rGCTL (USBDEVICE3_LINK_BASE + 0xc110) +#define rGEVTEN (USBDEVICE3_LINK_BASE + 0xc114) +#define rGSTS (USBDEVICE3_LINK_BASE + 0xc118) +#define rGSNPSID (USBDEVICE3_LINK_BASE + 0xc120) +#define rGGPIO (USBDEVICE3_LINK_BASE + 0xc124) +#define rGUID (USBDEVICE3_LINK_BASE + 0xc128) +#define rGUCTL (USBDEVICE3_LINK_BASE + 0xc12c) +#define rGBUSERRADDR_LO (USBDEVICE3_LINK_BASE + 0xc130) +#define rGBUSERRADDR_HI (USBDEVICE3_LINK_BASE + 0xc134) + +// Global Port to USB Instance Mapping Registers +#define rGPRTBIMAP_LO (USBDEVICE3_LINK_BASE + 0xc138) +#define rGPRTBIMAP_HI (USBDEVICE3_LINK_BASE + 0xc13c) +#define rGPRTBIMAP_HS_LO (USBDEVICE3_LINK_BASE + 0xc180) +#define rGPRTBIMAP_HS_HI (USBDEVICE3_LINK_BASE + 0xc184) +#define rGPRTBIMAP_FS_LO (USBDEVICE3_LINK_BASE + 0xc188) +#define rGPRTBIMAP_FS_HI (USBDEVICE3_LINK_BASE + 0xc18c) + +// Global Hardware Parameter Registers +#define rGHWPARAMS0 (USBDEVICE3_LINK_BASE + 0xc140) // 0x20204000 @c510 +#define rGHWPARAMS1 (USBDEVICE3_LINK_BASE + 0xc144) // 0x0060c93b @c510 +#define rGHWPARAMS2 (USBDEVICE3_LINK_BASE + 0xc148) // 0x12345678 @c510 +#define rGHWPARAMS3 (USBDEVICE3_LINK_BASE + 0xc14c) // 0x10420085 @c510 +#define rGHWPARAMS4 (USBDEVICE3_LINK_BASE + 0xc150) // 0x48820004 @c510 +#define rGHWPARAMS5 (USBDEVICE3_LINK_BASE + 0xc154) // 0x04204108 @c510 +#define rGHWPARAMS6 (USBDEVICE3_LINK_BASE + 0xc158) // 0x04008020 @c510 +#define rGHWPARAMS7 (USBDEVICE3_LINK_BASE + 0xc15c) // 0x018516fe @c510 +#define rGHWPARAMS8 (USBDEVICE3_LINK_BASE + 0xc600) // 0x00000386 @c510 + +// Global Debug Registers +#define rGDBGFIFOSPACE (USBDEVICE3_LINK_BASE + 0xc160) +#define rGDBGLTSSM (USBDEVICE3_LINK_BASE + 0xc164) +#define rGDBGLSPMUX (USBDEVICE3_LINK_BASE + 0xc170) +#define rGDBGLSP (USBDEVICE3_LINK_BASE + 0xc174) +#define rGDBGEPINFO0 (USBDEVICE3_LINK_BASE + 0xc178) +#define rGDBGEPINFO1 (USBDEVICE3_LINK_BASE + 0xc17c) + +// Global PHY Registers +#define rGUSB2PHYCFG (USBDEVICE3_LINK_BASE + 0xc200) +#define rGUSB2I2CCTL (USBDEVICE3_LINK_BASE + 0xc240) +#define rGUSB2PHYACC (USBDEVICE3_LINK_BASE + 0xc280) +#define rGUSB3PIPECTL (USBDEVICE3_LINK_BASE + 0xc2c0) + +// Global FIFO Size Registers (0 <= num <= 15 @510) +#define rGTXFIFOSIZ(num) ((USBDEVICE3_LINK_BASE + 0xc300) + 0x04*num) +#define rGRXFIFOSIZ0 (USBDEVICE3_LINK_BASE + 0xc380) + +// Global Event Buffer Registers (DWC_USB3_DEVICE_NUM_INT = 1 @C510, GHWPARAMS1[20:15]) +#define rGEVNTADR_LO0 (USBDEVICE3_LINK_BASE + 0xc400) +#define rGEVNTADR_HI0 (USBDEVICE3_LINK_BASE + 0xc404) +#define rGEVNTSIZ0 (USBDEVICE3_LINK_BASE + 0xc408) +#define rGEVNTCOUNT0 (USBDEVICE3_LINK_BASE + 0xc40c) + +//========================== +// Device Registers (Dxxxx) +//========================== +// Device Common Registers +#define rDCFG (USBDEVICE3_LINK_BASE + 0xc700) +#define rDCTL (USBDEVICE3_LINK_BASE + 0xc704) +#define rDEVTEN (USBDEVICE3_LINK_BASE + 0xc708) +#define rDSTS (USBDEVICE3_LINK_BASE + 0xc70c) +#define rDGCMDPAR (USBDEVICE3_LINK_BASE + 0xc710) +#define rDGCMD (USBDEVICE3_LINK_BASE + 0xc714) +#define rDALEPENA (USBDEVICE3_LINK_BASE + 0xc720) + +// Device Endpoint Registers (0 <= ep <= 15) +#define rDOEPCMDPAR2(ep) ((USBDEVICE3_LINK_BASE + 0xc800) + 0x20*ep) +#define rDOEPCMDPAR1(ep) ((USBDEVICE3_LINK_BASE + 0xc804) + 0x20*ep) +#define rDOEPCMDPAR0(ep) ((USBDEVICE3_LINK_BASE + 0xc808) + 0x20*ep) +#define rDOEPCMD(ep) ((USBDEVICE3_LINK_BASE + 0xc80c) + 0x20*ep) + +#define rDIEPCMDPAR2(ep) ((USBDEVICE3_LINK_BASE + 0xc810) + 0x20*ep) +#define rDIEPCMDPAR1(ep) ((USBDEVICE3_LINK_BASE + 0xc814) + 0x20*ep) +#define rDIEPCMDPAR0(ep) ((USBDEVICE3_LINK_BASE + 0xc818) + 0x20*ep) +#define rDIEPCMD(ep) ((USBDEVICE3_LINK_BASE + 0xc81c) + 0x20*ep) + +//========================== +// USB DEVICE PHY CONTROL REGISTERS +//========================== +#define EXYNOS_PHY_LINKSYSTEM (USBDEVICE3_PHYCTRL_BASE + 0x04) +#define EXYNOS_PHY_UTMI (USBDEVICE3_PHYCTRL_BASE + 0x08) +#define EXYNOS_PHY_PIPE (USBDEVICE3_PHYCTRL_BASE + 0x0C) +#define EXYNOS_PHY_CLKPWR (USBDEVICE3_PHYCTRL_BASE + 0x10) +#define EXYNOS_PHY_REG0 (USBDEVICE3_PHYCTRL_BASE + 0x14) +#define EXYNOS_PHY_REG1 (USBDEVICE3_PHYCTRL_BASE + 0x18) +#define EXYNOS_PHY_PARAM0 (USBDEVICE3_PHYCTRL_BASE + 0x1C) +#define EXYNOS_PHY_PARAM1 (USBDEVICE3_PHYCTRL_BASE + 0x20) +#define EXYNOS_PHY_TERM (USBDEVICE3_PHYCTRL_BASE + 0x24) +#define EXYNOS_PHY_TEST (USBDEVICE3_PHYCTRL_BASE + 0x28) +#define EXYNOS_PHY_ADP (USBDEVICE3_PHYCTRL_BASE + 0x2C) +#define EXYNOS_PHY_BATCHG (USBDEVICE3_PHYCTRL_BASE + 0x30) +#define EXYNOS_PHY_RESUME (USBDEVICE3_PHYCTRL_BASE + 0x34) +#define EXYNOS_PHY_LINK_PORT (USBDEVICE3_PHYCTRL_BASE + 0x44) + +/* USBD 2.0 SFR */ +#define USBOTG_LINK_BASE (0x12140000) +#define USBOTG_PHY_BASE (0x12130000) + +#endif /* _EXYNOS5250_CPU_H */ |