diff options
Diffstat (limited to 'Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h')
| -rw-r--r-- | Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h | 583 |
1 files changed, 307 insertions, 276 deletions
diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h b/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h index 8e6473cfa..449e99662 100644 --- a/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h +++ b/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h @@ -15,289 +15,320 @@ #ifndef __OMAP4430_PAD_CONFIGURATION_H__ #define __OMAP4430_PAD_CONFIGURATION_H__ -#define SYSTEM_CONTROL_MODULE_BASE 0x48002000 +#define OMAP4430_CONTROL_MODULE_CORE_BASE 0x4A100000 +#define OMAP4430_CONTROL_MODULE_WKUP_BASE 0x4A31E000 -//Pin definition -#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030) -#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032) -#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034) -#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036) -#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038) -#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A) -#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C) -#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E) -#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040) -#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042) -#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044) -#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046) -#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048) -#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A) -#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C) -#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E) -#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050) -#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052) -#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054) -#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056) -#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058) -#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A) -#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C) -#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E) -#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060) -#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062) -#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064) -#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066) -#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068) -#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A) -#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C) -#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E) -#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070) -#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072) -#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262) -#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264) -#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074) -#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076) -#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078) -#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A) -#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C) -#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E) -#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080) -#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082) -#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084) -#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086) -#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088) -#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A) -#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C) -#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E) -#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090) -#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092) -#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094) -#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096) -#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098) -#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A) -#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C) -#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E) -#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0) -#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2) -#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4) -#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6) -#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8) -#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA) -#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC) -#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE) -#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0) -#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2) -#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4) -#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6) -#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8) -#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA) -#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC) -#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE) -#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0) -#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2) -#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4) -#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6) -#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8) -#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA) -#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC) -#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE) -#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0) -#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2) -#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4) -#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6) -#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8) -#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA) -#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC) -#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE) -#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0) -#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2) -#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4) -#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6) -#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8) -#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA) -#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC) -#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE) -#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0) -#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2) -#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4) -#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6) -#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8) -#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA) -#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC) -#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE) -#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100) -#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102) -#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104) -#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106) -#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108) -#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A) -#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C) -#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E) -#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110) -#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112) -#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114) -#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116) -#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118) -#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A) -#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C) -#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E) -#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120) -#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122) -#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124) -#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126) -#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128) -#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A) -#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C) -#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E) -#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130) -#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132) -#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134) -#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136) -#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138) -#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A) -#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C) -#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E) -#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140) -#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142) -#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144) -#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146) -#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148) -#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A) -#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C) -#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E) -#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150) -#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152) -#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154) -#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156) -#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158) -#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A) -#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C) -#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E) -#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160) -#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162) -#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164) -#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166) -#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168) -#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A) -#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C) -#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E) -#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170) -#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172) -#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174) -#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176) -#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178) -#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A) -#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C) -#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E) -#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180) -#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182) -#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184) -#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186) -#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188) -#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A) -#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C) -#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E) -#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190) -#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192) -#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194) -#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196) -#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198) -#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A) -#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C) -#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E) -#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0) -#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2) -#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4) -#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6) -#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8) -#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA) -#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC) -#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE) -#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0) -#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2) -#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4) -#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6) -#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8) -#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA) -#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC) -#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE) -#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0) -#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2) -#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4) -#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6) -#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8) -#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA) -#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC) -#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE) -#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0) -#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2) -#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4) -#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6) -#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8) -#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA) -#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC) -#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE) -#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0) -#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2) -#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8) -#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA) -#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC) -#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE) -#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0) -#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2) -#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4) -#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6) -#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8) -#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA) -#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC) -#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE) -#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0) -#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2) -#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4) -#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6) -#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8) -#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA) -#define SYS_BOOT0 (SYSTEM_CONTROL_MODULE_BASE + 0xA0A) -#define SYS_BOOT1 (SYSTEM_CONTROL_MODULE_BASE + 0xA0C) -#define SYS_BOOT3 (SYSTEM_CONTROL_MODULE_BASE + 0xA10) -#define SYS_BOOT4 (SYSTEM_CONTROL_MODULE_BASE + 0xA12) -#define SYS_BOOT5 (SYSTEM_CONTROL_MODULE_BASE + 0xA14) -#define SYS_BOOT6 (SYSTEM_CONTROL_MODULE_BASE + 0xA16) +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A -//Mux modes -#define MUXMODE0 (0x0UL) -#define MUXMODE1 (0x1UL) -#define MUXMODE2 (0x2UL) -#define MUXMODE3 (0x3UL) -#define MUXMODE4 (0x4UL) -#define MUXMODE5 (0x5UL) -#define MUXMODE6 (0x6UL) -#define MUXMODE7 (0x7UL) +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif -//Pad configuration register. -#define PAD_CONFIG_MASK (0xFFFFUL) -#define MUXMODE_OFFSET 0 -#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET) -#define PULL_CONFIG_OFFSET 3 -#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET) -#define INPUTENABLE_OFFSET 8 -#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET) -#define OFFMODE_VALUE_OFFSET 9 -#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET) -#define WAKEUP_OFFSET 14 -#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET) +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) -#define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0) -#define PULL_UP_SELECTED (BIT1 | BIT0) -#define PULL_DISABLED (0x0UL << 0) +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 -#define OUTPUT (0x0UL) //Pin is configured in output only mode. -#define INPUT (0x1UL) //Pin is configured in bi-directional mode. +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C typedef struct { - UINTN Pin; - UINTN MuxMode; - UINTN PullConfig; - UINTN InputEnable; + UINT16 Off; + UINT16 Val; + } PAD_CONFIGURATION; #endif //__OMAP4430_PAD_CONFIGURATION_H__ |