diff options
Diffstat (limited to 'ArmPlatformPkg')
38 files changed, 4734 insertions, 99 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 3358225ae..d813f885e 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -132,6 +132,8 @@ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
+ gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L""|VOID*|0x0000002E + ## Timeout value for displaying progressing bar in before boot OS.
# According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc index 0cc443416..6addb739e 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 0b511920-978d-4b34-acc0-3d9f8e6f9d81
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15-A7
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -173,11 +177,13 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0xE000000,0xE800000)"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400 earlyprintk debug verbose"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x0E800000,0x0E803000)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca15-tc2.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait ro androidboot.console=ttyAMA0" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca15-tc2.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
# PL111 - CLCD
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.dsc new file mode 100644 index 000000000..37765e929 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.dsc @@ -0,0 +1,307 @@ +# +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ArmVExpressPkg-CTA15x2 + PLATFORM_GUID = eb2bd5ff-2379-4a06-9c12-db905cdee9ea + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15x2 +!endif + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf +!ifndef $(EDK2_ARMVE_STANDALONE) + DEFINE EDK2_ARMVE_STANDALONE=1 +!endif + +!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf + + # ARM PL310 L2 Cache Driver + L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf + # ARM PL354 SMC Driver + PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf + # ARM PL341 DMC Driver + PL341DmcLib|ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.inf + # ARM PL301 Axi Driver + PL301AxiLib|ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + #LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf + ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + + # ARM PL390 General Interrupt Driver in Secure and Non-secure + ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + +[BuildOptions] + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2 + + GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2 + + XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] +!ifdef $(EDK2_ARMVE_STANDALONE) + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE +!else + gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + +!ifdef $(EDK2_SKIP_PEICORE) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress" + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + + # + # NV Storage PCDs. Use base of 0x00000000 for NOR1 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # System Memory (1GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + # + # ARM PrimeCell + # + + ## SP804 Timer + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|34 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x1c110000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x1c110020 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x1c120020 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000 + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + ## PL111 Versatile Express Motherboard controller + #gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 + + ## PL180 MMC/SD card controller + gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048 + gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000 + + # + # ARM PL390 General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000 + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmTokenSpaceGuid.PcdArmMachineType|2272 + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca15-tc1.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait ro androidboot.console=ttyAMA0 mmci.fmax=12000000" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca15-tc1.dtb" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()" + + # + # ARM L2x0 PCDs + # + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000 + + # + # ARM Architectual Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|600000000 + + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + ArmPlatformPkg/Sec/Sec.inf { + <LibraryClasses> + # Use the implementation which set the Secure bits + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf + } + + # + # PEI Phase modules + # +!ifdef $(EDK2_SKIP_PEICORE) + ArmPlatformPkg/PrePi/PeiMPCore.inf { + <LibraryClasses> + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf + } +!else + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf + } + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + Nt32Pkg/BootModePei/BootModePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } +!endif + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # Filesystems + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # Multimedia Card Interface + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + ArmPlatformPkg/Bds/Bds.inf diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf new file mode 100644 index 000000000..a15a72160 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf @@ -0,0 +1,324 @@ +# +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.ArmVExpress_EFI] +!if $(EDK2_ARMVE_STANDALONE) == 1 +BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +!else +BaseAddress = 0xA0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM. +!endif +Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x280 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00080000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FV = FVMAIN_SEC + +0x00080000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN_SEC] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/Sec/Sec.inf + + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + +!if $(EDK2_ARMVE_STANDALONE) != 1 + # + # Semi-hosting filesystem (Required the Hardware Debugger to be connected) + # + INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Multimedia Card Interface + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # UEFI application + # + INF ShellBinPkg/UefiShell/UefiShell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +!if $(EDK2_SKIP_PEICORE) == 1 + INF ArmPlatformPkg/PrePi/PeiMPCore.inf +!else + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +!endif + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.dsc new file mode 100644 index 000000000..b4ce23451 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.dsc @@ -0,0 +1,301 @@ +# +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ArmVExpressPkg-CTA5s + PLATFORM_GUID = eb2bd5ff-2379-4a06-9c12-db905cdee9ea + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY = Build/ArmVExpress-CTA5s +!endif + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf +!ifndef $(EDK2_ARMVE_STANDALONE) + DEFINE EDK2_ARMVE_STANDALONE=1 +!endif + +!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf + + # ARM PL310 L2 Cache Driver + L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf + # ARM PL354 SMC Driver + PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf + # ARM PL341 DMC Driver + PL341DmcLib|ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.inf + # ARM PL301 Axi Driver + PL301AxiLib|ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + #LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf + ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + + # ARM PL390 General Interrupt Driver in Secure and Non-secure + ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + +[BuildOptions] + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A5 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s + + GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a5 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s + + XCODE:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a5 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] +!ifdef $(EDK2_ARMVE_STANDALONE) + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE +!else + gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + +!ifdef $(EDK2_SKIP_PEICORE) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress" + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + + # + # NV Storage PCDs. Use base of 0x0C000000 for NOR1 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # System Memory (1GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + # + # ARM PrimeCell + # + + ## SP804 Timer + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|34 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x1c110000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x1c110020 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x1c120020 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000 + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + ## PL111 Versatile Express Motherboard controller + #gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 + + ## PL180 MMC/SD card controller + gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048 + gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000 + + # + # ARM PL390 General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000100 + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmTokenSpaceGuid.PcdArmMachineType|2272 + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca5s.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait ro androidboot.console=ttyAMA0 mmci.fmax=12000000" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca5s.dtb" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()" + + # + # ARM L2x0 PCDs + # + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + ArmPlatformPkg/Sec/Sec.inf { + <LibraryClasses> + # Use the implementation which set the Secure bits + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf + } + + # + # PEI Phase modules + # +!ifdef $(EDK2_SKIP_PEICORE) + ArmPlatformPkg/PrePi/PeiMPCore.inf { + <LibraryClasses> + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf + } +!else + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf + } + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + Nt32Pkg/BootModePei/BootModePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } +!endif + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # Filesystems + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # Multimedia Card Interface + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + ArmPlatformPkg/Bds/Bds.inf diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf new file mode 100644 index 000000000..a15a72160 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf @@ -0,0 +1,324 @@ +# +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.ArmVExpress_EFI] +!if $(EDK2_ARMVE_STANDALONE) == 1 +BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +!else +BaseAddress = 0xA0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM. +!endif +Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x280 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00080000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FV = FVMAIN_SEC + +0x00080000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN_SEC] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/Sec/Sec.inf + + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + +!if $(EDK2_ARMVE_STANDALONE) != 1 + # + # Semi-hosting filesystem (Required the Hardware Debugger to be connected) + # + INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Multimedia Card Interface + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # UEFI application + # + INF ShellBinPkg/UefiShell/UefiShell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +!if $(EDK2_SKIP_PEICORE) == 1 + INF ArmPlatformPkg/PrePi/PeiMPCore.inf +!else + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +!endif + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc new file mode 100755 index 000000000..566411609 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc @@ -0,0 +1,264 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ArmVExpress-FVP-AArch64 + PLATFORM_GUID = 0de70077-9b3b-43bf-ba38-0ea37d77141b + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/ArmVExpress-FVP-AArch64 + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf + +!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf + ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf + +[BuildOptions] + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM + + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + + ## FVP platforms support hardware power control + # Disabled for now as we have a version mismatch. + gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP" + + # Up to 8 cores on Base models. This works fine if model happens to have less. + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + + # + # NV Storage PCDs. Use base of 0x0C000000 for NOR1 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # FVP models can have 2 clusters with 4 cpus each + # Stacks for MPCores in Secure World + # Trusted SRAM (DRAM on Foundation model) + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x04000000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800 + + # Stacks for MPCores in Normal World + # Non-Trusted SRAM + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 + + # System Memory (2GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + ## Trustzone enable (to make the transition from EL3 to NS EL2 in ArmPlatformPkg/Sec) + gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE + + # + # ARM PrimeCell + # + + ## SP805 Watchdog - Motherboard Watchdog at 24MHz + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000 + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|24000000 + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + ## PL111 Versatile Express Motherboard controller + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 + + ## PL180 MMC/SD card controller + gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048 + gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000 + + # + # ARM PL390 General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro disk image on virtio" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image" +# gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"xxx" +# gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/fvp-base-gicv2-psci.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 loglevel=9 root=/dev/vda2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/fdt.dtb" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()" + + # + # ARM Architectual Timer Frequency + # + # Set tick frequency value to 120Mhz + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|120000000 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + ArmPlatformPkg/Sec/Sec.inf { + <LibraryClasses> + # Use the implementation which set the Secure bits + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf + } + + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf + } + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + Nt32Pkg/BootModePei/BootModePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # Semi-hosting filesystem + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # Multimedia Card Interface + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + ArmPlatformPkg/Bds/Bds.inf diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf new file mode 100755 index 000000000..3bbb34d69 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf @@ -0,0 +1,323 @@ +# +# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.FVP_AARCH64_EFI_SEC] +BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in SecureROM. +Size = 0x04000000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the device (64MiB). +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x4000 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00080000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FV = FVMAIN_SEC + +[FD.FVP_AARCH64_EFI] +BaseAddress = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in Flash0. +Size = 0x04000000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the device (64MiB). +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x4000 + +0x00000000|0x00280000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN_SEC] +FvBaseAddress = 0x0 # Secure ROM +FvForceRebase = TRUE +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/Sec/Sec.inf + + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # Semi-hosting filesystem + # + INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Multimedia Card Interface + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellBinPkg/UefiShell/UefiShell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc index 2d12f4ba8..b531e2103 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 1665b5b1-529d-4ba1-bd51-c3c9b29a2274
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -142,11 +146,13 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/rtsm_ve-cortex_a15x1.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca15x1.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait ro androidboot.console=ttyAMA0 mmci.fmax=12000000" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca15x1.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc index efd80ab0a..015750089 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 3a91a0f8-3af4-409d-a71d-a199dc134357
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15_MPCore
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -144,11 +148,13 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/rtsm_ve-cortex_a15x4.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca15x4.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait ro androidboot.console=ttyAMA0 mmci.fmax=12000000" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca15x4.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc index b6355026a..9e357c37e 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = e46039e0-5bb3-11e0-a9d6-0002a5d5c51b
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A9x4
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -154,11 +158,13 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/rtsm_ve-cortex_a9x4.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca9x4.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait ro androidboot.console=ttyAMA0 mmci.fmax=12000000" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|3 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca9x4.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2/ArmPlatform.h new file mode 100644 index 000000000..19d551dab --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2/ArmPlatform.h @@ -0,0 +1,96 @@ +/** @file +* Header defining Versatile Express constants (Base addresses, sizes, flags) +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_VEXPRESS_H__ +#define __ARM_VEXPRESS_H__ + +#include <Base.h> +#include <VExpressMotherBoard.h> + +/*********************************************************************************** +// Platform Memory Map +************************************************************************************/ + +// Can be NOR0, NOR1, DRAM +#define ARM_VE_REMAP_BASE 0x00000000 +#define ARM_VE_REMAP_SZ SIZE_64MB + +// Motherboard Peripheral and On-chip peripheral +#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x1C000000 +#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB +#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 +#define ARM_VE_CHIP_PERIPH_BASE 0x2A000000 + +// SMC +#define ARM_VE_SMC_BASE 0x08000000 +#define ARM_VE_SMC_SZ 0x1C000000 + +// NOR Flash 1 +// There is typo in the reference manual for the Base address of NOR Flash 1 +#define ARM_VE_SMB_NOR0_BASE 0x08000000 +#define ARM_VE_SMB_NOR0_SZ SIZE_64MB +// NOR Flash 2 +#define ARM_VE_SMB_NOR1_BASE 0x0C000000 +#define ARM_VE_SMB_NOR1_SZ SIZE_64MB +// SRAM +#define ARM_VE_SMB_SRAM_BASE 0x2E000000 +#define ARM_VE_SMB_SRAM_SZ SIZE_64KB +// USB, Ethernet, VRAM +#define ARM_VE_SMB_PERIPH_BASE 0x18000000 +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE +#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB + +// DRAM +#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase) +#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize) + +// This can be any value since we only support motherboard PL111 +#define LCD_VRAM_CORE_TILE_BASE 0x84000000 + +// On-chip peripherals (Snoop Control Unit etc...) +#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000 +// Note: The TRM says not all the peripherals are implemented +#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB + + +// External AXI between daughterboards (Logic Tile) +#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled +#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */ + + +/*********************************************************************************** + Core Tile memory-mapped Peripherals +************************************************************************************/ + +// SP810 Controller +#undef SP810_CTRL_BASE +#define SP810_CTRL_BASE 0x1C020000 + +// PL111 Colour LCD Controller +#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE +#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 +// PL341 Dynamic Memory Controller Base +#define ARM_VE_DMC_BASE (0x2B0A0000) + +// PL354 Static Memory Controller Base +#define ARM_VE_SMC_CTRL_BASE (0x7FFD0000) + +// SCC Base +#define ARM_VE_SCC_BASE (0x7FFF0000) + +// VRAM offset for the PL111 Colour LCD Controller on the motherboard +#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) + +#endif diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s/ArmPlatform.h new file mode 100644 index 000000000..4efd10e78 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s/ArmPlatform.h @@ -0,0 +1,93 @@ +/** @file +* Header defining Versatile Express constants (Base addresses, sizes, flags) +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_VEXPRESS_H__ +#define __ARM_VEXPRESS_H__ + +#include <Base.h> +#include <VExpressMotherBoard.h> + +/*********************************************************************************** +// Platform Memory Map +************************************************************************************/ + +// Can be NOR0, NOR1, DRAM +#define ARM_VE_REMAP_BASE 0x00000000 +#define ARM_VE_REMAP_SZ SIZE_64MB + +// Motherboard Peripheral and On-chip peripheral +#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x1C000000 +#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB +#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 +#define ARM_VE_CHIP_PERIPH_BASE 0x2A000000 + +// SMC +#define ARM_VE_SMC_BASE 0x08000000 +#define ARM_VE_SMC_SZ 0x1C000000 + +// NOR Flash 1 +// There is typo in the reference manual for the Base address of NOR Flash 1 +#define ARM_VE_SMB_NOR0_BASE 0x08000000 +#define ARM_VE_SMB_NOR0_SZ SIZE_64MB +// NOR Flash 2 +#define ARM_VE_SMB_NOR1_BASE 0x0C000000 +#define ARM_VE_SMB_NOR1_SZ SIZE_64MB +// SRAM +#define ARM_VE_SMB_SRAM_BASE 0x2E000000 +#define ARM_VE_SMB_SRAM_SZ SIZE_64KB +// USB, Ethernet, VRAM +#define ARM_VE_SMB_PERIPH_BASE 0x18000000 +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE +#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB + +// DRAM +#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase) +#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize) + +// This can be any value since we only support motherboard PL111 +#define LCD_VRAM_CORE_TILE_BASE 0x84000000 + +// On-chip peripherals (Snoop Control Unit etc...) +#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000 +// Note: The TRM says not all the peripherals are implemented +#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB + + +// External AXI between daughterboards (Logic Tile) +#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled +#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */ + + +/*********************************************************************************** + Core Tile memory-mapped Peripherals +************************************************************************************/ + +// SP810 Controller +#undef SP810_CTRL_BASE +#define SP810_CTRL_BASE 0x1C020000 + +// PL111 Colour LCD Controller +#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE +#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 +// PL341 Dynamic Memory Controller Base +#define ARM_VE_DMC_BASE (0x2A150000) + +// PL354 Static Memory Controller Base +#define ARM_VE_SMC_CTRL_BASE (0x2A190000) + +// VRAM offset for the PL111 Colour LCD Controller on the motherboard +#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) + +#endif diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf new file mode 100644 index 000000000..ef209e18c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf @@ -0,0 +1,54 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CTA15x2ArmVExpressLib + FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + IoLib + ArmLib + PL341DmcLib + PL301AxiLib + L2X0CacheLib + SerialPortLib + +[Sources.common] + CTA15x2.c + CTA15x2Mem.c + CTA15x2Helper.asm | RVCT + CTA15x2Helper.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf new file mode 100644 index 000000000..b576c1496 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf @@ -0,0 +1,53 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CTA15x2ArmVExpressLib + FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformSysConfigLib + IoLib + L2X0CacheLib + PL301AxiLib + PL341DmcLib + PL35xSmcLib + SerialPortLib + +[Sources.common] + CTA15x2Sec.c + CTA15x2.c + CTA15x2Boot.asm | RVCT + CTA15x2Boot.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c new file mode 100644 index 000000000..b91a93b44 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c @@ -0,0 +1,162 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/SerialPortLib.h> + +#include <Drivers/PL341Dmc.h> +#include <Drivers/PL301Axi.h> +#include <Drivers/SP804Timer.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include <ArmPlatform.h> + +#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1); + +ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA15x2[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) { + return BOOT_WITH_FULL_CONFIGURATION; + } else { + return BOOT_ON_S2_RESUME; + } +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + // Configure periodic timer (TIMER0) for 1MHz operation + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); + // Configure 1MHz clock + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); + // configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Memory is initialised in CTA15x2Boot.S +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA15x2) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mVersatileExpressMpCoreInfoCTA15x2; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S new file mode 100644 index 000000000..d865d6701 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S @@ -0,0 +1,503 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Drivers/PL35xSmc.h> +#include <Drivers/PL341Dmc.h> +#include <ArmPlatform.h> +#include <AutoGen.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformSecBootAction) +GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory) +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ASM_PFX(ArmPlatformSecBootAction): + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformInitializeBootMemory): + bx lr + + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformSecBootMemoryInit): + mov r8, lr + bl smc_init + bl dmc_init + bx r8 + + +/** + Initialise the Static Memory Controller +**/ +smc_init: + + // + // Disable loop buffer for A15 + // + MRC p15, 0, r2, c0, c0, 0 + MOV r1, r2, lsr #4 + LDR r0, =0xFFF + AND r1, r1, r0 + LDR r0, =0xC0F // See if A15 + CMP r1, r0 + BNE smc_init2 // Go if not + + MRC p15, 0, r1, c1, c0, 1 // Read Aux Ctrl Reg + ORR r1, r1, #(1 << 1) // Set Bit 1 + MCR p15, 0, r1, c1, c0, 1 // and write it back + +smc_init2: + + LDR r0, = ARM_VE_SMC_CTRL_BASE + LDR r2, = ARM_VE_SMB_PERIPH_BASE + + // CS0 - NOR0 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS1 - PSRAM + LDR r1, = 0x00027158 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000802 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS2 - usb, ethernet and vram + LDR r1, = 0x000CD2AA + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS3 - IOFPGA peripherals + LDR r1, = 0x00025156 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS4 - NOR1 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS5 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS6 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS7 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // Set refresh period + LDR r1, = 0x1 + STR r1, [r0, #0x20] + + LDR r1, = 0x1 + STR r1, [r0, #0x24] + + // page mode setup for VRAM + LDR r0, = 0x00FFFFFC + ADD r0, r0, r2 + + // read current state + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + // enable page mode + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, = 0x00900090 + STR r1, [r0, #0] + + // confirm page mode enabled + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + BX lr + // end of smc_init + + +/** + Initialise the PL341 Dynamic Memory Controller (DMC) + + On A15, the PHY needs to be locked before configuring the DMC. + After DMC config, the PHY needs to be trained +**/ +#define SCC_PHY_RESET_REG_OFFSET 0x04 + +dmc_init: + + LDR r0, = ARM_VE_DMC_BASE + LDR r1, = 0x00000400 // SCC reset bit for DDR PHY + LDR r2, = 0x7FEF0000 // PHY addr + + LDR r3, =0x3 + STR r3, [r2, #PHY_PTM_DFI_CLK_RANGE] + LDR r3, =0x0 + STR r3, [r2, #PHY_PTM_PLL_RANGE] + LDR r3, =0x0 + STR r3, [r2, #PHY_PTM_FEEBACK_DIV] + LDR r3, =0x0 + STR r3, [r2, #PHY_PTM_RCLK_DIV] + LDR r3, =0x1 + STR r3, [r2, #PHY_PTM_PLL_EN] + + // Wait for PHY to lock +waitloop_01: + LDR r3, [r2, #PHY_PTM_LOCK_STATUS] + AND r3, #0xff + CMP r3, #0x1 + BNE waitloop_01 + + LDR r3, =0x5 + STR r3, [r2, #PHY_PTM_IOTERM] + LDR r0, =ARM_VE_SCC_BASE + LDR r3, [r0, #SCC_PHY_RESET_REG_OFFSET] + ORR r3, r3, r1 + STR r3, [r0, #SCC_PHY_RESET_REG_OFFSET] + + // wait for PHY ready +waitloop_03: + LDR r3, [r2, #PHY_PTM_INIT_DONE] + AND r3, #0x1 + TST r3, #0x1 + BEQ waitloop_03 + + // Init PL341 + LDR r0, = ARM_VE_DMC_BASE + + LDR r1, =0x4 // enter config mode + STR r1, [r0, #DMC_COMMAND_REG] + LDR r1, =0xc30 + STR r1, [r0, #DMC_REFRESH_PRD_REG] + LDR r1, =0xc + STR r1, [r0, #DMC_CAS_LATENCY_REG] + LDR r1, =0x5 + STR r1, [r0, #DMC_WRITE_LATENCY_REG] + LDR r1, =0x2 + STR r1, [r0, #DMC_T_MRD_REG] + LDR r1, =0x12 + STR r1, [r0, #DMC_T_RAS_REG] + LDR r1, =0x18 + STR r1, [r0, #DMC_T_RC_REG] + LDR r1, =0x0306 + STR r1, [r0,#DMC_T_RCD_REG] + LDR r1, =0x00004c4f + STR r1, [r0, #DMC_T_RFC_REG] + LDR r1, =0x00000306 + STR r1, [r0, #DMC_T_RP_REG] + LDR r1, =0x4 + STR r1, [r0, #DMC_T_RRD_REG] + LDR r1, =0x6 + STR r1, [r0, #DMC_T_WR_REG] + LDR r1, =0x3 + STR r1, [r0, #DMC_T_WTR_REG] + LDR r1, =0x2 + STR r1, [r0, #DMC_T_XP_REG] + LDR r1, =0x52 + STR r1, [r0, #DMC_T_XSR_REG] + LDR r1, =0xc8 + STR r1, [r0, #DMC_T_ESR_REG] + LDR r1, =0x0b0e + STR r1, [r0, #DMC_T_FAW_REG] + LDR r1, =0x3 + STR r1, [r0, #DMC_T_RDATA_EN] + LDR r1, =0x1 + STR r1, [r0, #DMC_T_WRLAT_DIFF] + LDR r1, =0x00210022 + STR r1, [r0, #DMC_MEMORY_CONFIG_REG] + LDR r1, =0x0000007C + STR r1, [r0, #DMC_MEMORY_CFG2_REG] + LDR r1, =0x00000001 + STR r1, [r0, #DMC_MEMORY_CFG3_REG] + LDR r1, =0x000000c0 + STR r1, [r0, #DMC_CHIP_0_CFG_REG] + LDR r1, =0x00040c0 + STR r1, [r0, #DMC_CHIP_1_CFG_REG] + + // Configure DDR2 Devices on Chip Select 0 + // nop + LDR r1, =0x000C0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // pre-charge all + LDR r1, =0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_04: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_04 + + // extended mode register 2 (EMR2) + LDR r1, =0x000A0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // extended mode register 3 (EMR3) + LDR r1, =0x000B0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // extended mode register (EMR), OCD default state + LDR r1, =0x00090000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register (MR) with DLL reset + LDR r1,=0x00080B62 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // pre-charge all + LDR r1, =0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + LDR r1, =0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + LDR r1, =0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register (MR) without DLL reset + LDR r1,=0x00080A62 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_05: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_05 + + // extended mode register (EMR) enable OCD defaults + LDR r1, =0x00094384 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_06: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_06 + + // extended mode register (EMR) OCD Exit + LDR r1, =0x00094004 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_07: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_07 + + // Configure DDR2 Devices on Chip Select 1 + // send nop + // nop + LDR r1, =0x001C0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // pre-charge all + LDR r1, =0x00100000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_08: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_08 + + // set extended mode register 2 + LDR r1, =0x001A0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register 3 + LDR r1, =0x001B0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // extended mode register (EMR) OCD default state + LDR r1, =0x00190000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // mode register (MR) with DLL reset + LDR r1,=0x00180B62 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // pre-charge all + LDR r1, =0x00100000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + LDR r1, =0x00140000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + LDR r1, =0x00140000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + + // mode register (MR) without DLL reset + LDR r1,=0x00180A62 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_09: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_09 + + // extended mode register (EMR) enable OCD defaults + LDR r1, =0x00194384 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_10: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_10 + + // extended mode register (EMR) OCD Exit + LDR r1, =0x00194004 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // wait loop + LDR r1, =0x0 +waitloop_11: + LDR r3, [r0, #DMC_STATUS_REG] + ADD r1, r1, #1 + CMP r1, #10 + BLT waitloop_11 + + // go command + LDR r1, =DMC_COMMAND_GO + STR r1, [r0, #DMC_COMMAND_REG] + + // wait for ready +waitloop_12: + LDR r1, [r0,#DMC_STATUS_REG] + AND r1, #0x3 // Mask of all but memc_status bits + TST r1,#1 + BEQ waitloop_12 + + // PHY Squelch Training + LDR r3, =0x1 + STR r3, [r2, #PHY_PTM_SQU_TRAINING] + + LDR r5, =0x80000000 +waitloop_13: + LDR r4, =0 +waitloop_14: + LDR r3, [r5, #0] + ADD r4, #1 + CMP r4, #200 + BNE waitloop_14 + + // wait for ready + LDR r3, [r2,#PHY_PTM_SQU_STAT] + TST r3,#1 + BEQ waitloop_13 + + LDR r3, =0 + STR r3, [r2, #PHY_PTM_SQU_TRAINING] + + // For Test Chip Change Program architected timer frequency + MRC p15, 0, r0, c0, c1, 1 // CPUID_EXT_PFR1 + LSR r0, r0, #16 + ANDS r0, r0, #1 // Check generic timer support + BEQ exit + LDR r0, = 600000000 // 600MHz timer frequency + MCR p15, 0, r0, c14, c0, 0 // CNTFRQ + +exit: + bx lr + // end of dmc_init + diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm new file mode 100644 index 000000000..d0b792c35 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm @@ -0,0 +1,127 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Drivers/PL35xSmc.h> +#include <ArmPlatform.h> +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformSecBootAction + EXPORT ArmPlatformInitializeBootMemory + IMPORT PL35xSmcInitialize + + PRESERVE8 + AREA CTA15x2BootMode, CODE, READONLY + +// +// For each Chip Select: ChipSelect / SetCycle / SetOpMode +// +VersatileExpressSmcConfiguration + // NOR Flash 0 + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0) + DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // NOR Flash 1 + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4) + DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // SRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // Usb/Eth/VRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC + + // Memory Mapped Peripherals + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC + + // VRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1) + DCD 0x00049249 + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC +VersatileExpressSmcConfigurationEnd + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ArmPlatformSecBootAction + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformInitializeBootMemory + mov r5, lr + + // + // Initialize PL354 SMC + // + LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) + ldr r2, =VersatileExpressSmcConfiguration + ldr r3, =VersatileExpressSmcConfigurationEnd + blx PL35xSmcInitialize + + // + // Page mode setup for VRAM + // + LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2) + + // Read current state + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, [r2, #0] + + // Enable page mode + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, = 0x00900090 + str r0, [r2, #0] + + // Confirm page mode enabled + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, [r2, #0] + +ryan doesn't want this to happen + + bx r5 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.S new file mode 100644 index 000000000..5891eb4b6 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.S @@ -0,0 +1,62 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include <AsmMacroIoLib.h> +#include <Library/ArmLib.h> + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0) + ldr r0, [r0] + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformGetCorePosition): + and r0, r0, #ARM_CORE_MASK + bx lr + +ASM_PFX(ArmPlatformPeiBootAction): + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.asm new file mode 100644 index 000000000..9f4892b04 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.asm @@ -0,0 +1,70 @@ +// +// Copyright (c) 2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Library/ArmLib.h> + +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformPeiBootAction + EXPORT ArmPlatformIsPrimaryCore + EXPORT ArmPlatformGetPrimaryCoreMpId + EXPORT ArmPlatformGetCorePosition + + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask + + AREA CTA9x4Helper, CODE, READONLY + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ArmPlatformGetPrimaryCoreMpId FUNCTION + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0) + ldr r0, [r0] + bx lr + ENDFUNC + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ArmPlatformIsPrimaryCore FUNCTION + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ArmPlatformGetCorePosition FUNCTION + and r0, r0, #ARM_CORE_MASK + bx lr + ENDFUNC + +ArmPlatformPeiBootAction FUNCTION + bx lr + ENDFUNC + + END diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c new file mode 100644 index 000000000..eee3c3c9f --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c @@ -0,0 +1,128 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> + +#include <ArmPlatform.h> + +// Number of Virtual Memory Map Descriptors without a Logic Tile +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ; + + if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) { + // Map the NOR Flash as Secure Memory + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + } else { + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED; + } + } else { + // DRAM mapping + VirtualMemoryTable[Index].Attributes = CacheAttributes; + } + + // DDR + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SMC CS7 + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS0-CS1 - NOR Flash 1 & 2 + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS2 - SRAM + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SMB CS3-CS6 - Motherboard Peripherals + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // If a Logic Tile is connected to The ARM Versatile Express Motherboard + if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) { + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1)); + } else { + ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c new file mode 100644 index 000000000..d9d3ff731 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Drivers/PL310L2Cache.h> +#include <Drivers/SP804Timer.h> +#include <ArmPlatform.h> + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformTrustzoneInit ( + VOID + ) +{ + // No TZPC or TZASC on RTSM to initialize +} + +/** + Initialize controllers that must setup at the early stage + + Some peripherals must be initialized in Secure World. + For example, some L2x0 requires to be initialized in Secure World + +**/ +VOID +ArmPlatformSecInitialize ( + VOID + ) +{ + // Configure periodic timer (TIMER0) for 1MHz operation + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); + // Configure 1MHz clock + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); +} + +/** + Call before jumping to Normal World + + This function allows the firmware platform to do extra actions before + jumping to the Normal World + +**/ +VOID +ArmPlatformSecExtraAction ( + IN UINTN MpId, + OUT UINTN* JumpAddress + ) +{ + *JumpAddress = PcdGet32(PcdFvBaseAddress); +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf new file mode 100644 index 000000000..de141a86b --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf @@ -0,0 +1,54 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CTA5sArmVExpressLib + FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + IoLib + ArmLib + PL341DmcLib + PL301AxiLib + L2X0CacheLib + SerialPortLib + +[Sources.common] + CTA5s.c + CTA5sMem.c + CTA5Helper.asm | RVCT + CTA5Helper.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf new file mode 100644 index 000000000..f0521b95c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf @@ -0,0 +1,53 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CTA5sArmVExpressLib + FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformSysConfigLib + IoLib + L2X0CacheLib + PL301AxiLib + PL341DmcLib + PL35xSmcLib + SerialPortLib + +[Sources.common] + CTA5sSec.c + CTA5s.c + CTA5sBoot.asm | RVCT + CTA5sBoot.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.S new file mode 100644 index 000000000..5891eb4b6 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.S @@ -0,0 +1,62 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include <AsmMacroIoLib.h> +#include <Library/ArmLib.h> + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0) + ldr r0, [r0] + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformGetCorePosition): + and r0, r0, #ARM_CORE_MASK + bx lr + +ASM_PFX(ArmPlatformPeiBootAction): + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.asm new file mode 100644 index 000000000..9f4892b04 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.asm @@ -0,0 +1,70 @@ +// +// Copyright (c) 2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Library/ArmLib.h> + +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformPeiBootAction + EXPORT ArmPlatformIsPrimaryCore + EXPORT ArmPlatformGetPrimaryCoreMpId + EXPORT ArmPlatformGetCorePosition + + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask + + AREA CTA9x4Helper, CODE, READONLY + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ArmPlatformGetPrimaryCoreMpId FUNCTION + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0) + ldr r0, [r0] + bx lr + ENDFUNC + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ArmPlatformIsPrimaryCore FUNCTION + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ArmPlatformGetCorePosition FUNCTION + and r0, r0, #ARM_CORE_MASK + bx lr + ENDFUNC + +ArmPlatformPeiBootAction FUNCTION + bx lr + ENDFUNC + + END diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c new file mode 100644 index 000000000..ccf6fe0a6 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c @@ -0,0 +1,162 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/SerialPortLib.h> + +#include <Drivers/PL341Dmc.h> +#include <Drivers/PL301Axi.h> +#include <Drivers/SP804Timer.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include <ArmPlatform.h> + +#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1); + +ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA5s[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) { + return BOOT_WITH_FULL_CONFIGURATION; + } else { + return BOOT_ON_S2_RESUME; + } +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + // Configure periodic timer (TIMER0) for 1MHz operation + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); + // Configure 1MHz clock + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); + // configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Memory is initialised in CTA5sBoot.S +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA5s) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mVersatileExpressMpCoreInfoCTA5s; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S new file mode 100644 index 000000000..62750bde2 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S @@ -0,0 +1,386 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Drivers/PL35xSmc.h> +#include <Drivers/PL341Dmc.h> +#include <ArmPlatform.h> +#include <AutoGen.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformSecBootAction) +GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory) +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ASM_PFX(ArmPlatformSecBootAction): + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformInitializeBootMemory): + bx lr + + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformSecBootMemoryInit): + mov r8, lr + bl smc_init + bl dmc_init + bx r8 + + +/** + Initialise the Static Memory Controller +**/ +smc_init: + + // + // Disable loop buffer for A15 + // + MRC p15, 0, r2, c0, c0, 0 + MOV r1, r2, lsr #4 + LDR r0, =0xFFF + AND r1, r1, r0 + LDR r0, =0xC0F // See if A15 + CMP r1, r0 + BNE smc_init2 // Go if not + + MRC p15, 0, r1, c1, c0, 1 // Read Aux Ctrl Reg + ORR r1, r1, #(1 << 1) // Set Bit 1 + MCR p15, 0, r1, c1, c0, 1 // and write it back + +smc_init2: + + LDR r0, = ARM_VE_SMC_CTRL_BASE + LDR r2, = ARM_VE_SMB_PERIPH_BASE + + // CS0 - NOR0 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS1 - PSRAM + LDR r1, = 0x00027158 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000802 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS2 - usb, ethernet and vram + LDR r1, = 0x000CD2AA + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS3 - IOFPGA peripherals + LDR r1, = 0x00025156 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS4 - NOR1 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS5 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS6 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS7 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // Set refresh period + LDR r1, = 0x1 + STR r1, [r0, #0x20] + + LDR r1, = 0x1 + STR r1, [r0, #0x24] + + // page mode setup for VRAM + LDR r0, = 0x00FFFFFC + ADD r0, r0, r2 + + // read current state + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + // enable page mode + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, = 0x00900090 + STR r1, [r0, #0] + + // confirm page mode enabled + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + BX lr + // end of smc_init + + +/** + Initialise the PL341 Dynamic Memory Controller (DMC) + + On A15, the PHY needs to be locked before configuring the DMC. + After DMC config, the PHY needs to be trained +**/ +#define SCC_PHY_RESET_REG_OFFSET 0x04 + +dmc_init: + + LDR r0, = ARM_VE_DMC_BASE + LDR r1, = ARM_VE_BOARD_PERIPH_BASE + + // On entry:- + // r0 = base address of ssmc controller + // r1 = address of system registers + + // Initializes V2P_CA5 dynamic memory controller + + MOV r2, r1 + + // set config mode + MOV r1, #0x4 + STR r1, [r0, #DMC_COMMAND_REG] + + // initialise memory controlller + + // refresh period + LDR r1, =0x3D0 + STR r1, [r0, #DMC_REFRESH_PRD_REG] + + // cas latency + MOV r1, #0xA + STR r1, [r0, #DMC_CAS_LATENCY_REG] + + // write latency + MOV r1, #0x3 + STR r1, [r0, #DMC_WRITE_LATENCY_REG] + + // t_mrd + MOV r1, #0x2 + STR r1, [r0, #DMC_T_MRD_REG] + + // t_ras + MOV r1, #0x0C + STR r1, [r0, #DMC_T_RAS_REG] + + // t_rc + MOV r1, #0x0F + STR r1, [r0, #DMC_T_RC_REG] + + // t_rcd + LDR r1, =0x00000104 + STR r1, [r0,#DMC_T_RCD_REG] + + // t_rfc + LDR r1, =0x00001022 + STR r1, [r0, #DMC_T_RFC_REG] + + // t_rp + LDR r1, =0x00000104 + STR r1, [r0, #DMC_T_RP_REG] + + // t_rrd + MOV r1, #0x2 + STR r1, [r0, #DMC_T_RRD_REG] + + // t_wr + MOV r1, #0x4 + STR r1, [r0, #DMC_T_WR_REG] + + // t_wtr + MOV r1, #0x2 + STR r1, [r0, #DMC_T_WTR_REG] + + // t_xp + MOV r1, #0x2 + STR r1, [r0, #DMC_T_XP_REG] + + // t_xsr + MOV r1, #0xC8 + STR r1, [r0, #DMC_T_XSR_REG] + + // t_esr + MOV r1, #0x04 + STR r1, [r0, #DMC_T_ESR_REG] + + // t_faw + LDR r1, =0x00000407 + STR r1, [r0, #DMC_T_FAW_REG] + + // set memory config + LDR r1, =0x0001001A + STR r1, [r0, #DMC_MEMORY_CONFIG_REG] + + // set memory config 2 + LDR r1, =0x000000B0 + STR r1, [r0, #DMC_MEMORY_CFG2_REG] + + // initialise external memory chips + // set chip select for chip configuration + LDR r1, =0x000180C0 + STR r1, [r0, #DMC_CHIP_0_CFG_REG] + + // config memories + + // send nop + LDR r1, =0x000C0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B1: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B1 + + // pre-charge all + MOV r1, #0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B2: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B2 + + // set extended mode register 2 + LDR r1, =0x000A8000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register 3 + MOV r1, #0x000B0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register + LDR r1, =0x00094005 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register -DLL reset + LDR r1, =0x00080552 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B3: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B3 + + // pre-charge all + MOV r1, #0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + MOV r1, #0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + MOV r1, #0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register + LDR r1, =0x00080452 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register - Enable OCD defaults + LDR r1, =0x000943C5 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register - OCD Exit + LDR r1, =0x00094047 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + //---------------------------------------- + // go command + MOV r1, #0x0 + STR r1, [r0, #DMC_COMMAND_REG] + + // wait for ready +B4: LDR r1, [r0,#DMC_STATUS_REG] + TST r1,#1 + BEQ B4 + +exit: + bx lr + // end of dmc_init + diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.asm new file mode 100644 index 000000000..39d903378 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.asm @@ -0,0 +1,127 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Drivers/PL35xSmc.h> +#include <ArmPlatform.h> +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformSecBootAction + EXPORT ArmPlatformInitializeBootMemory + IMPORT PL35xSmcInitialize + + PRESERVE8 + AREA CTA5sBootMode, CODE, READONLY + +// +// For each Chip Select: ChipSelect / SetCycle / SetOpMode +// +VersatileExpressSmcConfiguration + // NOR Flash 0 + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0) + DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // NOR Flash 1 + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4) + DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // SRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // Usb/Eth/VRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC + + // Memory Mapped Peripherals + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC + + // VRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1) + DCD 0x00049249 + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC +VersatileExpressSmcConfigurationEnd + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ArmPlatformSecBootAction + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformInitializeBootMemory + mov r5, lr + + // + // Initialize PL354 SMC + // + LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) + ldr r2, =VersatileExpressSmcConfiguration + ldr r3, =VersatileExpressSmcConfigurationEnd + blx PL35xSmcInitialize + + // + // Page mode setup for VRAM + // + LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2) + + // Read current state + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, [r2, #0] + + // Enable page mode + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, = 0x00900090 + str r0, [r2, #0] + + // Confirm page mode enabled + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, [r2, #0] + +ryan doesn't want this to happen + + bx r5 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sMem.c new file mode 100644 index 000000000..eee3c3c9f --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sMem.c @@ -0,0 +1,128 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> + +#include <ArmPlatform.h> + +// Number of Virtual Memory Map Descriptors without a Logic Tile +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ; + + if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) { + // Map the NOR Flash as Secure Memory + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + } else { + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED; + } + } else { + // DRAM mapping + VirtualMemoryTable[Index].Attributes = CacheAttributes; + } + + // DDR + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SMC CS7 + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS0-CS1 - NOR Flash 1 & 2 + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS2 - SRAM + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SMB CS3-CS6 - Motherboard Peripherals + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // If a Logic Tile is connected to The ARM Versatile Express Motherboard + if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) { + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1)); + } else { + ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sSec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sSec.c new file mode 100644 index 000000000..d9d3ff731 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sSec.c @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Drivers/PL310L2Cache.h> +#include <Drivers/SP804Timer.h> +#include <ArmPlatform.h> + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformTrustzoneInit ( + VOID + ) +{ + // No TZPC or TZASC on RTSM to initialize +} + +/** + Initialize controllers that must setup at the early stage + + Some peripherals must be initialized in Secure World. + For example, some L2x0 requires to be initialized in Secure World + +**/ +VOID +ArmPlatformSecInitialize ( + VOID + ) +{ + // Configure periodic timer (TIMER0) for 1MHz operation + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); + // Configure 1MHz clock + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); +} + +/** + Call before jumping to Normal World + + This function allows the firmware platform to do extra actions before + jumping to the Normal World + +**/ +VOID +ArmPlatformSecExtraAction ( + IN UINTN MpId, + OUT UINTN* JumpAddress + ) +{ + *JumpAddress = PcdGet32(PcdFvBaseAddress); +} diff --git a/ArmPlatformPkg/Bds/Bds.c b/ArmPlatformPkg/Bds/Bds.c index 2801fac53..3a66eb3aa 100644 --- a/ArmPlatformPkg/Bds/Bds.c +++ b/ArmPlatformPkg/Bds/Bds.c @@ -223,8 +223,10 @@ DefineDefaultBootEntries ( ARM_BDS_LOADER_ARGUMENTS* BootArguments;
ARM_BDS_LOADER_TYPE BootType;
EFI_DEVICE_PATH* InitrdPath;
+ EFI_DEVICE_PATH* FdtLocalPath; UINTN CmdLineSize;
UINTN InitrdSize;
+ UINTN FdtLocalSize; //
// If Boot Order does not exist then create a default entry
@@ -255,24 +257,47 @@ DefineDefaultBootEntries ( ASSERT (StrCmp ((CHAR16*)PcdGetPtr(PcdDefaultBootDevicePath), DevicePathTxt) == 0);
- FreePool (DevicePathTxt);
+ if (DevicePathTxt != NULL){ + FreePool (DevicePathTxt); + } DEBUG_CODE_END();
// Create the entry is the Default values are correct
if (BootDevicePath != NULL) {
BootType = (ARM_BDS_LOADER_TYPE)PcdGet32 (PcdDefaultBootType);
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { CmdLineSize = AsciiStrSize ((CHAR8*)PcdGetPtr(PcdDefaultBootArgument));
InitrdPath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdDefaultBootInitrdPath));
- InitrdSize = GetDevicePathSize (InitrdPath);
-
- BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize);
- BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
- BootArguments->LinuxArguments.InitrdSize = InitrdSize;
-
- CopyMem ((VOID*)(BootArguments + 1), (CHAR8*)PcdGetPtr(PcdDefaultBootArgument), CmdLineSize);
- CopyMem ((VOID*)((UINTN)(BootArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
+ if (InitrdPath != NULL) { + InitrdSize = GetDevicePathSize (InitrdPath); + } else { + InitrdSize = 0; + } + if (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) { + FdtLocalPath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdDefaultFdtLocalDevicePath)); + FdtLocalSize = GetDevicePathSize (FdtLocalPath); + } else { + FdtLocalPath = NULL; + FdtLocalSize = 0; + } +
+ BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize + FdtLocalSize); + if ( BootArguments != NULL ) { + BootArguments->LinuxArguments.CmdLineSize = CmdLineSize; + BootArguments->LinuxArguments.InitrdSize = InitrdSize; + BootArguments->LinuxArguments.FdtLocalSize = FdtLocalSize; + + CopyMem ((VOID*)(BootArguments + 1), (CHAR8*)PcdGetPtr(PcdDefaultBootArgument), CmdLineSize); + CopyMem ((VOID*)((UINTN)(BootArguments + 1) + CmdLineSize), InitrdPath, InitrdSize); + CopyMem ((VOID*)((UINTN)(BootArguments + 1) + CmdLineSize + InitrdSize), FdtLocalPath, FdtLocalSize); + } + if (FdtLocalPath != NULL ) { + FreePool (FdtLocalPath); + } + if (InitrdPath != NULL ) { + FreePool (InitrdPath); + } } else {
BootArguments = NULL;
}
@@ -284,7 +309,12 @@ DefineDefaultBootEntries ( BootArguments,
&BdsLoadOption
);
- FreePool (BdsLoadOption);
+ if (BdsLoadOption != NULL){ + FreePool (BdsLoadOption); + } + if (BootDevicePath != NULL){ + FreePool (BootDevicePath); + } } else {
Status = EFI_UNSUPPORTED;
}
diff --git a/ArmPlatformPkg/Bds/Bds.inf b/ArmPlatformPkg/Bds/Bds.inf index 5faa4b2ee..a032d5e47 100644 --- a/ArmPlatformPkg/Bds/Bds.inf +++ b/ArmPlatformPkg/Bds/Bds.inf @@ -68,6 +68,7 @@ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument
gArmPlatformTokenSpaceGuid.PcdDefaultBootType
gArmPlatformTokenSpaceGuid.PcdFdtDevicePath
+ gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths
diff --git a/ArmPlatformPkg/Bds/BdsHelper.c b/ArmPlatformPkg/Bds/BdsHelper.c index 5e1b9935c..a0dc74be4 100644 --- a/ArmPlatformPkg/Bds/BdsHelper.c +++ b/ArmPlatformPkg/Bds/BdsHelper.c @@ -35,7 +35,7 @@ EditHIInputStr ( Print (CmdLine);
// To prevent a buffer overflow, we only allow to enter (MaxCmdLine-1) characters
- for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine - 1; ) {
+ for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine; ) {
Status = gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &WaitIndex);
ASSERT_EFI_ERROR (Status);
@@ -62,7 +62,7 @@ EditHIInputStr ( }
} else if ((Key.ScanCode == SCAN_ESC) || (Char == 0x1B) || (Char == 0x0)) {
return EFI_INVALID_PARAMETER;
- } else {
+ } else if (CmdLineIndex < (MaxCmdLine-1)) {
CmdLine[CmdLineIndex++] = Key.UnicodeChar;
Print (L"%c", Key.UnicodeChar);
}
diff --git a/ArmPlatformPkg/Bds/BdsInternal.h b/ArmPlatformPkg/Bds/BdsInternal.h index a8d836d86..1de20efd0 100644 --- a/ArmPlatformPkg/Bds/BdsInternal.h +++ b/ArmPlatformPkg/Bds/BdsInternal.h @@ -38,6 +38,11 @@ #define BOOT_DEVICE_OPTION_MAX 300
#define BOOT_DEVICE_ADDRESS_MAX (sizeof(L"0x0000000000000000"))
+// Length of the buffer used to hold the user input for the main menu +// This includes the NULL terminator +// 1 chars + newline + NULL gives room for up to 9 boot device configs +#define BOOT_OPTION_LEN 3 + #define ARM_BDS_OPTIONAL_DATA_SIGNATURE SIGNATURE_32('a', 'b', 'o', 'd')
#define IS_ARM_BDS_BOOTENTRY(ptr) (ReadUnaligned32 ((CONST UINT32*)&((ARM_BDS_LOADER_OPTIONAL_DATA*)((ptr)->OptionalData))->Header.Signature) == ARM_BDS_OPTIONAL_DATA_SIGNATURE)
@@ -48,16 +53,20 @@ typedef enum {
BDS_LOADER_EFI_APPLICATION = 0,
BDS_LOADER_KERNEL_LINUX_ATAG,
- BDS_LOADER_KERNEL_LINUX_FDT,
+ BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT, + BDS_LOADER_KERNEL_LINUX_LOCAL_FDT, } ARM_BDS_LOADER_TYPE;
typedef struct {
UINT16 CmdLineSize;
UINT16 InitrdSize;
+ UINT16 FdtLocalSize; + // These following fields have variable length and are packed:
//CHAR8 *CmdLine;
//EFI_DEVICE_PATH_PROTOCOL *InitrdPathList;
+ //EFI_DEVICE_PATH_PROTOCOL *FdtLocalPathList; } ARM_BDS_LINUX_ARGUMENTS;
typedef union {
diff --git a/ArmPlatformPkg/Bds/BootMenu.c b/ArmPlatformPkg/Bds/BootMenu.c index 1b101d45c..dd03f5a8a 100644 --- a/ArmPlatformPkg/Bds/BootMenu.c +++ b/ArmPlatformPkg/Bds/BootMenu.c @@ -128,9 +128,12 @@ BootMenuAddBootOption ( EFI_DEVICE_PATH_PROTOCOL *DevicePathNodes;
EFI_DEVICE_PATH_PROTOCOL *InitrdPathNodes;
EFI_DEVICE_PATH_PROTOCOL *InitrdPath;
+ EFI_DEVICE_PATH_PROTOCOL *FdtLocalPathNode; + EFI_DEVICE_PATH_PROTOCOL *FdtLocalPath; UINTN CmdLineSize;
BOOLEAN InitrdSupport;
UINTN InitrdSize;
+ UINTN FdtLocalSize; Attributes = 0;
SupportedBootDevice = NULL;
@@ -155,12 +158,12 @@ BootMenuAddBootOption ( goto EXIT;
}
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { Print(L"Add an initrd: ");
Status = GetHIInputBoolean (&InitrdSupport);
if (EFI_ERROR(Status)) {
Status = EFI_ABORTED;
- goto EXIT;
+ goto FREE_DEVICE_PATH; }
if (InitrdSupport) {
@@ -168,7 +171,7 @@ BootMenuAddBootOption ( Status = SupportedBootDevice->Support->CreateDevicePathNode (L"initrd", &InitrdPathNodes, NULL, NULL);
if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) { // EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
Status = EFI_ABORTED;
- goto EXIT;
+ goto FREE_DEVICE_PATH; }
if (InitrdPathNodes != NULL) {
@@ -176,7 +179,7 @@ BootMenuAddBootOption ( InitrdPath = AppendDevicePath (SupportedBootDevice->DevicePathProtocol, (CONST EFI_DEVICE_PATH_PROTOCOL *)InitrdPathNodes);
if (InitrdPath == NULL) {
Status = EFI_OUT_OF_RESOURCES;
- goto EXIT;
+ goto FREE_DEVICE_PATH; }
} else {
InitrdPath = NULL;
@@ -192,15 +195,37 @@ BootMenuAddBootOption ( goto FREE_DEVICE_PATH;
}
- CmdLineSize = AsciiStrSize (CmdLine);
- InitrdSize = GetDevicePathSize (InitrdPath);
-
- BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize);
-
- BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
- BootArguments->LinuxArguments.InitrdSize = InitrdSize;
- CopyMem ((VOID*)(&BootArguments->LinuxArguments + 1), CmdLine, CmdLineSize);
- CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
+ if (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) { + // Create the specific device path node + Status = SupportedBootDevice->Support->CreateDevicePathNode (L"local FDT", &FdtLocalPathNode, NULL, NULL); + if (EFI_ERROR(Status) || (FdtLocalPathNode == NULL)) { + Status = EFI_ABORTED; + goto FREE_DEVICE_PATH; + } +
+ if (FdtLocalPathNode != NULL) { + // Append the Device Path node to the select device path + FdtLocalPath = AppendDevicePathNode (SupportedBootDevice->DevicePathProtocol, (CONST EFI_DEVICE_PATH_PROTOCOL *)FdtLocalPathNode); + } else { + FdtLocalPath = NULL; + } + } else { + FdtLocalPath = NULL; + } +
+ CmdLineSize = AsciiStrSize (CmdLine); + InitrdSize = GetDevicePathSize (InitrdPath); + FdtLocalSize = GetDevicePathSize (FdtLocalPath); + + BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize + FdtLocalSize); + if ( BootArguments != NULL ) { + BootArguments->LinuxArguments.CmdLineSize = CmdLineSize; + BootArguments->LinuxArguments.InitrdSize = InitrdSize; + BootArguments->LinuxArguments.FdtLocalSize = FdtLocalSize; + CopyMem ((VOID*)(&BootArguments->LinuxArguments + 1), CmdLine, CmdLineSize); + CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize); + CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize + InitrdSize), FdtLocalPath, FdtLocalSize); + } } else {
BootArguments = NULL;
}
@@ -214,6 +239,10 @@ BootMenuAddBootOption ( // Create new entry
BdsLoadOptionEntry = (BDS_LOAD_OPTION_ENTRY*)AllocatePool (sizeof(BDS_LOAD_OPTION_ENTRY));
+ if ( BdsLoadOptionEntry == NULL ) { + Status = EFI_ABORTED; + goto FREE_DEVICE_PATH; + } Status = BootOptionCreate (Attributes, BootDescription, DevicePath, BootType, BootArguments, &BdsLoadOptionEntry->BdsLoadOption);
if (!EFI_ERROR(Status)) {
InsertTailList (BootOptionsList, &BdsLoadOptionEntry->Link);
@@ -274,7 +303,7 @@ BootMenuSelectBootOption ( Print(L"\t- %s\n",DevicePathTxt);
OptionalData = BdsLoadOption->OptionalData;
LoaderType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
- if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { Print (L"\t- Arguments: %a\n",&OptionalData->Arguments.LinuxArguments + 1);
}
@@ -366,14 +395,19 @@ BootMenuUpdateBootOption ( CHAR8 CmdLine[BOOT_DEVICE_OPTION_MAX];
EFI_DEVICE_PATH *DevicePath;
EFI_DEVICE_PATH *TempInitrdPath;
+ EFI_DEVICE_PATH *TempFdtLocalPath; ARM_BDS_LOADER_TYPE BootType;
ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
ARM_BDS_LINUX_ARGUMENTS* LinuxArguments;
EFI_DEVICE_PATH *InitrdPathNodes;
EFI_DEVICE_PATH *InitrdPath;
UINTN InitrdSize;
+ EFI_DEVICE_PATH *FdtLocalPathNode; + EFI_DEVICE_PATH *FdtLocalPath; + UINTN FdtLocalSize; UINTN CmdLineSize;
BOOLEAN InitrdSupport;
+ BOOLEAN FdtLocalSupport; Status = BootMenuSelectBootOption (BootOptionsList, UPDATE_BOOT_ENTRY, TRUE, &BootOptionEntry);
if (EFI_ERROR(Status)) {
@@ -397,12 +431,65 @@ BootMenuUpdateBootOption ( OptionalData = BootOption->OptionalData;
BootType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((UINT32 *)(&OptionalData->Header.LoaderType));
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { LinuxArguments = &OptionalData->Arguments.LinuxArguments;
CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
+ FdtLocalSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->FdtLocalSize); + + if (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) { + if (FdtLocalSize > 0) { + Print(L"Keep the local FDT: "); + } else { + Print(L"Add a local FDT: "); + } + Status = GetHIInputBoolean (&FdtLocalSupport); + if (EFI_ERROR(Status)) { + Status = EFI_ABORTED; + goto EXIT; + } + if (FdtLocalSupport && BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) { + if (FdtLocalSize > 0) { + // Case we update the FDT local device path + Status = DeviceSupport->UpdateDevicePathNode ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize + InitrdSize), L"local FDT", &FdtLocalPath, NULL, NULL); + if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) {// EFI_NOT_FOUND is returned on empty input string + Status = EFI_ABORTED; + goto EXIT; + } + FdtLocalSize = GetDevicePathSize (FdtLocalPath); + } else { + // Case we create the FdtLocal device path + + Status = DeviceSupport->CreateDevicePathNode (L"local FDT", &FdtLocalPathNode, NULL, NULL); + if (EFI_ERROR(Status) || (FdtLocalPathNode == NULL)) { + Status = EFI_ABORTED; + goto EXIT; + } + + if (FdtLocalPathNode != NULL) { + // Duplicate Linux kernel Device Path + TempFdtLocalPath = DuplicateDevicePath (BootOption->FilePathList); + if ( TempFdtLocalPath != NULL ) { + // Replace Linux kernel Node by EndNode + SetDevicePathEndNode (GetLastDevicePathNode (TempFdtLocalPath)); + // Append the Device Path node to the select device path + FdtLocalPath = AppendDevicePathNode (TempFdtLocalPath, (CONST EFI_DEVICE_PATH_PROTOCOL *)FdtLocalPathNode); + FreePool (TempFdtLocalPath); + FdtLocalSize = GetDevicePathSize (FdtLocalPath); + } + } else { + FdtLocalPath = NULL; + } + } + } else { + FdtLocalSize = 0; + } + } else { + FdtLocalSupport = FALSE; + } + if (InitrdSize > 0) {
Print(L"Keep the initrd: ");
} else {
@@ -467,11 +554,15 @@ BootMenuUpdateBootOption ( CmdLineSize = AsciiStrSize (CmdLine);
- BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool(sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize);
- BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
- BootArguments->LinuxArguments.InitrdSize = InitrdSize;
- CopyMem (&BootArguments->LinuxArguments + 1, CmdLine, CmdLineSize);
- CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
+ BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool(sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize + FdtLocalSize); + if ( BootArguments != NULL ) { + BootArguments->LinuxArguments.CmdLineSize = CmdLineSize; + BootArguments->LinuxArguments.InitrdSize = InitrdSize; + BootArguments->LinuxArguments.FdtLocalSize = FdtLocalSize; + CopyMem (&BootArguments->LinuxArguments + 1, CmdLine, CmdLineSize); + CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize); + CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize + InitrdSize), FdtLocalPath, FdtLocalSize); + } } else {
BootArguments = NULL;
}
@@ -614,12 +705,32 @@ BootShell ( return Status;
}
+EFI_STATUS +Reboot ( + IN LIST_ENTRY *BootOptionsList + ) +{ + gRT->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +Shutdown ( + IN LIST_ENTRY *BootOptionsList + ) +{ + gRT->ResetSystem(EfiResetShutdown, EFI_SUCCESS, 0, NULL); + return EFI_UNSUPPORTED; +} + struct BOOT_MAIN_ENTRY {
CONST CHAR16* Description;
EFI_STATUS (*Callback) (IN LIST_ENTRY *BootOptionsList);
} BootMainEntries[] = {
- { L"Shell", BootShell },
{ L"Boot Manager", BootMenuManager },
+ { L"Shell", BootShell }, + { L"Reboot", Reboot }, + { L"Shutdown", Shutdown }, };
@@ -628,15 +739,21 @@ BootMenuMain ( VOID
)
{
- LIST_ENTRY BootOptionsList;
- UINTN OptionCount;
- UINTN BootOptionCount;
- EFI_STATUS Status;
- LIST_ENTRY* Entry;
- BDS_LOAD_OPTION* BootOption;
- UINTN BootOptionSelected;
- UINTN Index;
- UINTN BootMainEntryCount;
+ LIST_ENTRY BootOptionsList; + UINTN OptionCount; + UINTN BootOptionCount; + EFI_STATUS Status; + LIST_ENTRY* Entry; + BDS_LOAD_OPTION* BootOption; + UINTN BootOptionSelected; + UINTN Index; + UINTN BootMainEntryCount; + CHAR8 BootOptionSelectedStr[BOOT_OPTION_LEN]; + EFI_DEVICE_PATH_PROTOCOL* DefaultFdtDevicePath; + UINTN FdtDevicePathSize; + EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol; + CHAR16* DevicePathTxt; + BootOption = NULL;
BootMainEntryCount = sizeof(BootMainEntries) / sizeof(struct BOOT_MAIN_ENTRY);
@@ -657,11 +774,10 @@ BootMenuMain ( Print(L"[%d] %s\n", OptionCount, BootOption->Description);
- DEBUG_CODE_BEGIN();
- CHAR16* DevicePathTxt;
- EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+ //DEBUG_CODE_BEGIN(); ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
UINTN CmdLineSize;
+ UINTN InitrdSize; ARM_BDS_LOADER_TYPE LoaderType;
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
@@ -678,7 +794,7 @@ BootMenuMain ( if (IS_ARM_BDS_BOOTENTRY (BootOption)) {
OptionalData = BootOption->OptionalData;
LoaderType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
- if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { if (ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.InitrdSize) > 0) {
CmdLineSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.CmdLineSize);
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (
@@ -697,24 +813,64 @@ BootMenuMain ( Print(L"\t- LoaderType: Linux kernel with ATAG support\n");
break;
- case BDS_LOADER_KERNEL_LINUX_FDT:
- Print(L"\t- LoaderType: Linux kernel with FDT support\n");
+ case BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT: + Print(L"\t- LoaderType: Linux kernel with global FDT support\n"); + break; + case BDS_LOADER_KERNEL_LINUX_LOCAL_FDT: + if (ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.FdtLocalSize) > 0) { + CmdLineSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.CmdLineSize); + InitrdSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.InitrdSize); + DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText ( + GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(&OptionalData->Arguments.LinuxArguments + 1) + CmdLineSize + InitrdSize)), TRUE, TRUE); + Print(L"\t- FDT: %s\n", DevicePathTxt); + } else { + Print(L"\t- FDT: error, local FDT not specified, using global FDT\n"); + } + Print(L"\t- LoaderType: Linux kernel with Local FDT\n"); break;
-
default:
Print(L"\t- LoaderType: Not recognized (%d)\n", LoaderType);
+ break; }
}
FreePool(DevicePathTxt);
- DEBUG_CODE_END();
+ //DEBUG_CODE_END(); OptionCount++;
}
BootOptionCount = OptionCount-1;
+ // Display the global FDT config + Print(L"-----------------------\n"); + { + EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL* EfiDevicePathFromTextProtocol; + EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath; + + // Get the default FDT device path + Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol); + ASSERT_EFI_ERROR(Status); + DefaultFdtDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdFdtDevicePath)); + + // Get the FDT device path + FdtDevicePathSize = GetDevicePathSize (DefaultFdtDevicePath); + Status = GetEnvironmentVariable ((CHAR16 *)L"Fdt", &gArmGlobalVariableGuid, DefaultFdtDevicePath, &FdtDevicePathSize, (VOID **)&FdtDevicePath); + + // Convert FdtDevicePath to text + if (EFI_ERROR(Status)) { + DevicePathTxt = L"not configured"; + } else { + Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol); + DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText ( FdtDevicePath, TRUE, TRUE ); + } + Print(L"Global FDT Config\n\t- %s\n", DevicePathTxt); + FreePool(DevicePathTxt); + FreePool(DefaultFdtDevicePath); + } + // Display the hardcoded Boot entries
+ Print(L"-----------------------\n"); for (Index = 0; Index < BootMainEntryCount; Index++) {
- Print(L"[%d] %s\n",OptionCount,BootMainEntries[Index]);
+ Print(L"[%c] %s\n", ('a' + Index), BootMainEntries[Index]); OptionCount++;
}
@@ -722,11 +878,20 @@ BootMenuMain ( BootOptionSelected = 0;
while (BootOptionSelected == 0) {
Print(L"Start: ");
- Status = GetHIInputInteger (&BootOptionSelected);
- if (EFI_ERROR(Status) || (BootOptionSelected == 0) || (BootOptionSelected > OptionCount)) {
- Print(L"Invalid input (max %d)\n",(OptionCount-1));
- BootOptionSelected = 0;
- }
+ Status = GetHIInputAscii (BootOptionSelectedStr, BOOT_OPTION_LEN); + + if (!EFI_ERROR(Status)) { + if ((BootOptionSelectedStr[0] - '0') < OptionCount) { + BootOptionSelected = BootOptionSelectedStr[0] - '0'; + } else if ((BootOptionSelectedStr[0] - 'a') < BootMainEntryCount) { + BootOptionSelected = BootOptionCount + 1 + BootOptionSelectedStr[0] - 'a'; + } + + if ((BootOptionSelected == 0) || (BootOptionSelected > OptionCount)) { + Print(L"Invalid input, please choose a menu option from the list above\n"); + BootOptionSelected = 0; + } + } }
// Start the selected entry
diff --git a/ArmPlatformPkg/Bds/BootOption.c b/ArmPlatformPkg/Bds/BootOption.c index ee0301ef2..7bbd548c8 100644 --- a/ArmPlatformPkg/Bds/BootOption.c +++ b/ArmPlatformPkg/Bds/BootOption.c @@ -33,6 +33,7 @@ BootOptionStart ( UINTN CmdLineSize;
UINTN InitrdSize;
EFI_DEVICE_PATH* Initrd;
+ UINTN FdtLocalSize; UINT16 LoadOptionIndexSize;
if (IS_ARM_BDS_BOOTENTRY (BootOption)) {
@@ -59,7 +60,7 @@ BootOptionStart ( Status = BdsBootLinuxAtag (BootOption->FilePathList,
Initrd, // Initrd
(CHAR8*)(LinuxArguments + 1)); // CmdLine
- } else if (LoaderType == BDS_LOADER_KERNEL_LINUX_FDT) {
+ } else if ((LoaderType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { LinuxArguments = &(OptionalData->Arguments.LinuxArguments);
CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
@@ -70,17 +71,27 @@ BootOptionStart ( Initrd = NULL;
}
- // Get the default FDT device path
- Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
- ASSERT_EFI_ERROR(Status);
- DefaultFdtDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdFdtDevicePath));
-
- // Get the FDT device path
- FdtDevicePathSize = GetDevicePathSize (DefaultFdtDevicePath);
- Status = GetEnvironmentVariable ((CHAR16 *)L"Fdt", &gArmGlobalVariableGuid,
- DefaultFdtDevicePath, &FdtDevicePathSize, (VOID **)&FdtDevicePath);
- ASSERT_EFI_ERROR(Status);
-
+ if (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) { + FdtLocalSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->FdtLocalSize); +
+ if (FdtLocalSize > 0) { + FdtDevicePath = GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize + InitrdSize)); + } else { + FdtDevicePath = NULL; + } + } else { + // Get the default FDT device path + Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol); + ASSERT_EFI_ERROR(Status); + DefaultFdtDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdFdtDevicePath)); + + // Get the FDT device path + FdtDevicePathSize = GetDevicePathSize (DefaultFdtDevicePath); + Status = GetEnvironmentVariable ((CHAR16 *)L"Fdt", &gArmGlobalVariableGuid, + DefaultFdtDevicePath, &FdtDevicePathSize, (VOID **)&FdtDevicePath); + ASSERT_EFI_ERROR(Status); + FreePool (DefaultFdtDevicePath); + } Status = BdsBootLinuxFdt (BootOption->FilePathList,
Initrd, // Initrd
(CHAR8*)(LinuxArguments + 1),
@@ -159,6 +170,7 @@ BootOptionSetFields ( UINT16 FilePathListLength;
UINT8* EfiLoadOptionPtr;
UINT8* InitrdPathListPtr;
+ UINT8* FdtLocalPathListPtr; UINTN OptionalDataSize;
ARM_BDS_LINUX_ARGUMENTS* DestLinuxArguments;
ARM_BDS_LINUX_ARGUMENTS* SrcLinuxArguments;
@@ -170,8 +182,8 @@ BootOptionSetFields ( BootDescriptionSize = StrSize (BootDescription);
BootOptionalDataSize = sizeof(ARM_BDS_LOADER_OPTIONAL_DATA_HEADER);
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
- BootOptionalDataSize += sizeof(ARM_BDS_LINUX_ARGUMENTS) + BootArguments->LinuxArguments.CmdLineSize + BootArguments->LinuxArguments.InitrdSize;
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { + BootOptionalDataSize += sizeof(ARM_BDS_LINUX_ARGUMENTS) + BootArguments->LinuxArguments.CmdLineSize + BootArguments->LinuxArguments.InitrdSize + BootArguments->LinuxArguments.FdtLocalSize; }
// Compute the size of the FilePath list
@@ -213,12 +225,13 @@ BootOptionSetFields ( OptionalDataSize = sizeof(ARM_BDS_LOADER_OPTIONAL_DATA_HEADER);
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) { SrcLinuxArguments = &(BootArguments->LinuxArguments);
DestLinuxArguments = &((ARM_BDS_LOADER_OPTIONAL_DATA*)EfiLoadOptionPtr)->Arguments.LinuxArguments;
WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->CmdLineSize), SrcLinuxArguments->CmdLineSize);
WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->InitrdSize), SrcLinuxArguments->InitrdSize);
+ WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->FdtLocalSize), SrcLinuxArguments->FdtLocalSize); OptionalDataSize += sizeof (ARM_BDS_LINUX_ARGUMENTS);
if (SrcLinuxArguments->CmdLineSize > 0) {
@@ -230,6 +243,11 @@ BootOptionSetFields ( InitrdPathListPtr = (UINT8*)((UINTN)(DestLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize);
CopyMem (InitrdPathListPtr, (VOID*)((UINTN)(SrcLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize), SrcLinuxArguments->InitrdSize);
}
+ + if (SrcLinuxArguments->FdtLocalSize > 0) { + FdtLocalPathListPtr = (UINT8*)((UINTN)(DestLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize + SrcLinuxArguments->InitrdSize); + CopyMem (FdtLocalPathListPtr, (VOID*)((UINTN)(SrcLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize + SrcLinuxArguments->InitrdSize), SrcLinuxArguments->FdtLocalSize); + } }
BootOption->OptionalDataSize = OptionalDataSize;
diff --git a/ArmPlatformPkg/Bds/BootOptionSupport.c b/ArmPlatformPkg/Bds/BootOptionSupport.c index 190169a30..bfb31187a 100644 --- a/ArmPlatformPkg/Bds/BootOptionSupport.c +++ b/ArmPlatformPkg/Bds/BootOptionSupport.c @@ -25,6 +25,7 @@ #include <Guid/FileSystemInfo.h>
#define IS_DEVICE_PATH_NODE(node,type,subtype) (((node)->Type == (type)) && ((node)->SubType == (subtype)))
+#define LOCAL_FDT_RESPONSE_LEN 2 // 1 character, plus carriage return EFI_STATUS
BdsLoadOptionFileSystemList (
@@ -233,7 +234,7 @@ BootDeviceGetType ( EFI_STATUS Status;
BOOLEAN IsEfiApp;
BOOLEAN IsBootLoader;
- BOOLEAN HasFDTSupport;
+ CHAR16 FDTType[ LOCAL_FDT_RESPONSE_LEN ]; if (FileName == NULL) {
Print(L"Is an EFI Application? ");
@@ -258,15 +259,19 @@ BootDeviceGetType ( }
*BootType = BDS_LOADER_EFI_APPLICATION;
} else {
- Print(L"Has FDT support? ");
- Status = GetHIInputBoolean (&HasFDTSupport);
+ Print(L"Boot Type: [a] ATAGS, [g] Global FDT or [l] Local FDT? [a/g/l] "); + Status = GetHIInputStr (FDTType, LOCAL_FDT_RESPONSE_LEN ); if (EFI_ERROR(Status)) {
return EFI_ABORTED;
}
- if (HasFDTSupport) {
- *BootType = BDS_LOADER_KERNEL_LINUX_FDT;
- } else {
+ if (StrCmp(FDTType, L"g") == 0) { + *BootType = BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT; + } else if (StrCmp(FDTType, L"l") == 0) { + *BootType = BDS_LOADER_KERNEL_LINUX_LOCAL_FDT; + } else if (StrCmp(FDTType, L"a") == 0) { *BootType = BDS_LOADER_KERNEL_LINUX_ATAG;
+ } else { + return EFI_ABORTED; }
}
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