3 files changed, 52 insertions, 8 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S
index b560f56c5..ac5378a62 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S
@@ -22,6 +22,7 @@
 GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
 GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
 
 ASM_PFX(ArmPlatformPeiBootAction):
   bx    lr
@@ -66,3 +67,23 @@ ASM_PFX(ArmPlatformIsPrimaryCore):
   movne r0, #0
   bx    lr
 
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+  // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
+  // with cpu_id[0:3] and cluster_id[4:7]
+  LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0)
+  ldr   r0, [r0]
+  lsr   r0, #24
+
+  // Shift the SCC value to get the cluster ID at the offset #8
+  lsl   r1, r0, #4
+  and   r1, r1, #0xF00
+
+  // Keep only the cpu ID from the original SCC
+  and   r0, r0, #0x0F
+  // Add the Cluster ID to the Cpu ID
+  orr   r0, r0, r1
+  bx    lr
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm
index ec2093adc..2e323a1dd 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm
@@ -21,6 +21,7 @@
   EXPORT  ArmPlatformPeiBootAction
   EXPORT  ArmPlatformGetCorePosition
   EXPORT  ArmPlatformIsPrimaryCore
+  EXPORT  ArmPlatformGetPrimaryCoreMpId
 
   PRESERVE8
   AREA    CTA15A7Helper, CODE, READONLY
@@ -71,4 +72,26 @@ ArmPlatformIsPrimaryCore FUNCTION
   bx    lr
   ENDFUNC
 
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ArmPlatformGetPrimaryCoreMpId FUNCTION
+  // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
+  // with cpu_id[0:3] and cluster_id[4:7]
+  LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0)
+  ldr   r0, [r0]
+  lsr   r0, #24
+
+  // Shift the SCC value to get the cluster ID at the offset #8
+  lsl   r1, r0, #4
+  and   r1, r1, #0xF00
+
+  // Keep only the cpu ID from the original SCC
+  and   r0, r0, #0x0F
+  // Add the Cluster ID to the Cpu ID
+  orr   r0, r0, r1
+  bx    lr
+  ENDFUNC
+
   END
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
index 473b3f323..e633c8937 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
@@ -136,18 +136,18 @@ ArmPlatformGetVirtualMemoryMap (
 
 #ifndef ARM_BIGLITTLE_TC2
   // Workaround for SRAM bug in RTSM
-  if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
+  if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {
     VirtualMemoryTable[++Index].PhysicalBase  = 0x80000000;
     VirtualMemoryTable[Index].VirtualBase     = 0x80000000;
-    VirtualMemoryTable[Index].Length          = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
+    VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;
     VirtualMemoryTable[Index].Attributes      = CacheAttributes;
   }
 #endif
 
   // DDR
-  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdSystemMemoryBase);
-  VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdSystemMemoryBase);
-  VirtualMemoryTable[Index].Length          = PcdGet32 (PcdSystemMemorySize);
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
   VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 
   // Detect if it is a 1GB or 2GB Test Chip
@@ -159,13 +159,13 @@ ArmPlatformGetVirtualMemoryMap (
         EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
           EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
           EFI_RESOURCE_ATTRIBUTE_TESTED,
-        PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
+        PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),
         SIZE_1GB
     );
 
     // Map the additional 1GB into the MMU
-    VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
-    VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
+    VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
+    VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
     VirtualMemoryTable[Index].Length          = SIZE_1GB;
     VirtualMemoryTable[Index].Attributes      = CacheAttributes;
   }