diff options
| author | jljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-06-19 06:08:07 +0000 |
|---|---|---|
| committer | jljusten <jljusten@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-06-19 06:08:07 +0000 |
| commit | 64ed5935e91b10e6230927cf2ed98a9046b295b0 (patch) | |
| tree | 0c6fd6db1254e7bde232b2aea0b56ac1ae78661f /edk2/PcAtChipsetPkg | |
| parent | 03e4b0cea6f91b6d05e533ddc25eca64da6983e6 (diff) | |
PcAtChipsetPkg PciHostBridgeDxe: Fix build warning with GCC
Add default case to switch blocks to remove GCC compiler warning.
The default case code path should never be taken.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk@10592 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'edk2/PcAtChipsetPkg')
| -rw-r--r-- | edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c index edbe4a03b..a33836569 100644 --- a/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/edk2/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -914,6 +914,13 @@ RootBridgeIoMemRW ( case EfiPciWidthUint64:
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
} else {
switch (OperationWidth) {
@@ -929,6 +936,13 @@ RootBridgeIoMemRW ( case EfiPciWidthUint64:
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
}
}
@@ -989,6 +1003,13 @@ RootBridgeIoIoRW ( case EfiPciWidthUint32:
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
} else {
switch (OperationWidth) {
@@ -1001,6 +1022,13 @@ RootBridgeIoIoRW ( case EfiPciWidthUint32:
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
}
}
@@ -1074,6 +1102,13 @@ RootBridgeIoPciRW ( case EfiPciWidthUint32:
PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
} else {
switch (OperationWidth) {
@@ -1086,6 +1121,13 @@ RootBridgeIoPciRW ( case EfiPciWidthUint32:
*((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);
break;
+ default:
+ //
+ // The RootBridgeIoCheckParameter call above will ensure that this
+ // path is not taken.
+ //
+ ASSERT (FALSE);
+ break;
}
}
}
|