diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2013-09-18 19:14:27 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2013-09-18 19:14:27 +0100 |
| commit | 2e484bf1d9e22c8910d0bf8def69412f971b63db (patch) | |
| tree | f45ef79c17be30c7339b72b3db1cebc5ccedff30 /SamsungPlatformPkgOrigen/SmdkBoardPkg | |
| parent | 7f1515b0da8d1595fe2e6c1bca947abe8b7d8328 (diff) | |
| parent | b0b916298304830d940d43202bea6ccd7350f490 (diff) | |
Merge branch 'linaro-topic-origen' into linaro-tracking-2013.09
Diffstat (limited to 'SamsungPlatformPkgOrigen/SmdkBoardPkg')
28 files changed, 5021 insertions, 0 deletions
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/AcpiTables.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000..a40aac687 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/AcpiTables.inf @@ -0,0 +1,37 @@ +## @file +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD +# License which accompanies this distribution. The full text of the license +# may be found at http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 +# +# The following information is for reference only and not required by the +# build tools. +# +# VALID_ARCHITECTURES = +# + +[Sources] + Platform.h + Madt.aslc + Facp.aslc + Facs.aslc + Dsdt.asl +[Packages] + MdePkg/MdePkg.dec diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Dsdt.asl b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Dsdt.asl new file mode 100644 index 000000000..ca2b17275 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Dsdt.asl @@ -0,0 +1,446 @@ +/** @file + Contains root level name space objects for the platform + + Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ("Dsdt.aml", "DSDT", 1, "EXYNOS", "4210 ", 3) { + // + // System Sleep States + // + Name (\_S0, Package () {5, 0, 0, 0}) + Name (\_S4, Package () {1, 0, 0, 0}) + Name (\_S5, Package () {0, 0, 0, 0}) + + // + // System Bus + // + Scope (\_SB) { + // + // PCI Root Bridge + // + Device (PCI0) { + Name (_HID, EISAID ("PNP0A03")) + Name (_ADR, 0x00000000) + Name (_BBN, 0x00) + Name (_UID, 0x00) + + // + // BUS, I/O, and MMIO resources + // + Name (_CRS, ResourceTemplate () { + // Bus number resource (0); the bridge produces bus numbers for its + // subsequent buses + WORDBusNumber ( + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x00FF, // Max + 0x0000, // Translation + 0x0100 // Range Length = Max-Min+1 + ) + + //Consumed resource (0xCF8-0xCFF) + IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) + + // Consumed-and-produced resource (all I/O below CF8) + WORDIO ( + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x0CF7, // Max + 0x0000, // Translation + 0x0CF8 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource + // (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0D00, // Min + 0xFFFF, // Max + 0x0000, // Translation + 0xF300 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy VGA video RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Min + 0x000BFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for linear frame buffer video RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0xF8000000, // Min + 0xFFFBFFFF, // Max + 0x00000000, // Translation + 0x07FC0000 // Range Length + ) + }) + + // + // PCI Interrupt Routing Table - PIC Mode Only + // + Method (_PRT, 0, NotSerialized) { + Return ( + Package () { + // + // Bus 0, Device 1 + // + Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00}, + Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00}, + Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00}, + Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00}, + // + // Bus 0, Device 3 + // + Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00}, + Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00}, + Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00}, + Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00}, + } + ) + } + + // + // PCI to ISA Bridge (Bus 0, Device 1, Function 0) + // + Device (LPC) { + Name (_ADR, 0x00010000) + + // + // PCI Interrupt Routing Configuration Registers + // + OperationRegion (PRR0, PCI_Config, 0x60, 0x04) + Field (PRR0, ANYACC, NOLOCK, PRESERVE) { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } + + // + // _STA method for LNKA, LNKB, LNKC, LNKD + // + Method (PSTA, 1, NotSerialized) { + If (And (Arg0, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } + } + + // + // _DIS method for LNKA, LNKB, LNKC, LNKD + // + Method (PDIS, 1, NotSerialized) { + Or (Arg0, 0x80, Arg0) + } + + // + // _CRS method for LNKA, LNKB, LNKC, LNKD + // + Method (PCRS, 1, NotSerialized) { + Name (BUF0, ResourceTemplate () {IRQ (Level, ActiveLow, Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (Arg0, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70 + // + ShiftLeft (Local0, And (Arg0, 0x0F), IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } + + // + // _PRS resource for LNKA, LNKB, LNKC, LNKD + // + Name (PPRS, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3, 4, 5, 7, 9, 10, 11, 12, 14, 15} + }) + + // + // _SRS method for LNKA, LNKB, LNKC, LNKD + // + Method (PSRS, 2, NotSerialized) { + CreateWordField (Arg1, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0) // Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, Arg0) + } + + // + // PCI IRQ Link A + // + Device (LNKA) { + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) } + Method (_DIS, 0, NotSerialized) { PDIS (PIRA) } + Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) } + Method (_PRS, 0, NotSerialized) { Return (PPRS) } + Method (_SRS, 1, NotSerialized) { PSRS (PIRA, Arg0) } + } + + // + // PCI IRQ Link B + // + Device (LNKB) { + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) } + Method (_DIS, 0, NotSerialized) { PDIS (PIRB) } + Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) } + Method (_PRS, 0, NotSerialized) { Return (PPRS) } + Method (_SRS, 1, NotSerialized) { PSRS (PIRB, Arg0) } + } + + // + // PCI IRQ Link C + // + Device (LNKC) { + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) } + Method (_DIS, 0, NotSerialized) { PDIS (PIRC) } + Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) } + Method (_PRS, 0, NotSerialized) { Return (PPRS) } + Method (_SRS, 1, NotSerialized) { PSRS (PIRC, Arg0) } + } + + // + // PCI IRQ Link D + // + Device (LNKD) { + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) } + Method (_DIS, 0, NotSerialized) { PDIS (PIRD) } + Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) } + Method (_PRS, 0, NotSerialized) { Return (PPRS) } + Method (_SRS, 1, NotSerialized) { PSRS (PIRD, Arg0) } + } + + // + // Programmable Interrupt Controller (PIC) + // + Device(PIC) { + Name (_HID, EISAID ("PNP0000")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x020, 0x020, 0x00, 0x02) + IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02) + IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02) + IRQNoFlags () {2} + }) + } + + // + // ISA DMA + // + Device (DMAC) { + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x00, 0x00, 0, 0x10) + IO (Decode16, 0x81, 0x81, 0, 0x03) + IO (Decode16, 0x87, 0x87, 0, 0x01) + IO (Decode16, 0x89, 0x89, 0, 0x03) + IO (Decode16, 0x8f, 0x8f, 0, 0x01) + IO (Decode16, 0xc0, 0xc0, 0, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8) {4} + }) + } + + // + // 8254 Timer + // + Device(TMR) { + Name(_HID,EISAID("PNP0100")) + Name(_CRS, ResourceTemplate () { + IO (Decode16, 0x40, 0x40, 0x00, 0x04) + IRQNoFlags () {0} + }) + } + + // + // Real Time Clock + // + Device (RTC) { + Name (_HID, EISAID ("PNP0B00")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x70, 0x70, 0x00, 0x02) + IRQNoFlags () {8} + }) + } + + // + // PCAT Speaker + // + Device(SPKR) { + Name (_HID, EISAID("PNP0800")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x61, 0x61, 0x01, 0x01) + }) + } + + // + // Floating Point Coprocessor + // + Device(FPU) { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0xF0, 0xF0, 0x00, 0x10) + IRQNoFlags () {13} + }) + } + + // + // Generic motherboard devices and pieces that don't fit anywhere else + // + Device(XTRA) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 0x01) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x010, 0x010, 0x00, 0x10) + IO (Decode16, 0x022, 0x022, 0x00, 0x1E) + IO (Decode16, 0x044, 0x044, 0x00, 0x1C) + IO (Decode16, 0x062, 0x062, 0x00, 0x02) + IO (Decode16, 0x065, 0x065, 0x00, 0x0B) + IO (Decode16, 0x072, 0x072, 0x00, 0x0E) + IO (Decode16, 0x080, 0x080, 0x00, 0x01) + IO (Decode16, 0x084, 0x084, 0x00, 0x03) + IO (Decode16, 0x088, 0x088, 0x00, 0x01) + IO (Decode16, 0x08c, 0x08c, 0x00, 0x03) + IO (Decode16, 0x090, 0x090, 0x00, 0x10) + IO (Decode16, 0x0A2, 0x0A2, 0x00, 0x1E) + IO (Decode16, 0x0E0, 0x0E0, 0x00, 0x10) + IO (Decode16, 0x1E0, 0x1E0, 0x00, 0x10) + IO (Decode16, 0x160, 0x160, 0x00, 0x10) + IO (Decode16, 0x278, 0x278, 0x00, 0x08) + IO (Decode16, 0x370, 0x370, 0x00, 0x02) + IO (Decode16, 0x378, 0x378, 0x00, 0x08) + IO (Decode16, 0x400, 0x400, 0x00, 0x40) // PMBLK1 + IO (Decode16, 0x440, 0x440, 0x00, 0x10) + IO (Decode16, 0x678, 0x678, 0x00, 0x08) + IO (Decode16, 0x778, 0x778, 0x00, 0x08) + Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC + Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000) + }) + } + + // + // PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102 + // + Device (PS2K) { + Name (_HID, EISAID ("PNP0303")) + Name (_CID, EISAID ("PNP030B")) + Name(_CRS,ResourceTemplate() { + IO (Decode16, 0x60, 0x60, 0x00, 0x01) + IO (Decode16, 0x64, 0x64, 0x00, 0x01) + IRQNoFlags () {1} + }) + } + + // + // PS/2 Mouse and Microsoft Mouse + // + Device (PS2M) { // PS/2 stype mouse port + Name (_HID, EISAID ("PNP0F03")) + Name (_CID, EISAID ("PNP0F13")) + Name (_CRS, ResourceTemplate() { + IRQNoFlags () {12} + }) + } + + // + // UART Serial Port - COM1 + // + Device (UAR1) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM1") + Name (_UID, 0x01) + Name(_CRS,ResourceTemplate() { + IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08) + IRQ (Edge, ActiveHigh, Exclusive, ) {4} + }) + } + + // + // UART Serial Port - COM2 + // + Device (UAR2) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM2") + Name (_UID, 0x02) + Name(_CRS,ResourceTemplate() { + IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08) + IRQ (Edge, ActiveHigh, Exclusive, ) {3} + }) + } + + // + // Floppy Disk Controller + // + Device (FDC) { + Name (_HID, EISAID ("PNP0700")) + Name (_CRS,ResourceTemplate() { + IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06) + IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + } + } + } + } +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Facp.aslc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Facp.aslc new file mode 100644 index 000000000..593861eb6 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Facp.aslc @@ -0,0 +1,79 @@ +/** @file + FACP Table + + Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "Platform.h" + +EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = { + EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number + 0, // Physical addesss of FACS + 0, // Physical address of DSDT + INT_MODEL, // System Interrupt Model + RESERVED, // reserved + SCI_INT_VECTOR, // System vector of SCI interrupt + SMI_CMD_IO_PORT, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + 0xE2, // PState control + PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk + PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk + GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk + GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // offset in gpe model where gpe1 events start + 0xE3, // _CST support + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM + CENTURY, // index to century in RTC CMOS RAM + 0x03, // Boot architecture flag + 0x00, // Boot architecture flag + RESERVED, // reserved + FLAG +}; + + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the exeutable + // + return (VOID*)&FACP; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Facs.aslc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Facs.aslc new file mode 100644 index 000000000..2d2129c42 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Facs.aslc @@ -0,0 +1,81 @@ +/** @file + FACS Table + + Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = { + EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, + sizeof (EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), + + // + // Hardware Signature will be updated at runtime + // + 0x00000000, + 0x00, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE +}; + + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the exeutable + // + return (VOID*)&FACS; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Madt.aslc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Madt.aslc new file mode 100644 index 000000000..7e360dd69 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Madt.aslc @@ -0,0 +1,158 @@ +/** @file + MADT Table + + This file contains a structure definition for the ACPI 1.0 Multiple APIC + Description Table (MADT). + + Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <IndustryStandard/Acpi.h> + +// +// MADT Definitions +// +#define EFI_ACPI_OEM_MADT_REVISION 0x00000000 // TBD + +// +// Local APIC address +// +#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000 // TBD + +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 1 +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_IO_APIC_COUNT 1 + +// +// Ensure proper structure formats +// +#pragma pack (1) + +// +// ACPI 1.0 MADT structure +// +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE \ + LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE \ + Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_1_0_IO_APIC_STRUCTURE \ + IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +// +// Multiple APIC Description Table +// +EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + EFI_ACPI_1_0_APIC_SIGNATURE, + sizeof (EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE), + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be programmed at runtime + // + 'E', 'X', 'Y', 'N', 'O', 'S', + + 0x30313234, + EFI_ACPI_OEM_MADT_REVISION, + 0, + 0, + + // + // MADT specific fields + // + EFI_ACPI_LOCAL_APIC_ADDRESS, + EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS, + + // + // Processor Local APIC Structure + // + + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x01, // Processor ID + 0x00, // Local APIC ID + 0x00000001, // Flags - Enabled by default + + // + // Interrupt Source Override Structure + // + + // + // IRQ0=>IRQ2 Interrupt Source Override Structure + // + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE, // Type + sizeof (EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + 0x00, // Bus - ISA + 0x00, // Source - IRQ0 + 0x00000002, // Global System Interrupt - IRQ2 + 0x0000, // Flags - Conforms to specifications of the bus + + // + // ISO (SCI Active High) Interrupt Source Override Structure + // + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE, // Type + sizeof (EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + 0x00, // Bus - ISA + 0x09, // Source - IRQ0 + 0x00000009, // Global System Interrupt - IRQ2 + 0x000D, // Flags - Level-tiggered, Active High + + // + // IO APIC Structure + // + EFI_ACPI_1_0_IO_APIC, // Type + sizeof (EFI_ACPI_1_0_IO_APIC_STRUCTURE), // Length + 0x02, // IO APIC ID + EFI_ACPI_RESERVED_BYTE, // Reserved + 0xFEC00000, // IO APIC Address (physical) + 0x00000000 // Global System Interrupt Base +}; + + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the exeutable + // + return (VOID*)&Madt; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Platform.h b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Platform.h new file mode 100644 index 000000000..307983933 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/AcpiTables/Platform.h @@ -0,0 +1,66 @@ +/** @file + Platform specific defines for constructing ACPI tables + + Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _Platform_h_INCLUDED_ +#define _Platform_h_INCLUDED_ + +#include <PiDxe.h> +#include <IndustryStandard/Acpi.h> + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'E','X','Y','N','O','S' // OEMID 6 bytes long +// OEM table id 8 bytes long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('4','2','1','0',' ',' ',' ',' ') +#define EFI_ACPI_OEM_REVISION 0x02000820 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('S','M','D','K') +#define EFI_ACPI_CREATOR_REVISION 0x00000097 + +#define INT_MODEL 0x01 +#define SCI_INT_VECTOR 0x0009 +#define SMI_CMD_IO_PORT 0 // If SMM was supported, then this would be 0xB2 +#define ACPI_ENABLE 0x0E1 +#define ACPI_DISABLE 0x01E +#define S4BIOS_REQ 0x00 +#define PM1a_EVT_BLK 0x00000400 +#define PM1b_EVT_BLK 0x00000000 +#define PM1a_CNT_BLK 0x00000404 +#define PM1b_CNT_BLK 0x00000000 +#define PM2_CNT_BLK 0x00000022 +#define PM_TMR_BLK 0x00000408 +#define GPE0_BLK 0x0000040C +#define GPE1_BLK 0x00000000 +#define PM1_EVT_LEN 0x04 +#define PM1_CNT_LEN 0x02 +#define PM2_CNT_LEN 0x01 +#define PM_TM_LEN 0x04 +#define GPE0_BLK_LEN 0x04 +#define GPE1_BLK_LEN 0x00 +#define GPE1_BASE 0x00 +#define RESERVED 0x00 +#define P_LVL2_LAT 0x0065 +#define P_LVL3_LAT 0x03E9 +#define FLUSH_SIZE 0x0400 +#define FLUSH_STRIDE 0x0010 +#define DUTY_OFFSET 0x00 +#define DUTY_WIDTH 0x00 +#define DAY_ALRM 0x0D +#define MON_ALRM 0x00 +#define CENTURY 0x00 +#define FLAG EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | \ + EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4 | \ + EFI_ACPI_1_0_TMR_VAL_EXT + +#endif diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/EBLoadSecSyms.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/EBLoadSecSyms.inc new file mode 100644 index 000000000..281c99b4a --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/EBLoadSecSyms.inc @@ -0,0 +1,15 @@ +// returns the base address of the SEC FV in flash on the EB board +// change this address for where your platform's SEC FV is located +// (or make it more intelligent to search for it) +define /r FindFv() +{ + return 0x40000000; +} +. + +include /s 'ZZZZZZ/EfiFuncs.inc' +error=continue +unload ,all +error=abort +LoadPeiSec() +include C:\loadfiles.inc diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/EfiFuncs.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/EfiFuncs.inc new file mode 100644 index 000000000..014d09440 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/EfiFuncs.inc @@ -0,0 +1,463 @@ +error=abort + +// NOTE: THIS MAY NEED TO BE ADJUSTED +// change to reflect the total amount of ram in your system +define /r GetMaxMem() +{ + return 0x10000000; // 256 MB +} +. + +define /r GetWord(Addr) +{ + unsigned long data; + + if( (Addr & 0x2) == 0 ) + { + data = dword(Addr); + data = data & 0xffff; + //$printf "getword data is %x\n", data$; + return data; + } + else + { + data = dword(Addr & 0xfffffffc); + //data = data >> 16; + data = data / 0x10000; + //$printf "getword data is %x (1)\n", data$; + return data; + } +} +. + +define /r ProcessPE32(imgstart) +unsigned long imgstart; +{ + unsigned long filehdrstart; + unsigned long debugdirentryrva; + unsigned long debugtype; + unsigned long debugrva; + unsigned long dwarfsig; + unsigned long baseofcode; + unsigned long baseofdata; + unsigned long elfbase; + char *elfpath; + + $printf "PE32 image found at %x",imgstart$; + + //$printf "PE file hdr offset %x",dword(imgstart+0x3C)$; + + // offset from dos hdr to PE file hdr + filehdrstart = imgstart + dword(imgstart+0x3C); + + // offset to debug dir in PE hdrs + //$printf "debug dir is at %x",(filehdrstart+0xA8)$; + debugdirentryrva = dword(filehdrstart + 0xA8); + if(debugdirentryrva == 0) + { + $printf "no debug dir for image at %x",imgstart$; + return; + } + + //$printf "debug dir entry rva is %x",debugdirentryrva$; + + debugtype = dword(imgstart + debugdirentryrva + 0xc); + if( (debugtype != 0xdf) && (debugtype != 0x2) ) + { + $printf "debug type is not dwarf for image at %x",imgstart$; + $printf "debug type is %x",debugtype$; + return; + } + + debugrva = dword(imgstart + debugdirentryrva + 0x14); + dwarfsig = dword(imgstart + debugrva); + if(dwarfsig != 0x66727764) + { + $printf "dwarf debug signature not found for image at %x",imgstart$; + return; + } + + elfpath = (char *)(imgstart + debugrva + 0xc); + + baseofcode = imgstart + dword(filehdrstart + 0x28); + baseofdata = imgstart + dword(filehdrstart + 0x2c); + + if( (baseofcode < baseofdata) && (baseofcode != 0) ) + { + elfbase = baseofcode; + } + else + { + elfbase = baseofdata; + } + + $printf "found path %s",elfpath$; + $fprintf 50, "load /ni /np /a %s &0x%x\n",elfpath,elfbase$; +} +. + +define /r ProcessTE(imgstart) +unsigned long imgstart; +{ + unsigned long strippedsize; + unsigned long debugdirentryrva; + unsigned long debugtype; + unsigned long debugrva; + unsigned long dwarfsig; + unsigned long elfbase; + char *elfpath; + + $printf "TE image found at %x",imgstart$; + + // determine pe header bytes removed to account for in rva references + //strippedsize = word(imgstart + 0x6); + //strippedsize = (dword(imgstart + 0x4) & 0xffff0000) >> 16; + strippedsize = (dword(imgstart + 0x4) & 0xffff0000) / 0x10000; + strippedsize = strippedsize - 0x28; + + debugdirentryrva = dword(imgstart + 0x20); + if(debugdirentryrva == 0) + { + $printf "no debug dir for image at %x",imgstart$; + return; + } + debugdirentryrva = debugdirentryrva - strippedsize; + + //$printf "debug dir entry rva is %x",debugdirentryrva$; + + debugtype = dword(imgstart + debugdirentryrva + 0xc); + if( (debugtype != 0xdf) && (debugtype != 0x2) ) + { + $printf "debug type is not dwarf for image at %x",imgstart$; + $printf "debug type is %x",debugtype$; + return; + } + + debugrva = dword(imgstart + debugdirentryrva + 0x14); + debugrva = debugrva - strippedsize; + dwarfsig = dword(imgstart + debugrva); + if( (dwarfsig != 0x66727764) && (dwarfsig != 0x3031424e) ) + { + $printf "dwarf debug signature not found for image at %x",imgstart$; + $printf "found %x", dwarfsig$; + return; + } + + if( dwarfsig == 0x66727764 ) + { + elfpath = (char *)(imgstart + debugrva + 0xc); + $printf "looking for elf path at 0x%x", elfpath$; + } + else + { + elfpath = (char *)(imgstart + debugrva + 0x10); + $printf "looking for elf path at 0x%x", elfpath$; + } + + // elf base is baseofcode (we hope that for TE images it's not baseofdata) + elfbase = imgstart + dword(imgstart + 0xc) - strippedsize; + + $printf "found path %s",elfpath$; + $fprintf 50, "load /ni /np /a %s &0x%x\n",elfpath,elfbase$; +} +. + +define /r ProcessFvSection(secstart) +unsigned long secstart; +{ + unsigned long sectionsize; + unsigned char sectiontype; + + sectionsize = dword(secstart); + //sectiontype = (sectionsize & 0xff000000) >> 24; + sectiontype = (sectionsize & 0xff000000) / 0x1000000; + sectionsize = sectionsize & 0x00ffffff; + + $printf "fv section at %x size %x type %x",secstart,sectionsize,sectiontype$; + + if(sectiontype == 0x10) // PE32 + { + ProcessPE32(secstart+0x4); + } + else if(sectiontype == 0x12) // TE + { + ProcessTE(secstart+0x4); + } +} +. + +define /r ProcessFfsFile(ffsfilestart) +unsigned long ffsfilestart; +{ + unsigned long ffsfilesize; + unsigned long ffsfiletype; + unsigned long secoffset; + unsigned long secsize; + + //ffsfiletype = byte(ffsfilestart + 0x12); + ffsfilesize = dword(ffsfilestart + 0x14); + //ffsfiletype = (ffsfilesize & 0xff000000) >> 24; + ffsfiletype = (ffsfilesize & 0xff000000) / 0x1000000; + ffsfilesize = ffsfilesize & 0x00ffffff; + + if(ffsfiletype == 0xff) return; + + $printf "ffs file at %x size %x type %x",ffsfilestart,ffsfilesize,ffsfiletype$; + + secoffset = ffsfilestart + 0x18; + + // loop through sections in file + while(secoffset < (ffsfilestart + ffsfilesize)) + { + // process fv section and increment section offset by size + secsize = dword(secoffset) & 0x00ffffff; + ProcessFvSection(secoffset); + secoffset = secoffset + secsize; + + // align to next 4 byte boundary + if( (secoffset & 0x3) != 0 ) + { + secoffset = secoffset + (0x4 - (secoffset & 0x3)); + } + } // end section loop +} +. + +define /r LoadPeiSec() +{ + unsigned long fvbase; + unsigned long fvlen; + unsigned long fvsig; + unsigned long ffsoffset; + unsigned long ffsfilesize; + + fvbase = FindFv(); + $printf "fvbase %x",fvbase$; + + // get fv signature field + fvsig = dword(fvbase + 0x28); + if(fvsig != 0x4856465F) + { + $printf "FV does not have proper signature, exiting"$; + return 0; + } + + $printf "FV signature found"$; + + $fopen 50, 'C:\loadfiles.inc'$; + + fvlen = dword(fvbase + 0x20); + + // first ffs file is after fv header, use headerlength field + //ffsoffset = (dword(fvbase + 0x30) & 0xffff0000) >> 16; + ffsoffset = (dword(fvbase + 0x30) & 0xffff0000) / 0x10000; + ffsoffset = fvbase + GetWord(fvbase + 0x30); + + // loop through ffs files + while(ffsoffset < (fvbase+fvlen)) + { + // process ffs file and increment by ffs file size field + ProcessFfsFile(ffsoffset); + ffsfilesize = (dword(ffsoffset + 0x14) & 0x00ffffff); + if(ffsfilesize == 0) + { + break; + } + ffsoffset = ffsoffset + ffsfilesize; + + + // align to next 8 byte boundary + if( (ffsoffset & 0x7) != 0 ) + { + ffsoffset = ffsoffset + (0x8 - (ffsoffset & 0x7)); + } + + } // end fv ffs loop + + $vclose 50$; + +} +. + +define /r FindSystemTable(TopOfRam) +unsigned long TopOfRam; +{ + unsigned long offset; + + $printf "FindSystemTable"$; + $printf "top of mem is %x",TopOfRam$; + + offset = TopOfRam; + + // align to highest 4MB boundary + offset = offset & 0xFFC00000; + + // start at top and look on 4MB boundaries for system table ptr structure + while(offset > 0) + { + //$printf "checking %x",offset$; + //$printf "value is %x",dword(offset)$; + + // low signature match + if(dword(offset) == 0x20494249) + { + // high signature match + if(dword(offset+4) == 0x54535953) + { + // less than 4GB? + if(dword(offset+0x0c) == 0) + { + // less than top of ram? + if(dword(offset+8) < TopOfRam) + { + return(dword(offset+8)); + } + } + } + + } + + if(offset < 0x400000) break; + offset = offset - 0x400000; + } + + return 0; +} +. + +define /r ProcessImage(ImageBase) +unsigned long ImageBase; +{ + $printf "ProcessImage %x", ImageBase$; +} +. + +define /r FindDebugInfo(SystemTable) +unsigned long SystemTable; +{ + unsigned long CfgTableEntries; + unsigned long ConfigTable; + unsigned long i; + unsigned long offset; + unsigned long dbghdr; + unsigned long dbgentries; + unsigned long dbgptr; + unsigned long dbginfo; + unsigned long loadedimg; + + $printf "FindDebugInfo"$; + + dbgentries = 0; + CfgTableEntries = dword(SystemTable + 0x40); + ConfigTable = dword(SystemTable + 0x44); + + $printf "config table is at %x (%d entries)", ConfigTable, CfgTableEntries$; + + // now search for debug info entry with guid 49152E77-1ADA-4764-B7A2-7AFEFED95E8B + // 0x49152E77 0x47641ADA 0xFE7AA2B7 0x8B5ED9FE + for(i=0; i<CfgTableEntries; i++) + { + offset = ConfigTable + (i*0x14); + if(dword(offset) == 0x49152E77) + { + if(dword(offset+4) == 0x47641ADA) + { + if(dword(offset+8) == 0xFE7AA2B7) + { + if(dword(offset+0xc) == 0x8B5ED9FE) + { + dbghdr = dword(offset+0x10); + dbgentries = dword(dbghdr + 4); + dbgptr = dword(dbghdr + 8); + } + } + } + } + } + + if(dbgentries == 0) + { + $printf "no debug entries found"$; + return; + } + + $printf "debug table at %x (%d entries)", dbgptr, dbgentries$; + + for(i=0; i<dbgentries; i++) + { + dbginfo = dword(dbgptr + (i*4)); + if(dbginfo != 0) + { + if(dword(dbginfo) == 1) // normal debug info type + { + loadedimg = dword(dbginfo + 4); + ProcessPE32(dword(loadedimg + 0x20)); + } + } + } +} +. + +define /r LoadDxe() +{ + unsigned long maxmem; + unsigned long systbl; + + $printf "LoadDxe"$; + + $fopen 50, 'C:\loadfiles.inc'$; + + maxmem = GetMaxMem(); + systbl = FindSystemTable(maxmem); + if(systbl != 0) + { + $printf "found system table at %x",systbl$; + FindDebugInfo(systbl); + } + + $vclose 50$; +} +. + +define /r LoadRuntimeDxe() + +{ + unsigned long maxmem; + unsigned long SystemTable; + unsigned long CfgTableEntries; + unsigned long ConfigTable; + unsigned long i; + unsigned long offset; + unsigned long numentries; + unsigned long RuntimeDebugInfo; + unsigned long DebugInfoOffset; + unsigned long imgbase; + + $printf "LoadRuntimeDxe"$; + + $fopen 50, 'C:\loadfiles.inc'$; + + RuntimeDebugInfo = 0x80000010; + + if(RuntimeDebugInfo != 0) + { + numentries = dword(RuntimeDebugInfo); + + $printf "runtime debug info is at %x (%d entries)", RuntimeDebugInfo, numentries$; + + DebugInfoOffset = RuntimeDebugInfo + 0x4; + for(i=0; i<numentries; i++) + { + imgbase = dword(DebugInfoOffset); + if(imgbase != 0) + { + $printf "found image at %x",imgbase$; + ProcessPE32(imgbase); + } + DebugInfoOffset = DebugInfoOffset + 0x4; + } + } + + $vclose 50$; +} +. diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc new file mode 100644 index 000000000..cd273a423 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc @@ -0,0 +1,20 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +error = continue +unload +error = abort + +setreg @CP15_CONTROL = 0x0005107E +setreg @pc=0x80008208 +setreg @cpsr=0x000000D3 +dis/D +readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000 diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_convert_symbols.sh b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_convert_symbols.sh new file mode 100644 index 000000000..46dd65cf3 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_convert_symbols.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http:#opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + + +IN=`/usr/bin/cygpath -u $1` +OUT=`/usr/bin/cygpath -u $2` + +/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \ + -e 's:\\:/:g' \ + -e "s/^/load\/a\/ni\/np \"/g" \ + -e "s/dll /dll\" \&/g" \ + $IN | /usr/bin/sort.exe --key=3 --output=$OUT diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_hw_setup.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_hw_setup.inc new file mode 100644 index 000000000..c03a443e8 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_hw_setup.inc @@ -0,0 +1,67 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +error = continue +unload +error = abort + +setreg @CP15_CONTROL = 0x0005107E +setreg @cpsr=0x000000D3 + +; General clock settings. +setmem /32 0x48307270=0x00000080 +setmem /32 0x48306D40=0x00000003 +setmem /32 0x48005140=0x03020A50 + +;Clock configuration +setmem /32 0x48004A40=0x0000030A +setmem /32 0x48004C40=0x00000015 + +;DPLL3 (Core) settings +setmem /32 0x48004D00=0x00370037 +setmem /32 0x48004D30=0x00000000 +setmem /32 0x48004D40=0x094C0C00 + +;DPLL4 (Peripheral) settings +setmem /32 0x48004D00=0x00370037 +setmem /32 0x48004D30=0x00000000 +setmem /32 0x48004D44=0x0001B00C +setmem /32 0x48004D48=0x00000009 + +;DPLL1 (MPU) settings +setmem /32 0x48004904=0x00000037 +setmem /32 0x48004934=0x00000000 +setmem /32 0x48004940=0x0011F40C +setmem /32 0x48004944=0x00000001 +setmem /32 0x48004948=0x00000000 + +;RAM setup. +setmem /16 0x6D000010=0x0000 +setmem /16 0x6D000040=0x0001 +setmem /16 0x6D000044=0x0100 +setmem /16 0x6D000048=0x0000 +setmem /32 0x6D000060=0x0000000A +setmem /32 0x6D000070=0x00000081 +setmem /16 0x6D000040=0x0003 +setmem /32 0x6D000080=0x02D04011 +setmem /16 0x6D000084=0x0032 +setmem /16 0x6D00008C=0x0000 +setmem /32 0x6D00009C=0xBA9DC4C6 +setmem /32 0x6D0000A0=0x00012522 +setmem /32 0x6D0000A4=0x0004E201 +setmem /16 0x6D000040=0x0003 +setmem /32 0x6D0000B0=0x02D04011 +setmem /16 0x6D0000B4=0x0032 +setmem /16 0x6D0000BC=0x0000 +setmem /32 0x6D0000C4=0xBA9DC4C6 +setmem /32 0x6D0000C8=0x00012522 +setmem /32 0x6D0000D4=0x0004E201
\ No newline at end of file diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_load_symbols.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_load_symbols.inc new file mode 100644 index 000000000..a8f98433d --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_load_symbols.inc @@ -0,0 +1,21 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +include 'ZZZZZZ/rvi_symbols_macros.inc' + +macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000) + +host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc" +include 'ZZZZZZ/rvi_symbols.inc' +load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata +unload rvi_dummy.axf +delfile rvi_dummy.axf diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_symbols_macros.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_symbols_macros.inc new file mode 100644 index 000000000..6f7377cbb --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_symbols_macros.inc @@ -0,0 +1,193 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +define /R int compare_guid(guid1, guid2) + unsigned char *guid1; + unsigned char *guid2; +{ + return strncmp(guid1, guid2, 16); +} +. + +define /R unsigned char * find_system_table(mem_start, mem_size) + unsigned char *mem_start; + unsigned long mem_size; +{ + unsigned char *mem_ptr; + + mem_ptr = mem_start + mem_size; + + do + { + mem_ptr -= 0x400000; // 4 MB + + if (strncmp(mem_ptr, "IBI SYST", 8) == 0) + { + return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase + } + + } while (mem_ptr > mem_start); + + return 0; +} +. + +define /R unsigned char * find_debug_info_table_header(system_table) + unsigned char *system_table; +{ + unsigned long configuration_table_entries; + unsigned char *configuration_table; + unsigned long index; + unsigned char debug_table_guid[16]; + + // Fill in the debug table's guid + debug_table_guid[ 0] = 0x77; + debug_table_guid[ 1] = 0x2E; + debug_table_guid[ 2] = 0x15; + debug_table_guid[ 3] = 0x49; + debug_table_guid[ 4] = 0xDA; + debug_table_guid[ 5] = 0x1A; + debug_table_guid[ 6] = 0x64; + debug_table_guid[ 7] = 0x47; + debug_table_guid[ 8] = 0xB7; + debug_table_guid[ 9] = 0xA2; + debug_table_guid[10] = 0x7A; + debug_table_guid[11] = 0xFE; + debug_table_guid[12] = 0xFE; + debug_table_guid[13] = 0xD9; + debug_table_guid[14] = 0x5E; + debug_table_guid[15] = 0x8B; + + configuration_table_entries = *(unsigned long *)(system_table + 64); + configuration_table = *(unsigned long *)(system_table + 68); + + for (index = 0; index < configuration_table_entries; index++) + { + if (compare_guid(configuration_table, debug_table_guid) == 0) + { + return *(unsigned long *)(configuration_table + 16); + } + + configuration_table += 20; + } + + return 0; +} +. + +define /R int valid_pe_header(header) + unsigned char *header; +{ + if ((header[0x00] == 'M') && + (header[0x01] == 'Z') && + (header[0x80] == 'P') && + (header[0x81] == 'E')) + { + return 1; + } + + return 0; +} +. + +define /R unsigned long pe_headersize(header) + unsigned char *header; +{ + unsigned long *size; + + size = header + 0x00AC; + + return *size; +} +. + +define /R unsigned char *pe_filename(header) + unsigned char *header; +{ + unsigned long *debugOffset; + unsigned char *stringOffset; + + if (valid_pe_header(header)) + { + debugOffset = header + 0x0128; + stringOffset = header + *debugOffset + 0x002C; + + return stringOffset; + } + + return 0; +} +. + +define /R int char_is_valid(c) + unsigned char c; +{ + if (c >= 32 && c < 127) + return 1; + + return 0; +} +. + +define /R write_symbols_file(filename, mem_start, mem_size) + unsigned char *filename; + unsigned char *mem_start; + unsigned long mem_size; +{ + unsigned char *system_table; + unsigned char *debug_info_table_header; + unsigned char *debug_info_table; + unsigned long debug_info_table_size; + unsigned long index; + unsigned char *debug_image_info; + unsigned char *loaded_image_protocol; + unsigned char *image_base; + unsigned char *debug_filename; + unsigned long header_size; + int status; + + system_table = find_system_table(mem_start, mem_size); + if (system_table == 0) + { + return; + } + + status = fopen(88, filename, "w"); + + debug_info_table_header = find_debug_info_table_header(system_table); + + debug_info_table = *(unsigned long *)(debug_info_table_header + 8); + debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4); + + for (index = 0; index < (debug_info_table_size * 4); index += 4) + { + debug_image_info = *(unsigned long *)(debug_info_table + index); + + if (debug_image_info == 0) + { + break; + } + + loaded_image_protocol = *(unsigned long *)(debug_image_info + 4); + + image_base = *(unsigned long *)(loaded_image_protocol + 32); + + debug_filename = pe_filename(image_base); + header_size = pe_headersize(image_base); + + $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$; + } + + + fclose(88); +} +. diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_unload_symbols.inc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_unload_symbols.inc new file mode 100644 index 000000000..4a7e12b81 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Debugger_scripts/rvi_unload_symbols.inc @@ -0,0 +1,118 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +error = continue + +unload + +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 + +error = abort diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.c new file mode 100644 index 000000000..2e13d1a42 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.c @@ -0,0 +1,414 @@ +/*++ +RealView EB FVB DXE Driver + +Copyright (c) 2010, Apple Inc. All rights reserved.<BR> +This program and the accompanying materials +are licensed and made available under the terms and conditions of the +BSD License which accompanies this distribution. The full text of the +license may be found at http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +#include <PiDxe.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> + +#include <Protocol/FirmwareVolumeBlock.h> + + + +/** + The GetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the + attributes and current settings are + returned. Type EFI_FVB_ATTRIBUTES_2 is defined + in EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were + returned. + +**/ + +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + The SetAttributes() function sets configurable firmware volume + attributes and returns the new settings of the firmware volume. + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Attributes On input, Attributes is a pointer to + EFI_FVB_ATTRIBUTES_2 that contains the + desired firmware volume settings. On + successful return, it contains the new + settings of the firmware volume. Type + EFI_FVB_ATTRIBUTES_2 is defined in + EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in + conflict with the capabilities + as declared in the firmware + volume header. + +**/ +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + The GetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. + +**/ +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + The GetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The GetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba Indicates the block for which to return the size. + + @param BlockSize Pointer to a caller-allocated UINTN in which + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + +**/ +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + return EFI_UNSUPPORTED; +} + + + +/** + Reads the specified number of bytes into a buffer from the specified block. + + The Read() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + Implementations should be mindful that the firmware volume + might be in the ReadDisabled state. If it is in this state, + the Read() function must return the status code + EFI_ACCESS_DENIED without modifying the contents of the + buffer. The Read() function must also prevent spanning block + boundaries. If a read is requested that would span a block + boundary, the read must read up to the boundary but not + beyond. The output parameter NumBytes must be set to correctly + indicate the number of bytes actually read. The caller must be + aware that a read may be partially completed. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index + from which to read. + + @param Offset Offset into the block at which to begin reading. + + @param NumBytes Pointer to a UINTN. At entry, *NumBytes + contains the total size of the buffer. At + exit, *NumBytes contains the total number of + bytes read. + + @param Buffer Pointer to a caller-allocated buffer that will + be used to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, + and contents are in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA + boundary. On output, NumBytes + contains the total number of bytes + returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the + ReadDisabled state. + + @retval EFI_DEVICE_ERROR The block device is not + functioning correctly and could + not be read. + +**/ +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Writes the specified number of bytes from the input buffer to the block. + + The Write() function writes the specified number of bytes from + the provided buffer to the specified block and offset. If the + firmware volume is sticky write, the caller must ensure that + all the bits of the specified range to write are in the + EFI_FVB_ERASE_POLARITY state before calling the Write() + function, or else the result will be unpredictable. This + unpredictability arises because, for a sticky-write firmware + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY + state but cannot flip it back again. Before calling the + Write() function, it is recommended for the caller to first call + the EraseBlocks() function to erase the specified block to + write. A block erase cycle will transition bits from the + (NOT)EFI_FVB_ERASE_POLARITY state back to the + EFI_FVB_ERASE_POLARITY state. Implementations should be + mindful that the firmware volume might be in the WriteDisabled + state. If it is in this state, the Write() function must + return the status code EFI_ACCESS_DENIED without modifying the + contents of the firmware volume. The Write() function must + also prevent spanning block boundaries. If a write is + requested that spans a block boundary, the write must store up + to the boundary but not beyond. The output parameter NumBytes + must be set to correctly indicate the number of bytes actually + written. The caller must be aware that a write may be + partially completed. All writes, partial or otherwise, must be + fully flushed to the hardware before the Write() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writing. + + @param NumBytes The pointer to a UINTN. At entry, *NumBytes + contains the total size of the buffer. At + exit, *NumBytes contains the total number of + bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer that + contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an + LBA boundary. On output, NumBytes + contains the total number of bytes + actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the + WriteDisabled state. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning + and could not be written. + + +**/ +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Erases and initializes a firmware volume block. + + The EraseBlocks() function erases one or more blocks as denoted + by the variable argument list. The entire parameter list of + blocks must be verified before erasing any blocks. If a block is + requested that does not exist within the associated firmware + volume (it has a larger index than the last block of the + firmware volume), the EraseBlocks() function must return the + status code EFI_INVALID_PARAMETER without modifying the contents + of the firmware volume. Implementations should be mindful that + the firmware volume might be in the WriteDisabled state. If it + is in this state, the EraseBlocks() function must return the + status code EFI_ACCESS_DENIED without modifying the contents of + the firmware volume. All calls to EraseBlocks() must be fully + flushed to the hardware before the EraseBlocks() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL + instance. + + @param ... The variable argument list is a list of tuples. + Each tuple describes a range of LBAs to erase + and consists of the following: + - An EFI_LBA that indicates the starting LBA + - A UINTN that indicates the number of blocks to + erase. + + The list is terminated with an + EFI_LBA_LIST_TERMINATOR. For example, the + following indicates that two ranges of blocks + (5-7 and 10-11) are to be erased: EraseBlocks + (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR); + + @retval EFI_SUCCESS The erase request successfully + completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the + WriteDisabled state. + @retval EFI_DEVICE_ERROR The block device is not functioning + correctly and could not be written. + The firmware device may have been + partially erased. + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed + in the variable argument list do + not exist in the firmware volume. + +**/ +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + return EFI_UNSUPPORTED; +} + + +// +// Making this global saves a few bytes in image size +// +EFI_HANDLE gFvbHandle = NULL; + + +/// +/// The Firmware Volume Block Protocol is the low-level interface +/// to a firmware volume. File-level access to a firmware volume +/// should not be done using the Firmware Volume Block Protocol. +/// Normal access to a firmware volume must use the Firmware +/// Volume Protocol. Typically, only the file system driver that +/// produces the Firmware Volume Protocol will bind to the +/// Firmware Volume Block Protocol. +/// +EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL gFvbProtocol = { + FvbGetAttributes, + FvbSetAttributes, + FvbGetPhysicalAddress, + FvbGetBlockSize, + FvbRead, + FvbWrite, + FvbEraseBlocks, + /// + /// The handle of the parent firmware volume. + /// + NULL +}; + + +/** + Initialize the state information for the CPU Architectural Protocol + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +FvbDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + + Status = gBS->InstallMultipleProtocolInterfaces ( + &gFvbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, &gFvbProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // SetVertAddressEvent () + + // GCD Map NAND as RT + + return Status; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.inf new file mode 100644 index 000000000..9e320d85c --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD +# License which accompanies this distribution. The full text of the license +# may be found at http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FvbDxe + FILE_GUID = 43ECE281-D9E2-4DD0-B304-E6A5689256F4 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = FvbDxeInitialize + + +[Sources.common] + FvbDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg.dec + +[LibraryClasses] + BaseLib + UefiLib + UefiBootServicesTableLib + DebugLib + PrintLib + UefiDriverEntryPoint + IoLib + +[Guids] + + +[Protocols] + gEfiFirmwareVolumeBlockProtocolGuid + +[FixedPcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + +[depex] + TRUE diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c new file mode 100644 index 000000000..2fd2b8353 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c @@ -0,0 +1,78 @@ +/** @file + Template for ArmEb DebugAgentLib. + + For ARM we reserve FIQ for the Debug Agent Timer. We don't care about + laytency as we only really need the timer to run a few times a second + (how fast can some one type a ctrl-c?), but it works much better if + the interrupt we are using to break into the debugger is not being + used, and masked, by the system. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> + +#include <Library/DebugAgentTimerLib.h> + +#include <ArmEb/ArmEb.h> + + +/** + Setup all the hardware needed for the debug agents timer. + + This function is used to set up debug enviroment. + +**/ +VOID +EFIAPI +DebugAgentTimerIntialize ( + VOID + ) +{ + // Map Timer to FIQ +} + + +/** + Set the period for the debug agent timer. Zero means disable the timer. + + @param[in] TimerPeriodMilliseconds Frequency of the debug agent timer. + +**/ +VOID +EFIAPI +DebugAgentTimerSetPeriod ( + IN UINT32 TimerPeriodMilliseconds + ) +{ + if (TimerPeriodMilliseconds == 0) { + // Disable timer and Disable FIQ + return; + } + + // Set timer period and unmask FIQ +} + + +/** + Perform End Of Interrupt for the debug agent timer. This is called in the + interrupt handler after the interrupt has been processed. + +**/ +VOID +EFIAPI +DebugAgentTimerEndOfInterrupt ( + VOID + ) +{ + // EOI Timer interrupt for FIQ +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf new file mode 100644 index 000000000..7eb16cd30 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf @@ -0,0 +1,37 @@ +#/** @file +# Component description file for Base PCI Cf8 Library. +# +# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles. +# Layers on top of an I/O Library instance. +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmEbDebugAgentTimerLib + FILE_GUID = 80949BBB-68EE-4a4c-B434-D5DB5A232F0C + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DebugAgentTimerLib|SEC BASE DXE_CORE + + +[Sources.common] + DebugAgentTimerLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg.dec + +[LibraryClasses] + IoLib diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoard.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoard.c new file mode 100644 index 000000000..2f734f692 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoard.c @@ -0,0 +1,210 @@ +/** @file +* +* Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Drivers/PL341Dmc.h> +#include <Platform/ArmPlatform.h> +#include <Ppi/ArmMpCoreInfo.h> + +ARM_CORE_INFO mExynosMpCoreInfo[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + } +}; +/** + Return if Trustzone is supported by your platform + + A non-zero value must be returned if you want to support a Secure World on your platform. + ArmPlatformTrustzoneInit() will later set up the secure regions. + This function can return 0 even if Trustzone is supported by your processor. In this case, + the platform will continue to run in Secure World. + + @return A non-zero value if Trustzone supported. + +**/ +UINTN ArmPlatformTrustzoneSupported(VOID) { + // There is no Trustzone controllers (TZPC & TZASC) and no Secure Memory on RTSM + return TRUE; +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID ArmPlatformTrustzoneInit(VOID) { + UINT32 TZPCBase; + TZPCBase = PcdGet32(PcdTZPCBase) + TZPC0_OFFSET; + MmioWrite32((TZPCBase + 0x00),0x00); + MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF); + + TZPCBase = PcdGet32(PcdTZPCBase) + TZPC1_OFFSET; + MmioWrite32((TZPCBase + 0x00),0x00); + MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF); + + TZPCBase = PcdGet32(PcdTZPCBase) + TZPC2_OFFSET; + MmioWrite32((TZPCBase + 0x00),0x00); + MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF); + + TZPCBase = PcdGet32(PcdTZPCBase) + TZPC3_OFFSET; + MmioWrite32((TZPCBase + 0x00),0x00); + MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF); + + TZPCBase = PcdGet32(PcdTZPCBase) + TZPC4_OFFSET; + MmioWrite32((TZPCBase + 0x00),0x00); + MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF); + + + TZPCBase = PcdGet32(PcdTZPCBase) + TZPC5_OFFSET; + MmioWrite32((TZPCBase + 0x00),0x00); + MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF); + MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF); +} + +/** + Remap the memory at 0x0 + + Some platform requires or gives the ability to remap the memory at the address 0x0. + This function can do nothing if this feature is not relevant to your platform. + +**/ +VOID ArmPlatformBootRemapping(VOID) { + // Disable memory remapping and return to normal mapping + MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE +} + + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID ArmPlatformInitializeSystemMemory(VOID) { + // We do not need to initialize the System Memory on RTSM +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ +return RETURN_SUCCESS; +} + + +VOID +ArmPlatformNormalInitialize ( + VOID + ) { + +} + +VOID +ArmPlatformSecExtraAction ( + IN UINTN CoreId, + OUT UINTN* JumpAddress + ) +{ + *JumpAddress = PcdGet32(PcdFvBaseAddress); +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mExynosMpCoreInfo) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mExynosMpCoreInfo; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S new file mode 100644 index 000000000..9dc7abdf9 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S @@ -0,0 +1,635 @@ +/* + * Copyright (c) 2011, Samsung Electronics Co. All rights reserved. + * + * This program and the accompanying materials + * are licensed and made available under the terms and conditions of the BSD License + * which accompanies this distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + */ + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <Platform/ArmPlatform.h> +#include <AutoGen.h> + +/* Start of Code section */ +.text +.align 3 + +GCC_ASM_IMPORT(_SetupPrimaryCoreStack) +GCC_ASM_EXPORT(ArmPlatformTZPCInitialized) +GCC_ASM_EXPORT(ArmPlatformUARTInitialized) +GCC_ASM_EXPORT(ArmPlatformIsClockInitialized) +GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized) +GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory) +GCC_ASM_EXPORT(ArmPlatformSecBootAction) +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) + +ASM_PFX(ArmPlatformTZPCInitialized): + ldr r0, =Exynos4210_TZPC0_BASE + mov r1, #0x0 + str r1, [r0] + mov r1, #0xff + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC1_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC2_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC3_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC4_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC5_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + bx lr + +ASM_PFX(ArmPlatformUARTInitialized): + ldr r0, =0x11400000 + ldr r1, =0x22222222 + str r1, [r0] + ldr r0, =0x11400020 + ldr r1, =0x222222 + str r1, [r0] + + ldr r0, =Exynos4210_CMU_BASE + ldr r1, =CLK_SRC_PERIL0_VAL + ldr r2, =CLK_SRC_PERIL0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_DIV_PERIL0_VAL + ldr r2, =CLK_DIV_PERIL0_OFFSET + str r1, [r0, r2] + + ldr r0, =Exynos4210_UART_BASE + ldr r1, =0x111 + str r1, [r0, #UFCON_OFFSET] + + mov r1, #0x3 + str r1, [r0, #ULCON_OFFSET] + + ldr r1, =0x3c5 + str r1, [r0, #UCON_OFFSET] + + ldr r1, =UART_UBRDIV_VAL + str r1, [r0, #UBRDIV_OFFSET] + + ldr r1, =UART_UDIVSLOT_VAL + str r1, [r0, #UDIVSLOT_OFFSET] + + ldr r1, =0x4c4c4c4c + str r1, [r0, #UTXH_OFFSET] // 'L' + + ldr r1, =0x4a4a4a4a + str r1, [r0, #UTXH_OFFSET] // 'J' + + ldr r1, =0x50505050 + str r1, [r0, #UTXH_OFFSET] // 'P' + + bx lr + + +ASM_PFX(ArmPlatformIsClockInitialized): + ldr r0, =Exynos4210_CMU_BASE + + ldr r1, =0x0 + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_1: + subs r1, r1, #1 + bne cmu_1 + + ldr r1, =CLK_DIV_CPU0_VAL + ldr r2, =CLK_DIV_CPU0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_DIV_CPU1_VAL + ldr r2, =CLK_DIV_CPU1_OFFSET + str r1, [r0, r2] + + ldr r1, =0x10000 + ldr r2, =CLK_SRC_DMC_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_2: + subs r1, r1, #1 + bne cmu_2 + + ldr r1, =CLK_DIV_DMC0_VAL + ldr r2, =CLK_DIV_DMC0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_DIV_DMC1_VAL + ldr r2, =CLK_DIV_DMC1_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_TOP0_VAL + ldr r2, =CLK_SRC_TOP0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_SRC_TOP1_VAL + ldr r2, =CLK_SRC_TOP1_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY + +cmu_3: + subs r1, r1, #1 + bne cmu_3 + + ldr r1, =CLK_DIV_TOP_VAL + ldr r2, =CLK_DIV_TOP_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_LEFTBUS_VAL + ldr r2, =CLK_SRC_LEFTBUS_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_4: + subs r1, r1, #1 + bne cmu_4 + + ldr r1, =CLK_DIV_LEFRBUS_VAL + ldr r2, =CLK_DIV_LEFTBUS_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_RIGHTBUS_VAL + ldr r2, =CLK_SRC_RIGHTBUS_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_5: + subs r1, r1, #1 + bne cmu_5 + + ldr r1, =CLK_DIV_RIGHTBUS_VAL + ldr r2, =CLK_DIV_RIGHTBUS_OFFSET + str r1, [r0, r2] + + ldr r1, =APLL_LOCK_VAL + ldr r2, =APLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r1, =MPLL_LOCK_VAL + ldr r2, =MPLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r1, =EPLL_LOCK_VAL + ldr r2, =EPLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r1, =VPLL_LOCK_VAL + ldr r2, =VPLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =APLL_CON1_VAL + ldr r2, =APLL_CON1_OFFSET + str r1, [r0, r2] + + ldr r1, =APLL_CON0_VAL + ldr r2, =APLL_CON0_OFFSET + str r1, [r0, r2] + + ldr r1, =MPLL_CON1_VAL + ldr r2, =MPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =MPLL_CON0_VAL + ldr r2, =MPLL_CON0_OFFSET + str r1, [r0, r2] + + ldr r1, =EPLL_CON1_VAL + ldr r2, =EPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =EPLL_CON0_VAL + ldr r2, =EPLL_CON0_OFFSET + str r1, [r0, r2] + + ldr r1, =VPLL_CON1_VAL + ldr r2, =VPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =VPLL_CON0_VAL + ldr r2, =VPLL_CON0_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_6: + subs r1, r1, #1 + bne cmu_6 + + ldr r1, =CLK_SRC_CPU_VAL_MOUTMPLLFOUT + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_7: + subs r1, r1, #1 + bne cmu_7 + + ldr r0, =Exynos4210_DMC_0_BASE + + ldr r1, =0x6910100A + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + ldr r1, =0x6910100B + + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_8: + subs r1, r1, #1 + bne cmu_8 + + ldr r1, =0x0000008C + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_9: + subs r1, r1, #1 + bne cmu_9 + + ldr r0, =Exynos4210_DMC_1_BASE + + ldr r1, =0xe910100A + + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + ldr r1, =0xe910100B + + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_10: + subs r1, r1, #1 + bne cmu_10 + + ldr r1, =0x0000008C + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_11: + subs r1, r1, #1 + bne cmu_11 + + ldr r0, =Exynos4210_DMC_0_BASE + ldr r1, =0x0FFF30fa + ldr r2, =DMC_CONCONTROL + str r1, [r0, r2] + ldr r0, =Exynos4210_DMC_1_BASE + ldr r1, =0x0FFF30fa + ldr r2, =DMC_CONCONTROL + str r1, [r0, r2] + + ldr r0, =Exynos4210_DMC_0_BASE + ldr r1, =0x00202537 + ldr r2, =DMC_MEMCONTROL + str r1, [r0, r2] + ldr r0, =Exynos4210_DMC_1_BASE + ldr r1, =0x00202537 + ldr r2, =DMC_MEMCONTROL + str r1, [r0, r2] + + bx lr + +/* + * Call at the beginning of the platform boot up + * + * This function allows the firmware platform to do extra actions at the early + * stage of the platform power up. + * + * Note: This function must be implemented in assembler + * as there is no stack set up yet + */ +ASM_PFX(ArmPlatformSecBootAction): + bx lr + + +ASM_PFX(ArmPlatformSecBootMemoryInit): + bx lr + +/* + * Called at the early stage of the Boot phase to know if the memory has + * already been initialized. Running the code from the reset vector does + * not mean we start from cold boot. In some case, we can go through this + * code with the memory already initialized. + * Because this function is called at the early stage, the implementation + * must not use the stack. Its implementation must probably done in + * assembly to ensure this requirement. + * + * @return Return the condition value into the 'Z' flag + */ +ASM_PFX(ArmPlatformIsMemoryInitialized): + /* + * Check if the memory has been already mapped, + * if so skipped the memory initialization + */ + LoadConstantToReg (Exynos4210_DMC_0_BASE, r0) + ldr r0, [r0, #0] + and r0, r0, #0x20 + cmp r0, #0x00 + bx lr + +/* + * Initialize the memory where the initial stacks will reside + * + * This memory can contain the initial stacks (Secure and Secure Monitor + * stacks). In some platform, this region is already initialized and the + * implementation of this function can do nothing. This memory can also + * represent the Secure RAM. + * This function is called before the satck has been set up. Its + * implementation must ensure the stack pointer is not used (probably + * required to use assembly language) + */ +ASM_PFX(ArmPlatformInitializeBootMemory): +/* + * Check if the Memory is already Initialized. + * If Initialized goto Stack setup + */ + mov r10, lr + bl ASM_PFX(ArmPlatformIsMemoryInitialized) + bne skip_initmem + + ldr r0, =0x10010350 + mov r1, #1 + str r1, [r0] + +/* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */ + ldr r0, =Exynos4210_CMU_BASE + ldr r1, =0x13113113 + ldr r2, =Exynos4210_CMU_DIV_DMC0 + str r1, [r0, r2] + +/* MIU Setting */ + ldr r0, =Exynos4210_MIU_BASE + + ldr r1, =0x20001507 + str r1, [r0, #0x400] + ldr r1, =0x00000001 + str r1, [r0, #0xc00] + +/*****************************************************************/ +/*DREX0***********************************************************/ +/*****************************************************************/ + + ldr r0, =Exynos4210_DMC_0_BASE + + ldr r1, =0xE3855503 + str r1, [r0, #DMC_PHYZQCONTROL] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + ldr r1, =0x0FFF30da + str r1, [r0, #DMC_CONCONTROL] + + ldr r1, =0x00202500 + str r1, [r0, #DMC_MEMCONTROL] + + ldr r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] + + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + ldr r1, =0x0000005D + str r1, [r0, #DMC_TIMINGAREF] + + ldr r1, =0x34498691 + str r1, [r0, #DMC_TIMINGROW] + + ldr r1, =0x36330306 + str r1, [r0, #DMC_TIMINGDATA] + + ldr r1, =0x50380365 + str r1, [r0, #DMC_TIMINGPOWER] + + mov r2, #Exynos4210_DMC_DELAY + +loop_2: + subs r2, r2, #1 + bne loop_2 + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_3: + subs r2, r2, #1 + bne loop_3 + ldr r1, =0x00071C00 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_4: + subs r2, r2, #1 + bne loop_4 + + ldr r1, =0x00010BFC + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_5: + subs r2, r2, #1 + bne loop_5 + ldr r1, =0x00000488 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000810 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000C08 + str r1, [r0, #DMC_DIRECTCMD] + +/* get DMC density information */ + ldr r1, =0x09010000 + mov r3, #10 +loop_6: + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_7: + subs r2, r2, #1 + bne loop_7 + ldr r6, [r0, #DMC_MRSTATUS] + subs r3, r3, #1 + bne loop_6 + and r6, r6, #0x3c + lsr r6, r6, #2 + cmp r6, #6 + ldreq r1, =0x20e01323 + ldrne r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] + +/*****************************************************************/ +/*DREX1***********************************************************/ +/*****************************************************************/ + ldr r0, =Exynos4210_DMC_1_BASE + ldr r1, =0xE3855503 + str r1, [r0, #DMC_PHYZQCONTROL] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + ldr r1, =0x0FFF30da + str r1, [r0, #DMC_CONCONTROL] + + ldr r1, =0x00202500 + str r1, [r0, #DMC_MEMCONTROL] + + ldr r1, =0x40f01223 + str r1, [r0, #DMC_MEMCONFIG0] + + ldr r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] + + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + ldr r1, =0x0000005D + str r1, [r0, #DMC_TIMINGAREF] + + ldr r1, =0x34498691 + str r1, [r0, #DMC_TIMINGROW] + + ldr r1, =0x36330306 + str r1, [r0, #DMC_TIMINGDATA] + + ldr r1, =0x50380365 + str r1, [r0, #DMC_TIMINGPOWER] + + mov r2, #Exynos4210_DMC_DELAY +loop_8: + subs r2, r2, #1 + bne loop_8 + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_9: + subs r2, r2, #1 + bne loop_9 + ldr r1, =0x00071C00 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_10: + subs r2, r2, #1 + bne loop_10 + + ldr r1, =0x00010BFC + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_11: + subs r2, r2, #1 + bne loop_11 + ldr r1, =0x00000488 + str r1, [r0, #DMC_DIRECTCMD] + + ldr r1, =0x00000810 + str r1, [r0, #DMC_DIRECTCMD] + + ldr r1, =0x00000C08 + str r1, [r0, #DMC_DIRECTCMD] + +/* get DMC density information */ + ldr r1, =0x09010000 + mov r3, #10 +loop_12: + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_13: + subs r2, r2, #1 + bne loop_13 + ldr r7, [r0, #DMC_MRSTATUS] + subs r3, r3, #1 + bne loop_12 + and r7, r7, #0x3c + lsr r7, r7, #2 + cmp r7, #6 + ldreq r1, =0x20e01323 + ldrne r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] +skip_initmem: + mov lr, r10 + bx lr + +.end diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm new file mode 100644 index 000000000..7960f22ee --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm @@ -0,0 +1,609 @@ +// +// Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <Platform/ArmPlatform.h> +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformTZPCInitialized + EXPORT ArmPlatformUARTInitialized + EXPORT ArmPlatformIsClockInitialized + EXPORT ArmPlatformIsMemoryInitialized + EXPORT ArmPlatformInitializeBootMemory + + PRESERVE8 + AREA ArmRealViewEbHelper, CODE, READONLY + +ArmPlatformTZPCInitialized + ldr r0, =Exynos4210_TZPC0_BASE + mov r1, #0x0 + str r1, [r0] + mov r1, #0xff + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC1_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC2_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC3_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC4_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =Exynos4210_TZPC5_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + bx lr + +ArmPlatformUARTInitialized + ldr r0, =0x11400000 + ldr r1, =0x22222222 + str r1, [r0] + ldr r0, =0x11400020 + ldr r1, =0x222222 + str r1, [r0] + + ldr r0, =Exynos4210_CMU_BASE + ldr r1, =CLK_SRC_PERIL0_VAL + ldr r2, =CLK_SRC_PERIL0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_DIV_PERIL0_VAL + ldr r2, =CLK_DIV_PERIL0_OFFSET + str r1, [r0, r2] + + ldr r0, =Exynos4210_UART_BASE + ldr r1, =0x111 + str r1, [r0, #UFCON_OFFSET] + + mov r1, #0x3 + str r1, [r0, #ULCON_OFFSET] + + ldr r1, =0x3c5 + str r1, [r0, #UCON_OFFSET] + + ldr r1, =UART_UBRDIV_VAL + str r1, [r0, #UBRDIV_OFFSET] + + ldr r1, =UART_UDIVSLOT_VAL + str r1, [r0, #UDIVSLOT_OFFSET] + + ldr r1, =0x4c4c4c4c + str r1, [r0, #UTXH_OFFSET] // 'L' + + ldr r1, =0x4a4a4a4a + str r1, [r0, #UTXH_OFFSET] // 'J' + + ldr r1, =0x50505050 + str r1, [r0, #UTXH_OFFSET] // 'P' + + bx lr + +ArmPlatformIsClockInitialized + ldr r0, =Exynos4210_CMU_BASE + + ldr r1, =0x0 + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_1 + subs r1, r1, #1 + bne cmu_1 + + ldr r1, =CLK_DIV_CPU0_VAL + ldr r2, =CLK_DIV_CPU0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_DIV_CPU1_VAL + ldr r2, =CLK_DIV_CPU1_OFFSET + str r1, [r0, r2] + + ldr r1, =0x10000 + ldr r2, =CLK_SRC_DMC_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_2 + subs r1, r1, #1 + bne cmu_2 + + ldr r1, =CLK_DIV_DMC0_VAL + ldr r2, =CLK_DIV_DMC0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_DIV_DMC1_VAL + ldr r2, =CLK_DIV_DMC1_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_TOP0_VAL + ldr r2, =CLK_SRC_TOP0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_SRC_TOP1_VAL + ldr r2, =CLK_SRC_TOP1_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_3 + subs r1, r1, #1 + bne cmu_3 + + ldr r1, =CLK_DIV_TOP_VAL + ldr r2, =CLK_DIV_TOP_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_LEFTBUS_VAL + ldr r2, =CLK_SRC_LEFTBUS_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_4 + subs r1, r1, #1 + bne cmu_4 + + ldr r1, =CLK_DIV_LEFRBUS_VAL + ldr r2, =CLK_DIV_LEFTBUS_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_RIGHTBUS_VAL + ldr r2, =CLK_SRC_RIGHTBUS_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_5 + subs r1, r1, #1 + bne cmu_5 + + ldr r1, =CLK_DIV_RIGHTBUS_VAL + ldr r2, =CLK_DIV_RIGHTBUS_OFFSET + str r1, [r0, r2] + + ldr r1, =APLL_LOCK_VAL + ldr r2, =APLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r1, =MPLL_LOCK_VAL + ldr r2, =MPLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r1, =EPLL_LOCK_VAL + ldr r2, =EPLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r1, =VPLL_LOCK_VAL + ldr r2, =VPLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =APLL_CON1_VAL + ldr r2, =APLL_CON1_OFFSET + str r1, [r0, r2] + + ldr r1, =APLL_CON0_VAL + ldr r2, =APLL_CON0_OFFSET + str r1, [r0, r2] + + ldr r1, =MPLL_CON1_VAL + ldr r2, =MPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =MPLL_CON0_VAL + ldr r2, =MPLL_CON0_OFFSET + str r1, [r0, r2] + + ldr r1, =EPLL_CON1_VAL + ldr r2, =EPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =EPLL_CON0_VAL + ldr r2, =EPLL_CON0_OFFSET + str r1, [r0, r2] + + ldr r1, =VPLL_CON1_VAL + ldr r2, =VPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =VPLL_CON0_VAL + ldr r2, =VPLL_CON0_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_6 + subs r1, r1, #1 + bne cmu_6 + + ldr r1, =CLK_SRC_CPU_VAL_MOUTMPLLFOUT + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_7 + subs r1, r1, #1 + bne cmu_7 + + ldr r0, =Exynos4210_DMC_0_BASE + + ldr r1, =0x6910100A + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + ldr r1, =0x6910100B + + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_8 + subs r1, r1, #1 + bne cmu_8 + + ldr r1, =0x0000008C + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_9 + subs r1, r1, #1 + bne cmu_9 + + ldr r0, =Exynos4210_DMC_1_BASE + + ldr r1, =0xe910100A + + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + ldr r1, =0xe910100B + + ldr r2, =DMC_PHYCONTROL0 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_10 + subs r1, r1, #1 + bne cmu_10 + + ldr r1, =0x0000008C + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + ldr r1, =0x00000084 + ldr r2, =DMC_PHYCONTROL1 + str r1, [r0, r2] + + mov r1, #Exynos4210_CMU_DELAY +cmu_11 + subs r1, r1, #1 + bne cmu_11 + + ldr r0, =Exynos4210_DMC_0_BASE + ldr r1, =0x0FFF30fa + ldr r2, =DMC_CONCONTROL + str r1, [r0, r2] + ldr r0, =Exynos4210_DMC_1_BASE + ldr r1, =0x0FFF30fa + ldr r2, =DMC_CONCONTROL + str r1, [r0, r2] + + ldr r0, =Exynos4210_DMC_0_BASE + ldr r1, =0x00202537 + ldr r2, =DMC_MEMCONTROL + str r1, [r0, r2] + ldr r0, =Exynos4210_DMC_1_BASE + ldr r1, =0x00202537 + ldr r2, =DMC_MEMCONTROL + str r1, [r0, r2] + + bx lr + +/** + Called at the early stage of the Boot phase to know if the memory has already been initialized + + Running the code from the reset vector does not mean we start from cold boot. In some case, we + can go through this code with the memory already initialized. + Because this function is called at the early stage, the implementation must not use the stack. + Its implementation must probably done in assembly to ensure this requirement. + + @return Return the condition value into the 'Z' flag + +**/ +ArmPlatformIsMemoryInitialized + // Check if the memory has been already mapped, if so skipped the memory initialization + LoadConstantToReg (Exynos4210_DMC_0_BASE, r0) + ldr r0, [r0, #0] + // Check Controller register is initialized or not by Auto-refresh bit + and r0, r0, #0x20 + cmp r0, #0x20 + bx lr +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformInitializeBootMemory + +//Async bridge configuration at CPU_core(1: half_sync 0: full_sync) + ldr r0, =0x10010350 + mov r1, #1 + str r1, [r0] + +//CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC + ldr r0, =Exynos4210_CMU_BASE + ldr r1, =0x13113113 + ldr r2, =Exynos4210_CMU_DIV_DMC0 + str r1, [r0, r2] + +//MIU Setting + ldr r0, =Exynos4210_MIU_BASE + + ldr r1, =0x20001507 + str r1, [r0, #0x400] + ldr r1, =0x00000001 + str r1, [r0, #0xc00] + +/*****************************************************************/ +/*DREX0***********************************************************/ +/*****************************************************************/ + + ldr r0, =Exynos4210_DMC_0_BASE + + ldr r1, =0xE3855503 + str r1, [r0, #DMC_PHYZQCONTROL] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + ldr r1, =0x0FFF30da + str r1, [r0, #DMC_CONCONTROL] + + ldr r1, =0x00202500 + str r1, [r0, #DMC_MEMCONTROL] + + ldr r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] + + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + ldr r1, =0x0000005D + str r1, [r0, #DMC_TIMINGAREF] + + ldr r1, =0x34498691 + str r1, [r0, #DMC_TIMINGROW] + + ldr r1, =0x36330306 + str r1, [r0, #DMC_TIMINGDATA] + + ldr r1, =0x50380365 + str r1, [r0, #DMC_TIMINGPOWER] + + mov r2, #Exynos4210_DMC_DELAY + +loop_2 + subs r2, r2, #1 + bne loop_2 + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_3 + subs r2, r2, #1 + bne loop_3 + ldr r1, =0x00071C00 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_4 + subs r2, r2, #1 + bne loop_4 + + ldr r1, =0x00010BFC + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_5 + subs r2, r2, #1 + bne loop_5 + ldr r1, =0x00000488 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000810 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000C08 + str r1, [r0, #DMC_DIRECTCMD] +#if 1 +//get DMC density information + ldr r1, =0x09010000 + mov r3, #10 +loop_6 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_7 + subs r2, r2, #1 + bne loop_7 + ldr r6, [r0, #DMC_MRSTATUS] + subs r3, r3, #1 + bne loop_6 + and r6, r6, #0x3c + lsr r6, r6, #2 + cmp r6, #6 + ldreq r1, =0x20e01323 + ldrne r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] +#endif + +/*****************************************************************/ +/*DREX1***********************************************************/ +/*****************************************************************/ + ldr r0, =Exynos4210_DMC_1_BASE + ldr r1, =0xE3855503 + str r1, [r0, #DMC_PHYZQCONTROL] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x0000008C + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000084 + str r1, [r0, #DMC_PHYCONTROL1] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + ldr r1, =0x0FFF30da + str r1, [r0, #DMC_CONCONTROL] + + ldr r1, =0x00202500 + str r1, [r0, #DMC_MEMCONTROL] + + ldr r1, =0x40f01223 + str r1, [r0, #DMC_MEMCONFIG0] + + ldr r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] + + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + ldr r1, =0x0000005D + str r1, [r0, #DMC_TIMINGAREF] + + ldr r1, =0x34498691 + str r1, [r0, #DMC_TIMINGROW] + + ldr r1, =0x36330306 + str r1, [r0, #DMC_TIMINGDATA] + + ldr r1, =0x50380365 + str r1, [r0, #DMC_TIMINGPOWER] + + mov r2, #Exynos4210_DMC_DELAY +loop_8 + subs r2, r2, #1 + bne loop_8 + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_9 + subs r2, r2, #1 + bne loop_9 + ldr r1, =0x00071C00 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_10 + subs r2, r2, #1 + bne loop_10 + + ldr r1, =0x00010BFC + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_11 + subs r2, r2, #1 + bne loop_11 + ldr r1, =0x00000488 + str r1, [r0, #DMC_DIRECTCMD] + + ldr r1, =0x00000810 + str r1, [r0, #DMC_DIRECTCMD] + + ldr r1, =0x00000C08 + str r1, [r0, #DMC_DIRECTCMD] + +#if 1 +// get DMC density information + ldr r1, =0x09010000 + mov r3, #10 +loop_12 + str r1, [r0, #DMC_DIRECTCMD] + mov r2, #Exynos4210_DMC_DELAY +loop_13 + subs r2, r2, #1 + bne loop_13 + ldr r7, [r0, #DMC_MRSTATUS] + subs r3, r3, #1 + bne loop_12 + and r7, r7, #0x3c + lsr r7, r7, #2 + cmp r7, #6 + ldreq r1, =0x20e01323 + ldrne r1, =0x20f01223 + str r1, [r0, #DMC_MEMCONFIG0] +#endif + + bx lr + + END diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf new file mode 100644 index 000000000..847f8ae27 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf @@ -0,0 +1,49 @@ +#/* @file +# Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmdkBoardLib + FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + SamsungPlatformPkgOrigen/ExynosPkg/ExynosPkg.dec + +[LibraryClasses] + IoLib + ArmLib + + +[Sources.common] + SmdkBoard.c + SmdkBoardMem.c + +[Protocols] + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdStandalone +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + gExynosPkgTokenSpaceGuid.PcdTZPCBase diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardMem.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardMem.c new file mode 100644 index 000000000..db1a163c8 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardMem.c @@ -0,0 +1,210 @@ +/** @file +* +* Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED +#define DDR_ATTRIBUTES_SECURE_CACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK +#define DDR_ATTRIBUTES_SECURE_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED + +#if 0 +/** + Return the information about the memory region in permanent memory used by PEI + + One of the PEI Module must install the permament memory used by PEI. This function returns the + information about this region for your platform to this PEIM module. + + @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules + @param[out] PeiMemorySize Size of the memory region used by PEI core and modules + +**/ +VOID ArmPlatformGetPeiMemory ( + OUT UINTN* PeiMemoryBase, + OUT UINTN* PeiMemorySize + ) { + ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL)); + + // *PeiMemoryBase = ARM_EB_DRAM_BASE + ARM_EB_EFI_FIX_ADDRESS_REGION_SZ; + // *PeiMemorySize = ARM_EB_EFI_MEMORY_REGION_SZ; + *PeiMemoryBase = PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdSystemMemoryFixRegionSize); + *PeiMemorySize = PcdGet32(PcdSystemMemoryUefiRegionSize); +} +#endif +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) { +// UINT32 val32; + UINT32 CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 5); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // SFR + VirtualMemoryTable[0].PhysicalBase = 0x00000000; + VirtualMemoryTable[0].VirtualBase = 0x00000000; + VirtualMemoryTable[0].Length = 0x20000000; + VirtualMemoryTable[0].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DDR + VirtualMemoryTable[1].PhysicalBase = 0x40000000; + VirtualMemoryTable[1].VirtualBase = 0x40000000; + VirtualMemoryTable[1].Length = 0x0e000000; + VirtualMemoryTable[1].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + + // framebuffer + VirtualMemoryTable[2].PhysicalBase = 0x4e000000; + VirtualMemoryTable[2].VirtualBase = 0x4e000000; + VirtualMemoryTable[2].Length = 0x02000000; + VirtualMemoryTable[2].Attributes = DDR_ATTRIBUTES_UNCACHED; + + VirtualMemoryTable[3].PhysicalBase = 0x50000000; + VirtualMemoryTable[3].VirtualBase = 0x50000000; + VirtualMemoryTable[3].Length = 0xb0000000; + VirtualMemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + + // End of Table + VirtualMemoryTable[4].PhysicalBase = 0; + VirtualMemoryTable[4].VirtualBase = 0; + VirtualMemoryTable[4].Length = 0; + VirtualMemoryTable[4].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + *VirtualMemoryMap = VirtualMemoryTable; +} + + + +#if 0 +/** + Return the EFI Memory Map of your platform + + This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource + Descriptor HOBs used by DXE core. + + @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an + EFI Memory region. This array must be ended by a zero-filled entry + +**/ +VOID ArmPlatformGetEfiMemoryMap ( + OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap +) { + EFI_RESOURCE_ATTRIBUTE_TYPE Attributes; + UINT64 MemoryBase; + UINTN Index = 0; + ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR *EfiMemoryTable; + + ASSERT(EfiMemoryMap != NULL); + + EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6); + + Attributes = + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + MemoryBase = PcdGet32(PcdSystemMemoryBase);//ARM_EB_DRAM_BASE; + + // Memory Reserved for fixed address allocations (such as Exception Vector Table) + EfiMemoryTable[Index].ResourceAttribute = Attributes; + EfiMemoryTable[Index].PhysicalStart = MemoryBase; + EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdSystemMemoryFixRegionSize);//ARM_EB_EFI_FIX_ADDRESS_REGION_SZ; + + MemoryBase += PcdGet32(PcdSystemMemoryFixRegionSize);//ARM_EB_EFI_FIX_ADDRESS_REGION_SZ; + + // Memory declared to PEI as permanent memory for PEI and DXE + EfiMemoryTable[++Index].ResourceAttribute = Attributes; + EfiMemoryTable[Index].PhysicalStart = MemoryBase; + EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdSystemMemoryUefiRegionSize);//ARM_EB_EFI_MEMORY_REGION_SZ; + + MemoryBase += PcdGet32(PcdSystemMemoryUefiRegionSize);//ARM_EB_EFI_MEMORY_REGION_SZ; + + // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000 + if (!PcdGet32(PcdStandalone)) { + // Chunk between the EFI Memory region and the firmware + EfiMemoryTable[++Index].ResourceAttribute = Attributes; + EfiMemoryTable[Index].PhysicalStart = MemoryBase; + //EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase; + EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdBaseAddress) - MemoryBase; + + // Chunk reserved by the firmware in DRAM + EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT); + //EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress); + EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdNormalFdBaseAddress); + //EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize); + EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdSize); + + //MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize); + MemoryBase = PcdGet32(PcdNormalFdBaseAddress) + PcdGet32(PcdNormalFdSize); + } + + // We allocate all the remain memory as untested system memory + EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED); + EfiMemoryTable[Index].PhysicalStart = MemoryBase; + EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdSystemMemorySize) - (MemoryBase-PcdGet32(PcdSystemMemoryBase)); + + EfiMemoryTable[++Index].ResourceAttribute = 0; + EfiMemoryTable[Index].PhysicalStart = 0; + EfiMemoryTable[Index].NumberOfBytes = 0; + + *EfiMemoryMap = EfiMemoryTable; +} +#endif + +/** + Return the EFI Memory Map of your platform + + This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource + Descriptor HOBs used by DXE core. + + @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an + EFI Memory region. This array must be ended by a zero-filled entry + +**/ +EFI_STATUS +ArmPlatformGetAdditionalSystemMemory ( + OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap +) { + +// ArmPlatformGetEfiMemoryMap(EfiMemoryMap); + //return EFI_SUCCESS; + return EFI_UNSUPPORTED; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSec.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSec.c new file mode 100644 index 000000000..9471df2fb --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSec.c @@ -0,0 +1,57 @@ +/** @file +* +* Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Drivers/PL310L2Cache.h> +#include <Drivers/PL341Dmc.h> + + +/** + Initialize controllers that must setup at the early stage + + Some peripherals must be initialized in Secure World. + For example, some L2x0 requires to be initialized in Secure World + ============ added by girish to resolve compile error================= +**/ + +VOID +ArmPlatformSecInitialize ( + VOID + ) { + // The L2x0 controller must be intialize in Secure World + L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), + PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES), + PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES), + 0,~0, // Use default setting for the Auxiliary Control Register + FALSE); + +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ +return; +} diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf new file mode 100644 index 000000000..ba6611939 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf @@ -0,0 +1,50 @@ +#/* @file +# Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmdkBoardSecLib + FILE_GUID = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + SamsungPlatformPkgOrigen/ExynosPkg/ExynosPkg.dec + +[LibraryClasses] + IoLib + ArmLib + L2X0CacheLib + +[Sources.common] + SmdkBoard.c + SmdkBoardSec.c + SmdkBoardHelper.asm | RVCT + SmdkBoardHelper.S | GCC + +[Protocols] + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdStandalone + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdL2x0ControllerBase + gExynosPkgTokenSpaceGuid.PcdTZPCBase diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.dsc b/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.dsc new file mode 100644 index 000000000..74d2b41b2 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.dsc @@ -0,0 +1,474 @@ +# +# Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = SmdkBoard-Exynos + PLATFORM_GUID = 66a5a01d-be0a-4398-9b74-5af4a261381f + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/SmdkBoard-Exynos + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.fdf + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +!endif + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + EfiResetSystemLib|SamsungPlatformPkgOrigen/ExynosPkg/Library/ResetSystemLib/ResetSystemLib.inf + EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf + EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + +# +# Assume everything is fixed at build +# + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf + EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf + EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + SerialPortLib|SamsungPlatformPkgOrigen/ExynosPkg/Library/SerialPortLib/SerialPortLib.inf + TimerLib|SamsungPlatformPkgOrigen/ExynosPkg/Library/TimerLib/TimerLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # Samsung specific + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + GdbSerialLib|SamsungPlatformPkgOrigen/ExynosPkg/Library/GdbSerialLib/GdbSerialLib.inf + + # iky for usb host + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf + ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf + ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf + ArmPlatformLib|SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + # L2 Cache Driver + L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf + +!if $(EDK2_SKIP_PEICORE)==1 + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf +!endif + +[LibraryClasses.common.PEI_CORE] + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + # note: this won't actually work since globals in PEI are not writeable + # need to generate an ARM PEI services table pointer implementation + PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + +[LibraryClasses.common.PEIM] + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + # note: this won't actually work since globals in PEI are not writeable + # need to generate an ARM PEI services table pointer implementation + PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + +[LibraryClasses.common.DXE_CORE] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + +[LibraryClasses.ARM] + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + +[BuildOptions] + RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A9 --thumb --fpu=softvfp -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + + GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb -mthumb-interwork -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a -mthumb-interwork -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + GCC:*_*_ARM_CC_FLAGS = -Os -mword-relocations -mfpu=vfp -ffixed-r8 + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + + XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/SamsungPlatformPkgOrigen/ExynosPkg/Include/Platform + XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +!if $(EDK2_SKIP_PEICORE) == 1 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"SMDK4210" + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + +# DEBUG_ASSERT_ENABLED 0x01 +# DEBUG_PRINT_ENABLED 0x02 +# DEBUG_CODE_ENABLED 0x04 +# CLEAR_MEMORY_ENABLED 0x08 +# ASSERT_BREAKPOINT_ENABLED 0x10 +# ASSERT_DEADLOOP_ENABLED 0x20 + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f + +# DEBUG_INIT 0x00000001 // Initialization +# DEBUG_WARN 0x00000002 // Warnings +# DEBUG_LOAD 0x00000004 // Load events +# DEBUG_FS 0x00000008 // EFI File system +# DEBUG_POOL 0x00000010 // Alloc & Free's +# DEBUG_PAGE 0x00000020 // Alloc & Free's +# DEBUG_INFO 0x00000040 // Verbose +# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers +# DEBUG_VARIABLE 0x00000100 // Variable +# DEBUG_BM 0x00000400 // Boot Manager +# DEBUG_BLKIO 0x00001000 // BlkIo Driver +# DEBUG_NET 0x00004000 // SNI Driver +# DEBUG_UNDI 0x00010000 // UNDI Driver +# DEBUG_LOADFILE 0x00020000 // UNDI Driver +# DEBUG_EVENT 0x00080000 // Event messages +# DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + +# +# Optional feature to help prevent EFI memory map fragments +# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob +# Values are in EFI Pages (4K). DXE Core will make sure that +# at least this much of each type of memory can be allocated +# from a single memory range. This way you only end up with +# maximum of two fragements for each type in the memory map +# (the memory used, and the free memory that was prereserved +# but not used). +# + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x00000000 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x01000000 + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000 # Top of SEC Stack for Secure World + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x4A000000 # Top of SEC Stack for Monitor World + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x2000 # Stack for each of the 4 CPU cores + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x48000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # Stacks for MPCores in Normal World + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000 + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x0f + gArmTokenSpaceGuid.PcdArmPrimaryCore|0x00 + gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + # + # ARM EB PCDS + # + gExynosPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000 + gExynosPkgTokenSpaceGuid.PcdConsoleUartBase|0x13810000 + gExynosPkgTokenSpaceGuid.PcdCmuBase|0x10030000 + gExynosPkgTokenSpaceGuid.PcdPWMTimerBase|0x139d0000 + gExynosPkgTokenSpaceGuid.PcdPmuBase|0x10020000 + gExynosPkgTokenSpaceGuid.PcdGpioPart1Base|0x11400000 + gExynosPkgTokenSpaceGuid.PcdGpioPart2Base|0x11000000 + gExynosPkgTokenSpaceGuid.PcdSdMmcBase|0x12530000 + gExynosPkgTokenSpaceGuid.PcdSysBase|0x10010000 + gExynosPkgTokenSpaceGuid.PcdFIMD0Base|0x11C00000 + gExynosPkgTokenSpaceGuid.PcdGICBase|0x10500000 + gExynosPkgTokenSpaceGuid.PcdTZPCBase|0x10100000 + # + # ARM PL390 General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x10490000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x10480000 + + # + # ARM OS Loader + # + #gArmTokenSpaceGuid.PcdArmMachineType|2925 + gArmTokenSpaceGuid.PcdArmMachineType|2456 + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SD-MMC Booting" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(B615F1F5-5088-43CD-809C-A16E52487D00)/HD(1,MBR,0x6F20736B,0x1D6E74,0x58A400)/zImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"root=/dev/mmcblk0p2 rw rootwait console=ttySAC1,115200 init=/linuxrc" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1 + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|L"Samsung Exynos4210-SMDK Board" + +# Use the Serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(c5deae31-fad2-4030-841b-cfc9644d2c5b)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10 + + # + # ARM L2x0 PCDs + # + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10502000 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + +# +# SEC +# + ArmPlatformPkg/Sec/Sec.inf + +# +# PEI Phase modules +# +!if $(EDK2_SKIP_PEICORE) == 1 + ArmPlatformPkg/PrePi/PeiMPCore.inf { + <LibraryClasses> + ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf + } +!else + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf + } + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + Nt32Pkg/BootModePei/BootModePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } +!endif + +# +# DXE +# + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + SamsungPlatformPkgOrigen/SmdkBoardPkg/FvbDxe/FvbDxe.inf + SamsungPlatformPkgOrigen/ExynosPkg/TimerDxe/TimerDxe.inf + + # + # Samsung specific Driver + # + ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + SamsungPlatformPkgOrigen/ExynosPkg/SDHCDxe/SDHCDxe.inf + SamsungPlatformPkgOrigen/ExynosPkg/Gpio/Gpio.inf{ + <LibraryClasses> + ExynosLib|SamsungPlatformPkgOrigen/ExynosPkg/Library/ExynosLib/ExynosLib.inf + } + + # + # Semi-hosting filesystem + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Application + # + EmbeddedPkg/Ebl/Ebl.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + ArmPlatformPkg/Bds/Bds.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.fdf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.fdf new file mode 100644 index 000000000..72574416a --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg-Exynos.fdf @@ -0,0 +1,316 @@ +# FLASH layout file for ARM VE. +# +# Copyright (c) 2011, Samsung Electronics Co. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + + +[FD.SmdkBoard_EFI] +BaseAddress = 0x43E00000|gArmTokenSpaceGuid.PcdFdBaseAddress +Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize +ErasePolarity = 1 +BlockSize = 0x00010000 +NumBlocks = 0x20 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00100000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +0x00110000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + #Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + #Size: 0x10000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xFFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + + + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf + INF SamsungPlatformPkgOrigen/ExynosPkg/TimerDxe/TimerDxe.inf + + # + # ACPI Support + # + + # + # Samsung specific Driver + # + INF SamsungPlatformPkgOrigen/ExynosPkg/SDHCDxe/SDHCDxe.inf + INF SamsungPlatformPkgOrigen/ExynosPkg/Gpio/Gpio.inf + # + # PCI EMULATION + # + # + # Semi-hosting filesystem + # + INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # USB HOST STACK + # + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF EmbeddedPkg/Ebl/Ebl.inf + + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional |.depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 |.efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 |.efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE |.efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional |.depex + TE TE |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional |.depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg.dec b/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg.dec new file mode 100644 index 000000000..f4afba182 --- /dev/null +++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/SmdkBoardPkg.dec @@ -0,0 +1,43 @@ +#/** @file +# Arm RealView EB package. +# +# Copyright (c) 2011, Samsung Electronics Co. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made +# available under the terms and conditions of the BSD License which +# accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = SmdkBoardPkg + PACKAGE_GUID = 4c9e432c-b84e-44fd-a796-f4545deec144 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER +# DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] +# Include # Root include for the package + +[Guids.common] #bc92b024-79f8-11e0-a039-0026b9733e2c + gSmdkBoardPkgTokenSpaceGuid = { 0xbc92b024, 0x79f8, 0x11e0, { 0xa0, 0x39, 0x00, 0x26, 0xb9, 0x73, 0x3e, 0x2c} } + +[PcdsFeatureFlag.common] + +[PcdsFixedAtBuild.common] + +[Protocols.common] |