Samsung/Origen: Move BSP to SamsungPlatformPkgOrigen dir

The Origen BSP clashes with the Arndale BSP.

Samsung have a plan to deliver a single BSP directory that supports both Origen and Arndale, but for now, I need to move one.

As Arndale is the "supported" one from Samsung, it get's priority.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

9 files changed, 1935 insertions, 0 deletions

diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
new file mode 100644
index 000000000..2fd2b8353
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
@@ -0,0 +1,78 @@
+/** @file
+  Template for ArmEb DebugAgentLib.
+
+  For ARM we reserve FIQ for the Debug Agent Timer. We don't care about
+  laytency as we only really need the timer to run a few times a second
+  (how fast can some one type a ctrl-c?), but it works much better if
+  the interrupt we are using to break into the debugger is not being
+  used, and masked, by the system.
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+
+#include <Library/DebugAgentTimerLib.h>
+
+#include <ArmEb/ArmEb.h>
+
+
+/**
+  Setup all the hardware needed for the debug agents timer.
+
+  This function is used to set up debug enviroment.
+
+**/
+VOID
+EFIAPI
+DebugAgentTimerIntialize (
+  VOID
+  )
+{
+  // Map Timer to FIQ
+}
+
+
+/**
+  Set the period for the debug agent timer. Zero means disable the timer.
+
+  @param[in] TimerPeriodMilliseconds    Frequency of the debug agent timer.
+
+**/
+VOID
+EFIAPI
+DebugAgentTimerSetPeriod (
+  IN  UINT32  TimerPeriodMilliseconds
+  )
+{
+  if (TimerPeriodMilliseconds == 0) {
+    // Disable timer and Disable FIQ
+    return;
+  }
+
+  // Set timer period and unmask FIQ
+}
+
+
+/**
+  Perform End Of Interrupt for the debug agent timer. This is called in the
+  interrupt handler after the interrupt has been processed.
+
+**/
+VOID
+EFIAPI
+DebugAgentTimerEndOfInterrupt (
+  VOID
+  )
+{
+  // EOI Timer interrupt for FIQ
+}
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
new file mode 100644
index 000000000..ee5438d2a
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
@@ -0,0 +1,37 @@
+#/** @file
+# Component description file for Base PCI Cf8 Library.
+#
+# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.
+#  Layers on top of an I/O Library instance.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmEbDebugAgentTimerLib
+  FILE_GUID                      = 80949BBB-68EE-4a4c-B434-D5DB5A232F0C
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = DebugAgentTimerLib|SEC BASE DXE_CORE
+
+
+[Sources.common]
+  DebugAgentTimerLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  SamsungPlatformPkg/SmdkBoardPkg/SmdkBoardPkg.dec
+
+[LibraryClasses]
+  IoLib
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoard.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoard.c
new file mode 100644
index 000000000..2f734f692
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoard.c
@@ -0,0 +1,210 @@
+/** @file
+*
+*  Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL341Dmc.h>
+#include <Platform/ArmPlatform.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+ARM_CORE_INFO mExynosMpCoreInfo[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  }
+};
+/**
+  Return if Trustzone is supported by your platform
+
+  A non-zero value must be returned if you want to support a Secure World on your platform.
+  ArmPlatformTrustzoneInit() will later set up the secure regions.
+  This function can return 0 even if Trustzone is supported by your processor. In this case,
+  the platform will continue to run in Secure World.
+
+  @return   A non-zero value if Trustzone supported.
+
+**/
+UINTN ArmPlatformTrustzoneSupported(VOID) {
+  // There is no Trustzone controllers (TZPC & TZASC) and no Secure Memory on RTSM
+	return TRUE;
+}
+
+/**
+  Initialize the Secure peripherals and memory regions
+
+  If Trustzone is supported by your platform then this function makes the required initialization
+  of the secure peripherals and memory regions.
+
+**/
+VOID ArmPlatformTrustzoneInit(VOID) {
+  UINT32  TZPCBase;
+  TZPCBase = PcdGet32(PcdTZPCBase) + TZPC0_OFFSET;
+  MmioWrite32((TZPCBase + 0x00),0x00);
+  MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF);
+
+  TZPCBase = PcdGet32(PcdTZPCBase) + TZPC1_OFFSET;
+  MmioWrite32((TZPCBase + 0x00),0x00);
+  MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF);
+
+  TZPCBase = PcdGet32(PcdTZPCBase) + TZPC2_OFFSET;
+  MmioWrite32((TZPCBase + 0x00),0x00);
+  MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF);
+
+  TZPCBase = PcdGet32(PcdTZPCBase) + TZPC3_OFFSET;
+  MmioWrite32((TZPCBase + 0x00),0x00);
+  MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF);
+
+  TZPCBase = PcdGet32(PcdTZPCBase) + TZPC4_OFFSET;
+  MmioWrite32((TZPCBase + 0x00),0x00);
+  MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF);
+
+
+  TZPCBase = PcdGet32(PcdTZPCBase) + TZPC5_OFFSET;
+  MmioWrite32((TZPCBase + 0x00),0x00);
+  MmioWrite32((TZPCBase +TZPC_DECPROT0SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT1SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT2SET_OFFSET),0xFF);
+  MmioWrite32((TZPCBase +TZPC_DECPROT3SET_OFFSET),0xFF);
+}
+
+/**
+  Remap the memory at 0x0
+
+  Some platform requires or gives the ability to remap the memory at the address 0x0.
+  This function can do nothing if this feature is not relevant to your platform.
+
+**/
+VOID ArmPlatformBootRemapping(VOID) {
+  // Disable memory remapping and return to normal mapping
+	MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
+}
+
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID ArmPlatformInitializeSystemMemory(VOID) {
+    // We do not need to initialize the System Memory on RTSM
+}
+
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+return RETURN_SUCCESS;
+}
+
+
+VOID
+ArmPlatformNormalInitialize (
+  VOID
+  ) {
+
+}
+
+VOID
+ArmPlatformSecExtraAction (
+  IN  UINTN         CoreId,
+  OUT UINTN*        JumpAddress
+  )
+{
+  *JumpAddress = PcdGet32(PcdFvBaseAddress);
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  *CoreCount    = sizeof(mExynosMpCoreInfo) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mExynosMpCoreInfo;
+
+  return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &mArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S
new file mode 100644
index 000000000..9dc7abdf9
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S
@@ -0,0 +1,635 @@
+/*
+ * Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution.  The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ */
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/PcdLib.h>
+#include <Platform/ArmPlatform.h>
+#include <AutoGen.h>
+
+/* Start of Code section */
+.text
+.align 3
+
+GCC_ASM_IMPORT(_SetupPrimaryCoreStack)
+GCC_ASM_EXPORT(ArmPlatformTZPCInitialized)
+GCC_ASM_EXPORT(ArmPlatformUARTInitialized)
+GCC_ASM_EXPORT(ArmPlatformIsClockInitialized)
+GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
+
+ASM_PFX(ArmPlatformTZPCInitialized):
+        ldr     r0, =Exynos4210_TZPC0_BASE
+        mov     r1, #0x0
+        str     r1, [r0]
+        mov     r1, #0xff
+        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+        ldr     r0, =Exynos4210_TZPC1_BASE
+        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+        ldr     r0, =Exynos4210_TZPC2_BASE
+        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+        ldr     r0, =Exynos4210_TZPC3_BASE
+        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+        ldr     r0, =Exynos4210_TZPC4_BASE
+        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+        ldr     r0, =Exynos4210_TZPC5_BASE
+        str     r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+        str     r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+        bx              lr
+
+ASM_PFX(ArmPlatformUARTInitialized):
+        ldr     r0, =0x11400000
+        ldr     r1, =0x22222222
+        str     r1, [r0]
+        ldr     r0, =0x11400020
+        ldr     r1, =0x222222
+        str     r1, [r0]
+
+        ldr     r0, =Exynos4210_CMU_BASE
+        ldr     r1, =CLK_SRC_PERIL0_VAL
+        ldr     r2, =CLK_SRC_PERIL0_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =CLK_DIV_PERIL0_VAL
+        ldr     r2, =CLK_DIV_PERIL0_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r0, =Exynos4210_UART_BASE
+        ldr     r1, =0x111
+        str     r1, [r0, #UFCON_OFFSET]
+
+        mov     r1, #0x3
+        str     r1, [r0, #ULCON_OFFSET]
+
+        ldr     r1, =0x3c5
+        str     r1, [r0, #UCON_OFFSET]
+
+        ldr     r1, =UART_UBRDIV_VAL
+        str     r1, [r0, #UBRDIV_OFFSET]
+
+        ldr     r1, =UART_UDIVSLOT_VAL
+        str     r1, [r0, #UDIVSLOT_OFFSET]
+
+        ldr     r1, =0x4c4c4c4c
+        str     r1, [r0, #UTXH_OFFSET]          // 'L'
+
+        ldr     r1, =0x4a4a4a4a
+        str     r1, [r0, #UTXH_OFFSET]          // 'J'
+
+        ldr     r1, =0x50505050
+        str     r1, [r0, #UTXH_OFFSET]          // 'P'
+
+        bx              lr
+
+
+ASM_PFX(ArmPlatformIsClockInitialized):
+        ldr     r0, =Exynos4210_CMU_BASE
+
+        ldr     r1, =0x0
+        ldr     r2, =CLK_SRC_CPU_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_1:
+        subs    r1, r1, #1
+        bne     cmu_1
+
+        ldr     r1, =CLK_DIV_CPU0_VAL
+        ldr     r2, =CLK_DIV_CPU0_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =CLK_DIV_CPU1_VAL
+        ldr     r2, =CLK_DIV_CPU1_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =0x10000
+        ldr     r2, =CLK_SRC_DMC_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_2:
+        subs    r1, r1, #1
+        bne     cmu_2
+
+        ldr     r1, =CLK_DIV_DMC0_VAL
+        ldr     r2, =CLK_DIV_DMC0_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =CLK_DIV_DMC1_VAL
+        ldr     r2, =CLK_DIV_DMC1_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =CLK_SRC_TOP0_VAL
+        ldr     r2, =CLK_SRC_TOP0_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =CLK_SRC_TOP1_VAL
+        ldr     r2, =CLK_SRC_TOP1_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+
+cmu_3:
+        subs    r1, r1, #1
+        bne     cmu_3
+
+        ldr     r1, =CLK_DIV_TOP_VAL
+        ldr     r2, =CLK_DIV_TOP_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =CLK_SRC_LEFTBUS_VAL
+        ldr     r2, =CLK_SRC_LEFTBUS_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_4:
+        subs    r1, r1, #1
+        bne     cmu_4
+
+        ldr     r1, =CLK_DIV_LEFRBUS_VAL
+        ldr     r2, =CLK_DIV_LEFTBUS_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =CLK_SRC_RIGHTBUS_VAL
+        ldr     r2, =CLK_SRC_RIGHTBUS_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_5:
+        subs    r1, r1, #1
+        bne     cmu_5
+
+        ldr     r1, =CLK_DIV_RIGHTBUS_VAL
+        ldr     r2, =CLK_DIV_RIGHTBUS_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =APLL_LOCK_VAL
+        ldr     r2, =APLL_LOCK_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =MPLL_LOCK_VAL
+        ldr     r2, =MPLL_LOCK_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =EPLL_LOCK_VAL
+        ldr     r2, =EPLL_LOCK_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =VPLL_LOCK_VAL
+        ldr     r2, =VPLL_LOCK_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =APLL_CON1_VAL
+        ldr     r2, =APLL_CON1_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =APLL_CON0_VAL
+        ldr     r2, =APLL_CON0_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =MPLL_CON1_VAL
+        ldr     r2, =MPLL_CON1_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =MPLL_CON0_VAL
+        ldr     r2, =MPLL_CON0_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =EPLL_CON1_VAL
+        ldr     r2, =EPLL_CON1_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =EPLL_CON0_VAL
+        ldr     r2, =EPLL_CON0_OFFSET
+        str     r1, [r0, r2]
+
+        ldr     r1, =VPLL_CON1_VAL
+        ldr     r2, =VPLL_CON1_OFFSET
+        str     r1, [r0, r2]
+        ldr     r1, =VPLL_CON0_VAL
+        ldr     r2, =VPLL_CON0_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_6:
+        subs    r1, r1, #1
+        bne     cmu_6
+
+        ldr     r1, =CLK_SRC_CPU_VAL_MOUTMPLLFOUT
+        ldr     r2, =CLK_SRC_CPU_OFFSET
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_7:
+        subs    r1, r1, #1
+        bne     cmu_7
+
+        ldr     r0, =Exynos4210_DMC_0_BASE
+
+        ldr     r1, =0x6910100A
+        ldr     r2, =DMC_PHYCONTROL0
+        str     r1, [r0, r2]
+        ldr     r1, =0x00000084
+        ldr     r2, =DMC_PHYCONTROL1
+        str     r1, [r0, r2]
+
+        ldr     r1, =0x6910100B
+
+        ldr     r2, =DMC_PHYCONTROL0
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_8:
+        subs    r1, r1, #1
+        bne     cmu_8
+
+        ldr     r1, =0x0000008C
+        ldr     r2, =DMC_PHYCONTROL1
+        str     r1, [r0, r2]
+        ldr     r1, =0x00000084
+        ldr     r2, =DMC_PHYCONTROL1
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_9:
+        subs    r1, r1, #1
+        bne     cmu_9
+
+        ldr     r0, =Exynos4210_DMC_1_BASE
+
+        ldr     r1, =0xe910100A
+
+        ldr     r2, =DMC_PHYCONTROL0
+        str     r1, [r0, r2]
+        ldr     r1, =0x00000084
+        ldr     r2, =DMC_PHYCONTROL1
+        str     r1, [r0, r2]
+
+        ldr     r1, =0xe910100B
+
+        ldr     r2, =DMC_PHYCONTROL0
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_10:
+        subs    r1, r1, #1
+        bne     cmu_10
+
+        ldr     r1, =0x0000008C
+        ldr     r2, =DMC_PHYCONTROL1
+        str     r1, [r0, r2]
+        ldr     r1, =0x00000084
+        ldr     r2, =DMC_PHYCONTROL1
+        str     r1, [r0, r2]
+
+        mov     r1, #Exynos4210_CMU_DELAY
+cmu_11:
+        subs    r1, r1, #1
+        bne     cmu_11
+
+        ldr     r0, =Exynos4210_DMC_0_BASE
+        ldr     r1, =0x0FFF30fa
+        ldr     r2, =DMC_CONCONTROL
+        str     r1, [r0, r2]
+        ldr     r0, =Exynos4210_DMC_1_BASE
+        ldr     r1, =0x0FFF30fa
+        ldr     r2, =DMC_CONCONTROL
+        str     r1, [r0, r2]
+
+        ldr     r0, =Exynos4210_DMC_0_BASE
+        ldr     r1, =0x00202537
+        ldr     r2, =DMC_MEMCONTROL
+        str     r1, [r0, r2]
+        ldr     r0, =Exynos4210_DMC_1_BASE
+        ldr     r1, =0x00202537
+        ldr     r2, =DMC_MEMCONTROL
+        str     r1, [r0, r2]
+
+        bx              lr
+
+/*
+ * Call at the beginning of the platform boot up
+ *
+ * This function allows the firmware platform to do extra actions at the early
+ * stage of the platform power up.
+ *
+ * Note: This function must be implemented in assembler
+ *	 as there is no stack set up yet
+ */
+ASM_PFX(ArmPlatformSecBootAction):
+	 bx    lr
+
+
+ASM_PFX(ArmPlatformSecBootMemoryInit):
+	 bx    lr
+
+/*
+ * Called at the early stage of the Boot phase to know if the memory has
+ * already been initialized. Running the code from the reset vector does
+ * not mean we start from cold boot. In some case, we can go through this
+ * code with the memory already initialized.
+ * Because this function is called at the early stage, the implementation
+ * must not use the stack. Its implementation must probably done in
+ * assembly to ensure this requirement.
+ *
+ * @return   Return the condition value into the 'Z' flag
+ */
+ASM_PFX(ArmPlatformIsMemoryInitialized):
+ /*
+  * Check if the memory has been already mapped,
+  * if so skipped the memory initialization
+  */
+	LoadConstantToReg (Exynos4210_DMC_0_BASE, r0)
+	ldr   r0, [r0, #0]
+        and   r0, r0, #0x20
+        cmp   r0, #0x00
+	bx	lr
+
+/*
+ * Initialize the memory where the initial stacks will reside
+ *
+ * This memory can contain the initial stacks (Secure and Secure Monitor
+ * stacks). In some platform, this region is already initialized and the
+ * implementation of this function can do nothing. This memory can also
+ * represent the Secure RAM.
+ * This function is called before the satck has been set up. Its
+ * implementation must ensure the stack pointer is not used (probably
+ * required to use assembly language)
+ */
+ASM_PFX(ArmPlatformInitializeBootMemory):
+/*
+ * Check if the Memory is already Initialized.
+ * If Initialized goto Stack setup
+ */
+	mov r10, lr
+	bl   ASM_PFX(ArmPlatformIsMemoryInitialized)
+	bne  skip_initmem
+
+	ldr r0, =0x10010350
+        mov r1, #1
+        str r1, [r0]
+
+/* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
+        ldr     r0, =Exynos4210_CMU_BASE
+        ldr     r1, =0x13113113
+        ldr     r2, =Exynos4210_CMU_DIV_DMC0
+        str     r1, [r0, r2]
+
+/* MIU Setting */
+        ldr     r0, =Exynos4210_MIU_BASE
+
+        ldr     r1, =0x20001507
+        str     r1, [r0, #0x400]
+        ldr     r1, =0x00000001
+        str     r1, [r0, #0xc00]
+
+/*****************************************************************/
+/*DREX0***********************************************************/
+/*****************************************************************/
+
+        ldr     r0, =Exynos4210_DMC_0_BASE
+
+        ldr     r1, =0xE3855503
+        str     r1, [r0, #DMC_PHYZQCONTROL]
+
+        ldr     r1, =0x71101008
+        str     r1, [r0, #DMC_PHYCONTROL0]
+
+        ldr     r1, =0x7110100A
+        str     r1, [r0, #DMC_PHYCONTROL0]
+
+        ldr     r1, =0x00000084
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x71101008
+        str     r1, [r0, #DMC_PHYCONTROL0]
+
+        ldr     r1, =0x0000008C
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x00000084
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x0000008C
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x00000084
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x00000000
+         str     r1, [r0, #DMC_PHYCONTROL2]
+
+        ldr     r1, =0x0FFF30da
+        str     r1, [r0, #DMC_CONCONTROL]
+
+        ldr     r1, =0x00202500
+        str     r1, [r0, #DMC_MEMCONTROL]
+
+        ldr     r1, =0x20f01223
+        str     r1, [r0, #DMC_MEMCONFIG0]
+
+        ldr     r1, =0xff000000
+        str     r1, [r0, #DMC_PRECHCONFIG]
+
+        ldr     r1, =0x0000005D
+        str     r1, [r0, #DMC_TIMINGAREF]
+
+        ldr     r1, =0x34498691
+        str     r1, [r0, #DMC_TIMINGROW]
+
+        ldr     r1, =0x36330306
+        str     r1, [r0, #DMC_TIMINGDATA]
+
+        ldr     r1, =0x50380365
+        str     r1, [r0, #DMC_TIMINGPOWER]
+
+        mov     r2, #Exynos4210_DMC_DELAY
+
+loop_2:
+        subs    r2, r2, #1
+        bne     loop_2
+        ldr     r1, =0x07000000
+        str     r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_3:
+        subs    r2, r2, #1
+        bne     loop_3
+        ldr     r1, =0x00071C00
+        str     r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_4:
+        subs    r2, r2, #1
+        bne     loop_4
+
+        ldr     r1, =0x00010BFC
+        str     r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_5:
+        subs    r2, r2, #1
+        bne     loop_5
+        ldr     r1, =0x00000488
+        str     r1, [r0, #DMC_DIRECTCMD]
+        ldr     r1, =0x00000810
+        str     r1, [r0, #DMC_DIRECTCMD]
+        ldr     r1, =0x00000C08
+        str     r1, [r0, #DMC_DIRECTCMD]
+
+/* get DMC density information */
+        ldr r1, =0x09010000
+        mov r3, #10
+loop_6:
+        str r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_7:
+        subs r2, r2, #1
+        bne     loop_7
+        ldr r6, [r0, #DMC_MRSTATUS]
+        subs r3, r3, #1
+        bne     loop_6
+        and r6, r6, #0x3c
+        lsr r6, r6, #2
+        cmp r6, #6
+        ldreq r1, =0x20e01323
+        ldrne r1, =0x20f01223
+        str     r1, [r0, #DMC_MEMCONFIG0]
+
+/*****************************************************************/
+/*DREX1***********************************************************/
+/*****************************************************************/
+        ldr     r0, =Exynos4210_DMC_1_BASE
+        ldr     r1, =0xE3855503
+        str     r1, [r0, #DMC_PHYZQCONTROL]
+
+        ldr     r1, =0x71101008
+        str     r1, [r0, #DMC_PHYCONTROL0]
+
+        ldr     r1, =0x7110100A
+        str     r1, [r0, #DMC_PHYCONTROL0]
+
+        ldr     r1, =0x00000084
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x71101008
+        str     r1, [r0, #DMC_PHYCONTROL0]
+
+        ldr     r1, =0x0000008C
+        str     r1, [r0, #DMC_PHYCONTROL1]
+        ldr     r1, =0x00000084
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x0000008C
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x00000084
+        str     r1, [r0, #DMC_PHYCONTROL1]
+
+        ldr     r1, =0x00000000
+        str     r1, [r0, #DMC_PHYCONTROL2]
+
+        ldr     r1, =0x0FFF30da
+        str     r1, [r0, #DMC_CONCONTROL]
+
+        ldr     r1, =0x00202500
+        str     r1, [r0, #DMC_MEMCONTROL]
+
+        ldr     r1, =0x40f01223
+        str     r1, [r0, #DMC_MEMCONFIG0]
+
+        ldr     r1, =0x20f01223
+        str     r1, [r0, #DMC_MEMCONFIG0]
+
+        ldr     r1, =0xff000000
+        str     r1, [r0, #DMC_PRECHCONFIG]
+
+        ldr     r1, =0x0000005D
+        str     r1, [r0, #DMC_TIMINGAREF]
+
+        ldr     r1, =0x34498691
+        str     r1, [r0, #DMC_TIMINGROW]
+
+        ldr     r1, =0x36330306
+        str     r1, [r0, #DMC_TIMINGDATA]
+
+        ldr     r1, =0x50380365
+        str     r1, [r0, #DMC_TIMINGPOWER]
+
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_8:
+        subs    r2, r2, #1
+        bne     loop_8
+        ldr     r1, =0x07000000
+        str     r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_9:
+        subs    r2, r2, #1
+        bne     loop_9
+        ldr     r1, =0x00071C00
+        str     r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_10:
+        subs    r2, r2, #1
+        bne     loop_10
+
+        ldr     r1, =0x00010BFC
+        str     r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_11:
+        subs    r2, r2, #1
+        bne     loop_11
+        ldr     r1, =0x00000488
+        str     r1, [r0, #DMC_DIRECTCMD]
+
+        ldr     r1, =0x00000810
+        str     r1, [r0, #DMC_DIRECTCMD]
+
+        ldr     r1, =0x00000C08
+        str     r1, [r0, #DMC_DIRECTCMD]
+
+/* get DMC density information */
+        ldr r1, =0x09010000
+        mov r3, #10
+loop_12:
+        str r1, [r0, #DMC_DIRECTCMD]
+        mov     r2, #Exynos4210_DMC_DELAY
+loop_13:
+        subs r2, r2, #1
+        bne     loop_13
+        ldr r7, [r0, #DMC_MRSTATUS]
+        subs r3, r3, #1
+        bne     loop_12
+        and r7, r7, #0x3c
+        lsr r7, r7, #2
+        cmp r7, #6
+        ldreq r1, =0x20e01323
+        ldrne r1, =0x20f01223
+        str     r1, [r0, #DMC_MEMCONFIG0]
+skip_initmem:
+	mov lr, r10
+	bx    lr
+
+.end
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm
new file mode 100644
index 000000000..7960f22ee
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm
@@ -0,0 +1,609 @@
+//
+//  Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/PcdLib.h>
+#include <Platform/ArmPlatform.h>
+#include <AutoGen.h>
+
+  INCLUDE AsmMacroIoLib.inc
+
+	EXPORT	ArmPlatformTZPCInitialized
+	EXPORT	ArmPlatformUARTInitialized
+  EXPORT	ArmPlatformIsClockInitialized
+  EXPORT  ArmPlatformIsMemoryInitialized
+  EXPORT  ArmPlatformInitializeBootMemory
+
+  PRESERVE8
+  AREA    ArmRealViewEbHelper, CODE, READONLY
+
+ArmPlatformTZPCInitialized
+	ldr	r0, =Exynos4210_TZPC0_BASE
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =Exynos4210_TZPC1_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =Exynos4210_TZPC2_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =Exynos4210_TZPC3_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =Exynos4210_TZPC4_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =Exynos4210_TZPC5_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	bx		lr
+
+ArmPlatformUARTInitialized
+	ldr	r0, =0x11400000
+	ldr	r1, =0x22222222
+	str	r1, [r0]
+	ldr	r0, =0x11400020
+	ldr	r1, =0x222222
+	str	r1, [r0]
+
+	ldr	r0, =Exynos4210_CMU_BASE
+	ldr	r1, =CLK_SRC_PERIL0_VAL
+	ldr	r2, =CLK_SRC_PERIL0_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =CLK_DIV_PERIL0_VAL
+	ldr	r2, =CLK_DIV_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r0, =Exynos4210_UART_BASE
+	ldr	r1, =0x111
+	str	r1, [r0, #UFCON_OFFSET]
+
+	mov	r1, #0x3
+	str	r1, [r0, #ULCON_OFFSET]
+
+	ldr	r1, =0x3c5
+	str	r1, [r0, #UCON_OFFSET]
+
+	ldr	r1, =UART_UBRDIV_VAL
+	str	r1, [r0, #UBRDIV_OFFSET]
+
+	ldr	r1, =UART_UDIVSLOT_VAL
+	str	r1, [r0, #UDIVSLOT_OFFSET]
+
+	ldr	r1, =0x4c4c4c4c
+	str	r1, [r0, #UTXH_OFFSET]		// 'L'
+
+	ldr	r1, =0x4a4a4a4a
+	str	r1, [r0, #UTXH_OFFSET]		// 'J'
+
+	ldr	r1, =0x50505050
+	str	r1, [r0, #UTXH_OFFSET]		// 'P'
+
+	bx		lr
+
+ArmPlatformIsClockInitialized
+	ldr	r0, =Exynos4210_CMU_BASE
+
+	ldr	r1, =0x0
+	ldr	r2, =CLK_SRC_CPU_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_1
+	subs	r1, r1, #1
+	bne	cmu_1
+
+	ldr	r1, =CLK_DIV_CPU0_VAL
+	ldr	r2, =CLK_DIV_CPU0_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =CLK_DIV_CPU1_VAL
+	ldr	r2, =CLK_DIV_CPU1_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =0x10000
+	ldr	r2, =CLK_SRC_DMC_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_2
+	subs	r1, r1, #1
+	bne	cmu_2
+
+	ldr	r1, =CLK_DIV_DMC0_VAL
+	ldr	r2, =CLK_DIV_DMC0_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =CLK_DIV_DMC1_VAL
+	ldr	r2, =CLK_DIV_DMC1_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =CLK_SRC_TOP0_VAL
+	ldr	r2, =CLK_SRC_TOP0_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =CLK_SRC_TOP1_VAL
+	ldr	r2, =CLK_SRC_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_3
+	subs	r1, r1, #1
+	bne	cmu_3
+
+	ldr	r1, =CLK_DIV_TOP_VAL
+	ldr	r2, =CLK_DIV_TOP_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =CLK_SRC_LEFTBUS_VAL
+	ldr	r2, =CLK_SRC_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_4
+	subs	r1, r1, #1
+	bne	cmu_4
+
+	ldr	r1, =CLK_DIV_LEFRBUS_VAL
+	ldr	r2, =CLK_DIV_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =CLK_SRC_RIGHTBUS_VAL
+	ldr	r2, =CLK_SRC_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_5
+	subs	r1, r1, #1
+	bne	cmu_5
+
+	ldr	r1, =CLK_DIV_RIGHTBUS_VAL
+	ldr	r2, =CLK_DIV_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =APLL_LOCK_VAL
+	ldr	r2, =APLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =MPLL_LOCK_VAL
+	ldr	r2, =MPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =EPLL_LOCK_VAL
+	ldr	r2, =EPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =VPLL_LOCK_VAL
+	ldr	r2, =VPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =APLL_CON1_VAL
+	ldr	r2, =APLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =APLL_CON0_VAL
+	ldr	r2, =APLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =MPLL_CON1_VAL
+	ldr	r2, =MPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =MPLL_CON0_VAL
+	ldr	r2, =MPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =EPLL_CON1_VAL
+	ldr	r2, =EPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =EPLL_CON0_VAL
+	ldr	r2, =EPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =VPLL_CON1_VAL
+	ldr	r2, =VPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =VPLL_CON0_VAL
+	ldr	r2, =VPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_6
+	subs	r1, r1, #1
+	bne	cmu_6
+
+	ldr	r1, =CLK_SRC_CPU_VAL_MOUTMPLLFOUT
+	ldr	r2, =CLK_SRC_CPU_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_7
+	subs	r1, r1, #1
+	bne	cmu_7
+
+	ldr	r0, =Exynos4210_DMC_0_BASE
+
+	ldr	r1, =0x6910100A
+	ldr	r2, =DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+
+	ldr	r1, =0x6910100B
+
+	ldr	r2, =DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_8
+	subs	r1, r1, #1
+	bne	cmu_8
+
+	ldr	r1, =0x0000008C
+	ldr	r2, =DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_9
+	subs	r1, r1, #1
+	bne	cmu_9
+
+	ldr	r0, =Exynos4210_DMC_1_BASE
+
+	ldr	r1, =0xe910100A
+
+	ldr	r2, =DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+
+	ldr	r1, =0xe910100B
+
+	ldr	r2, =DMC_PHYCONTROL0
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_10
+	subs	r1, r1, #1
+	bne	cmu_10
+
+	ldr	r1, =0x0000008C
+	ldr	r2, =DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+	ldr	r1, =0x00000084
+	ldr	r2, =DMC_PHYCONTROL1
+	str	r1, [r0, r2]
+
+	mov	r1, #Exynos4210_CMU_DELAY
+cmu_11
+	subs	r1, r1, #1
+	bne	cmu_11
+
+	ldr	r0, =Exynos4210_DMC_0_BASE
+	ldr	r1, =0x0FFF30fa
+	ldr	r2, =DMC_CONCONTROL
+	str	r1, [r0, r2]
+	ldr	r0, =Exynos4210_DMC_1_BASE
+	ldr	r1, =0x0FFF30fa
+	ldr	r2, =DMC_CONCONTROL
+	str	r1, [r0, r2]
+
+	ldr	r0, =Exynos4210_DMC_0_BASE
+	ldr	r1, =0x00202537
+	ldr	r2, =DMC_MEMCONTROL
+	str	r1, [r0, r2]
+	ldr	r0, =Exynos4210_DMC_1_BASE
+	ldr	r1, =0x00202537
+	ldr	r2, =DMC_MEMCONTROL
+	str	r1, [r0, r2]
+
+	bx		lr
+
+/**
+  Called at the early stage of the Boot phase to know if the memory has already been initialized
+
+  Running the code from the reset vector does not mean we start from cold boot. In some case, we
+  can go through this code with the memory already initialized.
+  Because this function is called at the early stage, the implementation must not use the stack.
+  Its implementation must probably done in assembly to ensure this requirement.
+
+  @return   Return the condition value into the 'Z' flag
+
+**/
+ArmPlatformIsMemoryInitialized
+  // Check if the memory has been already mapped, if so skipped the memory initialization
+  LoadConstantToReg (Exynos4210_DMC_0_BASE, r0)
+  ldr   r0, [r0, #0]
+  // Check Controller register is initialized or not by Auto-refresh bit
+	and		r0, r0, #0x20
+	cmp		r0, #0x20
+	bx		lr
+/**
+  Initialize the memory where the initial stacks will reside
+
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+  In some platform, this region is already initialized and the implementation of this function can
+  do nothing. This memory can also represent the Secure RAM.
+  This function is called before the satck has been set up. Its implementation must ensure the stack
+  pointer is not used (probably required to use assembly language)
+
+**/
+ArmPlatformInitializeBootMemory
+
+//Async bridge configuration at CPU_core(1: half_sync 0: full_sync)
+	ldr r0, =0x10010350
+	mov r1, #1
+	str r1, [r0]
+
+//CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC
+	ldr	r0, =Exynos4210_CMU_BASE
+	ldr	r1, =0x13113113
+	ldr	r2, =Exynos4210_CMU_DIV_DMC0
+	str	r1, [r0, r2]
+
+//MIU Setting
+	ldr	r0, =Exynos4210_MIU_BASE
+
+	ldr	r1, =0x20001507
+	str	r1, [r0, #0x400]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xc00]
+
+/*****************************************************************/
+/*DREX0***********************************************************/
+/*****************************************************************/
+
+	ldr	r0, =Exynos4210_DMC_0_BASE
+
+	ldr	r1, =0xE3855503
+	str	r1, [r0, #DMC_PHYZQCONTROL]
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL2]
+
+	ldr	r1, =0x0FFF30da
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	ldr	r1, =0x00202500
+	str	r1, [r0, #DMC_MEMCONTROL]
+
+	ldr	r1, =0x20f01223
+	str	r1, [r0, #DMC_MEMCONFIG0]
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #DMC_PRECHCONFIG]
+
+	ldr	r1, =0x0000005D
+	str	r1, [r0, #DMC_TIMINGAREF]
+
+	ldr	r1, =0x34498691
+	str	r1, [r0, #DMC_TIMINGROW]
+
+	ldr	r1, =0x36330306
+	str	r1, [r0, #DMC_TIMINGDATA]
+
+	ldr	r1, =0x50380365
+	str	r1, [r0, #DMC_TIMINGPOWER]
+
+	mov	r2, #Exynos4210_DMC_DELAY
+
+loop_2
+	subs	r2, r2, #1
+	bne	loop_2
+	ldr	r1, =0x07000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_3
+	subs	r2, r2, #1
+	bne	loop_3
+	ldr	r1, =0x00071C00
+	str	r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_4
+	subs	r2, r2, #1
+	bne	loop_4
+
+	ldr	r1, =0x00010BFC
+	str	r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_5
+	subs	r2, r2, #1
+	bne	loop_5
+	ldr	r1, =0x00000488
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00000810
+	str	r1, [r0, #DMC_DIRECTCMD]
+	ldr	r1, =0x00000C08
+	str	r1, [r0, #DMC_DIRECTCMD]
+#if 1
+//get DMC density information
+	ldr r1, =0x09010000
+	mov r3, #10
+loop_6
+	str r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_7
+	subs r2, r2, #1
+	bne	loop_7
+	ldr r6, [r0, #DMC_MRSTATUS]
+	subs r3, r3, #1
+	bne	loop_6
+	and r6, r6, #0x3c
+	lsr r6, r6, #2
+	cmp r6, #6
+	ldreq r1, =0x20e01323
+	ldrne r1, =0x20f01223
+	str	r1, [r0, #DMC_MEMCONFIG0]
+#endif
+
+/*****************************************************************/
+/*DREX1***********************************************************/
+/*****************************************************************/
+	ldr	r0, =Exynos4210_DMC_1_BASE
+	ldr	r1, =0xE3855503
+	str	r1, [r0, #DMC_PHYZQCONTROL]
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x0000008C
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x00000084
+	str	r1, [r0, #DMC_PHYCONTROL1]
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL2]
+
+	ldr	r1, =0x0FFF30da
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	ldr	r1, =0x00202500
+	str	r1, [r0, #DMC_MEMCONTROL]
+
+	ldr	r1, =0x40f01223
+	str	r1, [r0, #DMC_MEMCONFIG0]
+
+	ldr	r1, =0x20f01223
+	str	r1, [r0, #DMC_MEMCONFIG0]
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #DMC_PRECHCONFIG]
+
+	ldr	r1, =0x0000005D
+	str	r1, [r0, #DMC_TIMINGAREF]
+
+	ldr	r1, =0x34498691
+	str	r1, [r0, #DMC_TIMINGROW]
+
+	ldr	r1, =0x36330306
+	str	r1, [r0, #DMC_TIMINGDATA]
+
+	ldr	r1, =0x50380365
+	str	r1, [r0, #DMC_TIMINGPOWER]
+
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_8
+	subs	r2, r2, #1
+	bne	loop_8
+	ldr	r1, =0x07000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_9
+	subs	r2, r2, #1
+	bne	loop_9
+	ldr	r1, =0x00071C00
+	str	r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_10
+	subs	r2, r2, #1
+	bne	loop_10
+
+	ldr	r1, =0x00010BFC
+	str	r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_11
+	subs	r2, r2, #1
+	bne	loop_11
+	ldr	r1, =0x00000488
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	ldr	r1, =0x00000810
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	ldr	r1, =0x00000C08
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+#if 1
+// get DMC density information
+	ldr r1, =0x09010000
+	mov r3, #10
+loop_12
+	str r1, [r0, #DMC_DIRECTCMD]
+	mov	r2, #Exynos4210_DMC_DELAY
+loop_13
+	subs r2, r2, #1
+	bne	loop_13
+	ldr r7, [r0, #DMC_MRSTATUS]
+	subs r3, r3, #1
+	bne	loop_12
+	and r7, r7, #0x3c
+	lsr r7, r7, #2
+	cmp r7, #6
+	ldreq r1, =0x20e01323
+	ldrne r1, =0x20f01223
+	str	r1, [r0, #DMC_MEMCONFIG0]
+#endif
+
+  bx    lr
+
+  END
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf
new file mode 100644
index 000000000..0ef5c8818
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardLib.inf
@@ -0,0 +1,49 @@
+#/* @file
+#  Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SmdkBoardLib
+  FILE_GUID                      = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  SamsungPlatformPkg/ExynosPkg/ExynosPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+ 
+
+[Sources.common]
+  SmdkBoard.c
+  SmdkBoardMem.c
+
+[Protocols]
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdStandalone
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+  gExynosPkgTokenSpaceGuid.PcdTZPCBase
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardMem.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardMem.c
new file mode 100644
index 000000000..db1a163c8
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardMem.c
@@ -0,0 +1,210 @@
+/** @file
+*
+*  Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+#define DDR_ATTRIBUTES_SECURE_CACHED    ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK
+#define DDR_ATTRIBUTES_SECURE_UNCACHED  ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED
+
+#if 0
+/**
+  Return the information about the memory region in permanent memory used by PEI
+
+  One of the PEI Module must install the permament memory used by PEI. This function returns the
+  information about this region for your platform to this PEIM module.
+
+  @param[out]   PeiMemoryBase       Base of the memory region used by PEI core and modules
+  @param[out]   PeiMemorySize       Size of the memory region used by PEI core and modules
+
+**/
+VOID ArmPlatformGetPeiMemory (
+    OUT UINTN*                                   PeiMemoryBase,
+    OUT UINTN*                                   PeiMemorySize
+    ) {
+    ASSERT((PeiMemoryBase != NULL) && (PeiMemorySize != NULL));
+
+   // *PeiMemoryBase = ARM_EB_DRAM_BASE + ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;
+   // *PeiMemorySize = ARM_EB_EFI_MEMORY_REGION_SZ;
+    *PeiMemoryBase = PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdSystemMemoryFixRegionSize);
+    *PeiMemorySize = PcdGet32(PcdSystemMemoryUefiRegionSize);
+}
+#endif
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {
+//    UINT32                        val32;
+    UINT32                        CacheAttributes;
+    ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+
+    ASSERT(VirtualMemoryMap != NULL);
+
+    VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 5);
+    if (VirtualMemoryTable == NULL) {
+        return;
+    }
+
+    if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+        CacheAttributes = DDR_ATTRIBUTES_CACHED;
+    } else {
+        CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+    }
+
+    // SFR
+    VirtualMemoryTable[0].PhysicalBase = 0x00000000;
+    VirtualMemoryTable[0].VirtualBase  = 0x00000000;
+    VirtualMemoryTable[0].Length       = 0x20000000;
+    VirtualMemoryTable[0].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+    // DDR
+    VirtualMemoryTable[1].PhysicalBase = 0x40000000;
+    VirtualMemoryTable[1].VirtualBase  = 0x40000000;
+    VirtualMemoryTable[1].Length       = 0x0e000000;
+    VirtualMemoryTable[1].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
+
+		// framebuffer
+    VirtualMemoryTable[2].PhysicalBase = 0x4e000000;
+    VirtualMemoryTable[2].VirtualBase  = 0x4e000000;
+    VirtualMemoryTable[2].Length       = 0x02000000;
+    VirtualMemoryTable[2].Attributes   = DDR_ATTRIBUTES_UNCACHED;
+
+    VirtualMemoryTable[3].PhysicalBase = 0x50000000;
+    VirtualMemoryTable[3].VirtualBase  = 0x50000000;
+    VirtualMemoryTable[3].Length       = 0xb0000000;
+    VirtualMemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
+
+    // End of Table
+    VirtualMemoryTable[4].PhysicalBase = 0;
+    VirtualMemoryTable[4].VirtualBase  = 0;
+    VirtualMemoryTable[4].Length       = 0;
+    VirtualMemoryTable[4].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+    *VirtualMemoryMap = VirtualMemoryTable;
+}
+
+
+
+#if 0
+/**
+  Return the EFI Memory Map of your platform
+
+  This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
+  Descriptor HOBs used by DXE core.
+
+  @param[out]   EfiMemoryMap        Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
+                                    EFI Memory region. This array must be ended by a zero-filled entry
+
+**/
+VOID ArmPlatformGetEfiMemoryMap (
+    OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
+) {
+    EFI_RESOURCE_ATTRIBUTE_TYPE     Attributes;
+    UINT64                          MemoryBase;
+    UINTN                           Index = 0;
+    ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR  *EfiMemoryTable;
+
+    ASSERT(EfiMemoryMap != NULL);
+
+    EfiMemoryTable = (ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR) * 6);
+
+    Attributes =
+    (
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED
+    );
+    MemoryBase = PcdGet32(PcdSystemMemoryBase);//ARM_EB_DRAM_BASE;
+
+    // Memory Reserved for fixed address allocations (such as Exception Vector Table)
+    EfiMemoryTable[Index].ResourceAttribute = Attributes;
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;
+    EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdSystemMemoryFixRegionSize);//ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;
+
+    MemoryBase += PcdGet32(PcdSystemMemoryFixRegionSize);//ARM_EB_EFI_FIX_ADDRESS_REGION_SZ;
+
+    // Memory declared to PEI as permanent memory for PEI and DXE
+    EfiMemoryTable[++Index].ResourceAttribute = Attributes;
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;
+    EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdSystemMemoryUefiRegionSize);//ARM_EB_EFI_MEMORY_REGION_SZ;
+
+    MemoryBase += PcdGet32(PcdSystemMemoryUefiRegionSize);//ARM_EB_EFI_MEMORY_REGION_SZ;
+
+    // We must reserve the memory used by the Firmware Volume copied in DRAM at 0x80000000
+    if (!PcdGet32(PcdStandalone)) {
+        // Chunk between the EFI Memory region and the firmware
+        EfiMemoryTable[++Index].ResourceAttribute = Attributes;
+        EfiMemoryTable[Index].PhysicalStart = MemoryBase;
+        //EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdBaseAddress) - MemoryBase;
+        EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdBaseAddress) - MemoryBase;
+
+        // Chunk reserved by the firmware in DRAM
+        EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_PRESENT);
+        //EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdEmbeddedFdBaseAddress);
+        EfiMemoryTable[Index].PhysicalStart = PcdGet32(PcdNormalFdBaseAddress);
+        //EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdEmbeddedFdSize);
+        EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdNormalFdSize);
+
+       //MemoryBase = PcdGet32(PcdEmbeddedFdBaseAddress) + PcdGet32(PcdEmbeddedFdSize);
+        MemoryBase = PcdGet32(PcdNormalFdBaseAddress) + PcdGet32(PcdNormalFdSize);
+    }
+
+    // We allocate all the remain memory as untested system memory
+    EfiMemoryTable[++Index].ResourceAttribute = Attributes & (~EFI_RESOURCE_ATTRIBUTE_TESTED);
+    EfiMemoryTable[Index].PhysicalStart = MemoryBase;
+    EfiMemoryTable[Index].NumberOfBytes = PcdGet32(PcdSystemMemorySize) - (MemoryBase-PcdGet32(PcdSystemMemoryBase));
+
+    EfiMemoryTable[++Index].ResourceAttribute = 0;
+    EfiMemoryTable[Index].PhysicalStart = 0;
+    EfiMemoryTable[Index].NumberOfBytes = 0;
+
+    *EfiMemoryMap = EfiMemoryTable;
+}
+#endif
+
+/**
+  Return the EFI Memory Map of your platform
+
+  This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
+  Descriptor HOBs used by DXE core.
+
+  @param[out]   EfiMemoryMap        Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
+                                    EFI Memory region. This array must be ended by a zero-filled entry
+
+**/
+EFI_STATUS
+ArmPlatformGetAdditionalSystemMemory (
+    OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
+) {
+
+//  ArmPlatformGetEfiMemoryMap(EfiMemoryMap);
+  //return EFI_SUCCESS;
+  return EFI_UNSUPPORTED;
+}
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSec.c b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSec.c
new file mode 100644
index 000000000..9471df2fb
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSec.c
@@ -0,0 +1,57 @@
+/** @file
+*
+*  Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL310L2Cache.h>
+#include <Drivers/PL341Dmc.h>
+
+
+/**
+  Initialize controllers that must setup at the early stage
+
+  Some peripherals must be initialized in Secure World.
+  For example, some L2x0 requires to be initialized in Secure World
+ ============ added by girish to resolve compile error=================
+**/
+
+VOID
+ArmPlatformSecInitialize (
+  VOID
+  ) {
+  // The L2x0 controller must be intialize in Secure World
+	L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
+      PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
+      PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
+      0,~0, // Use default setting for the Auxiliary Control Register
+      FALSE);
+
+}
+
+/**
+  Initialize the Secure peripherals and memory regions
+
+  If Trustzone is supported by your platform then this function makes the required initialization
+  of the secure peripherals and memory regions.
+
+**/
+VOID
+ArmPlatformSecTrustzoneInit (
+  IN  UINTN                     MpId
+  )
+{
+return;
+}
diff --git a/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf
new file mode 100644
index 000000000..f8f7228db
--- /dev/null
+++ b/SamsungPlatformPkgOrigen/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardSecLib.inf
@@ -0,0 +1,50 @@
+#/* @file
+#  Copyright (c) 2011, Samsung Electronics Co. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SmdkBoardSecLib
+  FILE_GUID                      = 6e02ebe0-1d96-11e0-b9cb-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  SamsungPlatformPkg/ExynosPkg/ExynosPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  L2X0CacheLib
+
+[Sources.common]
+  SmdkBoard.c
+  SmdkBoardSec.c
+  SmdkBoardHelper.asm   | RVCT
+  SmdkBoardHelper.S     | GCC
+
+[Protocols]
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+  gArmTokenSpaceGuid.PcdL2x0ControllerBase
+  gExynosPkgTokenSpaceGuid.PcdTZPCBase