Samsung/Arndale: Fix compilation errors

This patch fixes the build breakage issue for Arndale BSP due to the
patch "ArmPlatformPkg/ArmPlatformLib: Added support for
ArmPlatformIsPrimaryCore()"

8 files changed, 49 insertions, 48 deletions

diff --git a/SamsungPlatformPkg/ArndaleBoardPkg/Library/ArndaleBoardLib/Exynos5250/BoardHelper.S b/SamsungPlatformPkg/ArndaleBoardPkg/Library/ArndaleBoardLib/Exynos5250/BoardHelper.S
index 1975e6517..d5858630f 100644
--- a/SamsungPlatformPkg/ArndaleBoardPkg/Library/ArndaleBoardLib/Exynos5250/BoardHelper.S
+++ b/SamsungPlatformPkg/ArndaleBoardPkg/Library/ArndaleBoardLib/Exynos5250/BoardHelper.S
@@ -14,6 +14,7 @@
 #include <AsmMacroIoLib.h>
 #include <Base.h>
 #include <Library/PcdLib.h>
+#include <Library/ArmLib.h>
 #include <AutoGen.h>
 #.include AsmMacroIoLib.inc
 
@@ -23,6 +24,9 @@
 .align 2
 
 GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
 
 # IN None
 # OUT r0 = SCU Base Address
@@ -68,4 +72,25 @@ _Return:
   ldmfd SP!, {r1-r2}
   bx lr
 
+ASM_PFX(ArmPlatformIsPrimaryCore):
+  #last 2 bit of mpid register in 5250 is CPU ID
+  ldr   r1, =0x3
+  and   r0, r0, r1
+  #id for core0 should be 0
+  ldr   r1, =0x0
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  mov pc,  lr
+
+ASM_PFX(ArmPlatformGetCorePosition):
+  and  r1, r0, #0x03 //cpu core mask last 2 bits
+  and  r0, r0, #(0x0f<<8) //cpu cluster mask bit 8-11
+  add  r0, r1, r0, LSR #7
+  mov pc, lr
+
+
+ASM_PFX(ArmPlatformPeiBootAction):
+  mov pc, lr
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED 
diff --git a/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.dsc b/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.dsc
index 941c6e55c..ade299702 100755
--- a/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.dsc
+++ b/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.dsc
@@ -56,7 +56,6 @@
 [BuildOptions]
   RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform
 
-  #GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a8 -I$(WORKSPACE)/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform
   GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform
 
   XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/SamsungPlatformPkg/ExynosPkg/Exynos5250/Include/Platform
@@ -242,7 +241,6 @@
   SamsungPlatformPkg/ExynosPkg/Exynos5250/MemoryInitPei/MemoryInitPeim.inf
   ArmPkg/Drivers/CpuPei/CpuPei.inf
   IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
-  #Nt32Pkg/BootModePei/BootModePei.inf
   MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
     <LibraryClasses>
@@ -268,22 +266,17 @@
   MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
-  #MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-  #MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
   MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
   EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
   EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
 
   MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  #MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
   MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
   MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
-  #EmbeddedPkg/SerialDxe/SerialDxe.inf
 
   MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  #MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
 
   SamsungPlatformPkg/ArndaleBoardPkg/FvbDxe/FvbDxe.inf
   SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/TimerDxe/TimerDxe.inf
@@ -318,9 +311,6 @@
   #
   # Application
   #
-  #SamsungPlatformPkg/Apps/TestApps/HashServicesTest/HashServicesTest.inf
-  #SamsungPlatformPkg/Apps/TestApps/RngServicesTest/RngServicesTest.inf
-
   #
   # Bds
   #
@@ -346,9 +336,7 @@
   # usb host : ehci + bus + pci_emul + mass_storage
   #
   SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/PciEmulation/PciEmulation.inf
-  #SamsungPlatformPkg/ExynosPkg/Exynos5250/OhciDxe/OhciDxe.inf
   MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
-  #MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
   MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
   MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
 
@@ -363,8 +351,6 @@
     <LibraryClasses>
       LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
   }
-  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
-  #MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
 
   MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
   SamsungPlatformPkg/Apps/Tools/fwupdate/fwupdate_5250.inf
@@ -372,9 +358,7 @@
   #
   # Crypto for Exynos
   #
-  #SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/HashDxe/HashDxe.inf
 
   #
   # Rng for Exynos
   #
-  #SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/RngDxe/RngDxe.inf
diff --git a/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.fdf b/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.fdf
index 8b5a5a727..9bccd79bf 100755
--- a/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.fdf
+++ b/SamsungPlatformPkg/ArndaleBoardPkg/arndale-Exynos5250.fdf
@@ -120,7 +120,6 @@ READ_STATUS        = TRUE
 READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 
-  #INF ArmPlatformPkg/Sec/Sec.inf
   INF SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.inf
 
 
@@ -155,8 +154,6 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
-  #INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-  #INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
   INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
   INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
@@ -166,14 +163,10 @@ READ_LOCK_STATUS   = TRUE
   # Multiple Console IO support
   #
   INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  #INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
   INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
   INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
-  #INF EmbeddedPkg/SerialDxe/SerialDxe.inf
-
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  #INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
 
 !ifdef $(EXYNOS5250_EVT1)
   INF SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicDxe.inf
@@ -207,9 +200,7 @@ READ_LOCK_STATUS   = TRUE
   # USB HOST STACK
   #
   INF SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/PciEmulation/PciEmulation.inf
-  #INF SamsungPlatformPkg/ExynosPkg/Exynos5250/OhciDxe/OhciDxe.inf
   INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
-  #INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
 
@@ -223,20 +214,14 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
   INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
   INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
-  INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
-  #INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
 
   # Crypto for Exynos
   #
-  #INF SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/HashDxe/HashDxe.inf
-  #INF SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/RngDxe/RngDxe.inf
 
   #
   # UEFI application (Shell Embedded Boot Loader)
   #
   INF ShellBinPkg/UefiShell/UefiShell.inf 
-  #INF SamsungPlatformPkg/Apps/TestApps/HashServicesTest/HashServicesTest.inf
-  #INF SamsungPlatformPkg/Apps/TestApps/RngServicesTest/RngServicesTest.inf
 
   #
   # Bds
diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSec.c b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSec.c
index f7b6d7c3a..82ecfde6e 100644
--- a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSec.c
+++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSec.c
@@ -15,6 +15,7 @@
 #include <Base.h>
 #include <Library/ArmLib.h>
 #include <Library/DebugLib.h>
+#include <Library/ArmPlatformLib.h>
 #include <Library/IoLib.h>
 #include <Library/ArmGicLib.h>
 
@@ -50,7 +51,7 @@ ArmGicSetupNonSecure (
   }
 
   // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
-  if (IS_PRIMARY_CORE(MpId)) {
+  if (ArmPlatformIsPrimaryCore (MpId)) {
     // Ensure all GIC interrupts are Non-Secure
     for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {
       MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSecLib.inf b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSecLib.inf
index 9e1fd0966..ab399b4fb 100644
--- a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSecLib.inf
+++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Drivers/Gic400Dxe/PL390GicSecLib.inf
@@ -25,7 +25,9 @@
 
 [Packages]
   ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
   MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
 
 [LibraryClasses]
   ArmLib
@@ -33,6 +35,3 @@
   IoLib
   PcdLib
 
-[FixedPcd.common]
-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
-  gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.c b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.c
index 549171b3b..3c4f4983f 100644
--- a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.c
+++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.c
@@ -21,6 +21,7 @@
 #include <Library/ArmGicLib.h>
 #include <Library/ArmCpuLib.h>
 #include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
 #include "SecInternal.h"
 #include "Smc.h"
 
@@ -94,7 +95,7 @@ CEntryPoint (
   }
 
   // Primary CPU clears out the SCU tag RAMs, secondaries wait
-  if (IS_PRIMARY_CORE(MpId)) {
+  if (ArmPlatformIsPrimaryCore (MpId)) {
     if (ArmIsMpCore()) {
       // Is UEFI built as it is assumed that TZSW is running?
       // PcdTrustzoneSupport==1: YES.
@@ -174,7 +175,7 @@ TrustedWorldInitialization (
   ArmPlatformSecTrustzoneInit (MpId);
 
   // Setup the Trustzone Chipsets
-  if (IS_PRIMARY_CORE(MpId)) {
+  if (ArmPlatformIsPrimaryCore (MpId)) {
     if (ArmIsMpCore()) {
       // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
       ArmCallSEV ();
diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.inf b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.inf
index 854b26971..1cda8c3ad 100644
--- a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.inf
+++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/Sec.inf
@@ -62,9 +62,6 @@
   gArmTokenSpaceGuid.PcdArmNsacr
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition
 
-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
-  gArmTokenSpaceGuid.PcdArmPrimaryCore
-
   gArmTokenSpaceGuid.PcdSecureFvBaseAddress
   gArmTokenSpaceGuid.PcdSecureFvSize
 
diff --git a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/SecEntryPoint.S b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/SecEntryPoint.S
index 08a893cb0..aecbc939f 100644
--- a/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/SecEntryPoint.S
+++ b/SamsungPlatformPkg/ExynosPkg/Exynos5250/Sec/SecEntryPoint.S
@@ -14,12 +14,14 @@
 #include <AutoGen.h>
 #include <AsmMacroIoLib.h>
 #include <Library/ArmPlatformLib.h>
+#include <ArmPlatform.h>
 #include "SecInternal.h"
 
 .text
 .align 3
 
 GCC_ASM_IMPORT(CEntryPoint)
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
 GCC_ASM_IMPORT(CopyFirmwareFromEMMC)
 GCC_ASM_IMPORT(CopyFirmwareFromSDMMC)
 GCC_ASM_IMPORT(ArmPlatformClockInitialize)
@@ -36,6 +38,16 @@ GCC_ASM_EXPORT(_ModuleEntryPoint)
 SecStartupAddr:	    .word       ASM_PFX(_SecEntryFromTzsw)
 StartupAddr:        .word       ASM_PFX(CEntryPoint)
 
+// Convert the (ClusterId,CoreId) into a Core Position
+// 0x0F03 is the magic value for ARM_CORE_MASK | ARM_CLUSTER_MASK
+//Core is 0-1 bits and cluster is 8-11 bits
+#define GetCorePositionFromMpId(Pos, MpId, Tmp)    \
+	ldr   Tmp, =0x0F03 ;                             \
+	and   MpId, Tmp ;                                \
+	lsr   Pos, MpId, #6 ;                            \
+	and   Tmp, MpId, #3 ;                            \
+	add   Pos, Pos, Tmp
+
 // Reserve a region at the top of the IRAM Core stack
 // for Global variables for the XIP phase
 #define SetiRamStack(StackTop, GlobalSize, Tmp)  \
@@ -85,13 +97,13 @@ ASM_PFX(_ModuleEntryPoint):
 _IdentifyCpu:
   // Identify CPU ID
   bl   ASM_PFX(ArmReadMpidr)
-  // Get ID of this CPU in Multicore system
-  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
-  and  r5, r0, r1
+ // Keep a copy of the MpId register value
+  mov   r5, r0
 
   // Is it the Primary Core ?
-  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
-  cmp  r5, r3
+  bl   ASM_PFX(ArmPlatformIsPrimaryCore)
+  cmp   r0, #1
+
   // Only the primary core initialize the memory (SMC)
   beq  _InitMem
 
@@ -119,9 +131,6 @@ _InitMem:
 
   bl  ASM_PFX(ArmPlatformSecBootMemoryInit)
 
-  // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
-  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
-
 _SetupPrimaryCoreStack:
   // Get the top of the primary stacks (and the base of the secondary stacks)
   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)