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authorpkandel <pkandel@6f19259b-4bc3-4df7-8a09-765794883524>2009-06-04 16:16:15 +0000
committerpkandel <pkandel@6f19259b-4bc3-4df7-8a09-765794883524>2009-06-04 16:16:15 +0000
commit1a2f870c9babe077c2d3abea23b6e8e044778341 (patch)
treedb545c66ef72b32da3dbd2406b256c3430702af0 /MdePkg/Include/Library/CacheMaintenanceLib.h
parent7076244ef4005642712f32591abbd8188d6b6f40 (diff)
Second set of changes based on a review of the code comments in the Include directory for typos, grammar issues, and language clarity.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8467 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Include/Library/CacheMaintenanceLib.h')
-rw-r--r--MdePkg/Include/Library/CacheMaintenanceLib.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/MdePkg/Include/Library/CacheMaintenanceLib.h b/MdePkg/Include/Library/CacheMaintenanceLib.h
index a575ec2fc..eec774512 100644
--- a/MdePkg/Include/Library/CacheMaintenanceLib.h
+++ b/MdePkg/Include/Library/CacheMaintenanceLib.h
@@ -39,7 +39,7 @@ InvalidateInstructionCache (
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
- invalidating the specified range. If Length is 0, the no instruction cache
+ invalidating the specified range. If Length is 0, then no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@@ -88,7 +88,7 @@ WriteBackInvalidateDataCache (
line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified
- range. If Length is 0, the no data cache lines are written back and
+ range. If Length is 0, then no data cache lines are written back and
invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@@ -136,7 +136,7 @@ WriteBackDataCache (
cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range.
- If Length is 0, the no data cache lines are written back. This function may
+ If Length is 0, then no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned.