ArmPlatformPkg: Introduced 'ArmPlatformSecLib'

The function only used in Secure Firmware used to be mixed with
the Non-Secure/Normal functions in ArmPlatformLib.
When the Secure Firmware was not required for some platforms (eg:
BeagleBoard), these functions were empty functions.
This new interface has been created to clean the ArmPlatformLib
interface between the SEC and PEI phases.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13260 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 12 insertions, 27 deletions

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 00293f0d0..f9746ad89 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -19,7 +19,6 @@
 #include <Library/BaseMemoryLib.h>
 #include <Library/SerialPortLib.h>
 #include <Library/ArmGicLib.h>
-#include <Library/ArmCpuLib.h>
 
 #include "SecInternal.h"
 
@@ -50,7 +49,11 @@ CEntryPoint (
   if (FixedPcdGet32 (PcdVFPEnabled)) {
     ArmEnableVFP();
   }
-	
+
+  // Initialize peripherals that must be done at the early stage
+  // Example: Some L2 controller, interconnect, clock, DMC, etc
+  ArmPlatformSecInitialize (MpId);
+
   // Primary CPU clears out the SCU tag RAMs, secondaries wait
   if (IS_PRIMARY_CORE(MpId)) {
     if (ArmIsMpCore()) {
@@ -93,19 +96,6 @@ CEntryPoint (
   // Enable Full Access to CoProcessors
   ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
 
-  if (IS_PRIMARY_CORE(MpId)) {
-    // Initialize peripherals that must be done at the early stage
-    // Example: Some L2x0 controllers must be initialized in Secure World
-    ArmPlatformSecInitialize ();
-
-    // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
-    // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
-    if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
-      // Initialize system memory (DRAM)
-      ArmPlatformInitializeSystemMemory ();
-    }
-  }
-
   // Test if Trustzone is supported on this platform
   if (FixedPcdGetBool (PcdTrustzoneSupport)) {
     if (ArmIsMpCore()) {
@@ -155,7 +145,7 @@ TrustedWorldInitialization (
   ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
 
   // Initialize platform specific security policy
-  ArmPlatformTrustzoneInit (MpId);
+  ArmPlatformSecTrustzoneInit (MpId);
 
   // Setup the Trustzone Chipsets
   if (IS_PRIMARY_CORE(MpId)) {
diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index 1aa7fd122..a9ef05607 100644
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -38,7 +38,7 @@
 [LibraryClasses]

   ArmCpuLib

   ArmLib

-  ArmPlatformLib

+  ArmPlatformSecLib

   ArmTrustedMonitorLib

   BaseLib

   DebugLib

diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.S b/ArmPlatformPkg/Sec/SecEntryPoint.S
index 25b669617..8266dad97 100644
--- a/ArmPlatformPkg/Sec/SecEntryPoint.S
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.S
@@ -20,7 +20,7 @@
 

 GCC_ASM_IMPORT(CEntryPoint)

 GCC_ASM_IMPORT(ArmPlatformSecBootAction)

-GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)

+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)

 GCC_ASM_IMPORT(ArmDisableInterrupts)

 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)

 GCC_ASM_IMPORT(ArmWriteVBar)

@@ -66,7 +66,7 @@ _WaitInitMem:
   

 _InitMem:

   // Initialize Init Boot Memory

-  bl    ASM_PFX(ArmPlatformInitializeBootMemory)

+  bl    ASM_PFX(ArmPlatformSecBootMemoryInit)

   

   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)

   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)

diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.asm b/ArmPlatformPkg/Sec/SecEntryPoint.asm
index 3556ce471..a20a3fd9f 100644
--- a/ArmPlatformPkg/Sec/SecEntryPoint.asm
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.asm
@@ -19,7 +19,7 @@
   

   IMPORT  CEntryPoint

   IMPORT  ArmPlatformSecBootAction

-  IMPORT  ArmPlatformInitializeBootMemory

+  IMPORT  ArmPlatformSecBootMemoryInit

   IMPORT  ArmDisableInterrupts

   IMPORT  ArmDisableCachesAndMmu

   IMPORT  ArmWriteVBar

@@ -68,7 +68,7 @@ _WaitInitMem
   

 _InitMem

   // Initialize Init Boot Memory

-  bl    ArmPlatformInitializeBootMemory

+  bl    ArmPlatformSecBootMemoryInit

   

   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)

   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)

diff --git a/ArmPlatformPkg/Sec/SecInternal.h b/ArmPlatformPkg/Sec/SecInternal.h
index 9136db9b4..0d6daf993 100644
--- a/ArmPlatformPkg/Sec/SecInternal.h
+++ b/ArmPlatformPkg/Sec/SecInternal.h
@@ -19,7 +19,7 @@
 #include <Base.h>

 #include <Library/ArmLib.h>

 #include <Library/ArmCpuLib.h>

-#include <Library/ArmPlatformLib.h>

+#include <Library/ArmPlatformSecLib.h>

 #include <Library/BaseLib.h>

 #include <Library/DebugLib.h>

 #include <Library/PcdLib.h>

@@ -50,11 +50,6 @@ SecVectorTable (
   );

 

 VOID

-NonSecureWaitForFirmware (

-  VOID

-  );

-

-VOID

 enter_monitor_mode (

   IN UINTN                  MonitorEntryPoint,

   IN UINTN                  MpId,