TC1: Add Versatile Express CTA15x2 BSP

Add the BSP for the Versatile Express CTA15x2 TC1 Core Tile

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

7 files changed, 1044 insertions, 0 deletions

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf
new file mode 100644
index 000000000..47bedf638
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf
@@ -0,0 +1,49 @@
+#/* @file
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CTA15x2ArmVExpressLib
+  FILE_GUID                      = b16c63a0-f417-11df-b3af-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  MemoryAllocationLib
+  PL341DmcLib
+  PL301AxiLib
+  L2X0CacheLib
+  SerialPortLib
+
+[Sources.common]
+  CTA15x2.c
+  CTA15x2Mem.c
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf
new file mode 100644
index 000000000..b5d75fdf5
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf
@@ -0,0 +1,50 @@
+#/* @file
+#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  
+#  This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CTA15x2ArmVExpressLib
+  FILE_GUID                      = b16c63a0-f417-11df-b3af-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmPlatformSysConfigLib
+  IoLib
+  L2X0CacheLib
+  PL301AxiLib
+  PL341DmcLib
+  PL35xSmcLib
+  SerialPortLib
+
+[Sources.common]
+  CTA15x2Sec.c
+  CTA15x2.c
+  CTA15x2Boot.asm     | RVCT
+  CTA15x2Boot.S       | GCC
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFvBaseAddress
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c
new file mode 100644
index 000000000..0427bef5b
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c
@@ -0,0 +1,143 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Drivers/PL341Dmc.h>
+#include <Drivers/PL301Axi.h>
+#include <Drivers/SP804Timer.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+#define SerialPrint(txt)  SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
+
+ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA15x2[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {
+    return BOOT_WITH_FULL_CONFIGURATION;
+  } else {
+    return BOOT_ON_S2_RESUME;
+  }
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+VOID
+ArmPlatformNormalInitialize (
+  VOID
+  )
+{
+  // Configure periodic timer (TIMER0) for 1MHz operation
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+  // Configure 1MHz clock
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+  // configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+  // Configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+  // Memory is initialised in CTA15x2Boot.S
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  *CoreCount    = sizeof(mVersatileExpressMpCoreInfoCTA15x2) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mVersatileExpressMpCoreInfoCTA15x2;
+
+  return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &mArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S
new file mode 100644
index 000000000..c4b00c323
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S
@@ -0,0 +1,455 @@
+//
+//  Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL35xSmc.h>
+#include <Drivers/PL341Dmc.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
+
+/**
+  Call at the beginning of the platform boot up
+
+  This function allows the firmware platform to do extra actions at the early
+  stage of the platform power up.
+
+  Note: This function must be implemented in assembler as there is no stack set up yet
+
+**/
+ASM_PFX(ArmPlatformSecBootAction):
+  bx    lr
+
+/**
+  Initialize the memory where the initial stacks will reside
+
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+  In some platform, this region is already initialized and the implementation of this function can
+  do nothing. This memory can also represent the Secure RAM.
+  This function is called before the satck has been set up. Its implementation must ensure the stack
+  pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformInitializeBootMemory):
+  mov  r8, lr
+  bl   smc_init
+  bl   dmc_init
+  bx   r8
+
+
+/**
+  Initialise the Static Memory Controller
+**/
+smc_init:
+
+	LDR     r0, = ARM_VE_SMC_CTRL_BASE
+	LDR     r2, = ARM_VE_SMB_PERIPH_BASE
+
+	// CS0 - NOR0
+	LDR     r1, = 0x0002393A
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000AAA
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x00400000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS1 - PSRAM
+	LDR     r1, = 0x00027158
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000802
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x00C00000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS2 - usb, ethernet and vram
+	LDR     r1, = 0x000CD2AA
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000046
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x01400000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS3 - IOFPGA peripherals
+	LDR     r1, = 0x00025156
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000046
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x01C00000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS4 - NOR1
+	LDR     r1, = 0x0002393A
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000AAA
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x02400000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS5 - unused
+	LDR     r1, = 0x0002393A
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000AAA
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x02C00000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS6 - unused
+	LDR     r1, = 0x0002393A
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000AAA
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x03400000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// CS7 - unused
+	LDR     r1, = 0x0002393A
+	STR     r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+	LDR     r1, = 0x00000AAA
+	STR     r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+	LDR     r1, = 0x03C00000
+	STR     r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+	// page mode setup for VRAM
+	LDR     r0, = 0x00FFFFFC
+	ADD     r0, r0, r2
+
+	// read current state
+	LDR     r1, [r0, #0]
+	LDR     r1, [r0, #0]
+	LDR     r1, = 0x00000000
+	STR     r1, [r0, #0]
+	LDR     r1, [r0, #0]
+
+	// enable page mode
+	LDR     r1, [r0, #0]
+	LDR     r1, [r0, #0]
+	LDR     r1, = 0x00000000
+	STR     r1, [r0, #0]
+	LDR     r1, = 0x00900090
+	STR     r1, [r0, #0]
+
+	// confirm page mode enabled
+	LDR     r1, [r0, #0]
+	LDR     r1, [r0, #0]
+	LDR     r1, = 0x00000000
+	STR     r1, [r0, #0]
+	LDR     r1, [r0, #0]
+
+	BX      lr
+	// end of smc_init
+
+
+/**
+  Initialise the PL341 Dynamic Memory Controller (DMC)
+
+  On A15, the PHY needs to be locked before configuring the DMC.
+  After DMC config, the PHY needs to be trained
+**/
+#define SCC_PHY_RESET_REG_OFFSET                     0x04
+
+dmc_init:
+
+	LDR     r0, = ARM_VE_DMC_BASE
+	LDR     r1, = 0x00000400 // SCC reset bit for DDR PHY
+	LDR     r2, = 0x7FEF0000 // PHY addr
+
+	LDR     r3, =0x3
+	STR     r3, [r2, #PHY_PTM_DFI_CLK_RANGE]
+	LDR     r3, =0x0
+	STR     r3, [r2, #PHY_PTM_PLL_RANGE]
+	LDR     r3, =0x0
+	STR     r3, [r2, #PHY_PTM_FEEBACK_DIV]
+	LDR     r3, =0x0
+	STR     r3, [r2, #PHY_PTM_RCLK_DIV]
+	LDR     r3, =0x1
+	STR     r3, [r2, #PHY_PTM_PLL_EN]
+
+	// Wait for PHY to lock
+waitloop_01:
+	LDR     r3, [r2, #PHY_PTM_LOCK_STATUS]
+	AND     r3, #0xff
+	CMP     r3, #0x1
+	BNE     waitloop_01
+
+	LDR     r3, =0x5
+	STR     r3, [r2, #PHY_PTM_IOTERM]
+	LDR     r0, =ARM_VE_SCC_BASE
+	LDR     r3, [r0, #SCC_PHY_RESET_REG_OFFSET]
+	ORR     r3, r3, r1
+	STR     r3, [r0, #SCC_PHY_RESET_REG_OFFSET]
+
+	// wait for PHY ready
+waitloop_03:
+	LDR     r3, [r2, #PHY_PTM_INIT_DONE]
+	AND     r3, #0x1
+	TST     r3, #0x1
+	BEQ     waitloop_03
+
+	// Init PL341
+	LDR     r0, = ARM_VE_DMC_BASE
+
+	LDR     r1, =0x4 // enter config mode
+	STR     r1, [r0, #DMC_COMMAND_REG]
+	LDR     r1, =0xc30
+	STR     r1, [r0, #DMC_REFRESH_PRD_REG]
+	LDR     r1, =0xc
+	STR     r1, [r0, #DMC_CAS_LATENCY_REG]
+	LDR     r1, =0x5
+	STR     r1, [r0, #DMC_WRITE_LATENCY_REG]
+	LDR     r1, =0x2
+	STR     r1, [r0, #DMC_T_MRD_REG]
+	LDR     r1, =0x12
+	STR     r1, [r0, #DMC_T_RAS_REG]
+	LDR     r1, =0x18
+	STR     r1, [r0, #DMC_T_RC_REG]
+	LDR     r1, =0x0306
+	STR     r1, [r0,#DMC_T_RCD_REG]
+	LDR     r1, =0x00004c4f
+	STR     r1, [r0, #DMC_T_RFC_REG]
+	LDR     r1, =0x00000306
+	STR     r1, [r0, #DMC_T_RP_REG]
+	LDR     r1, =0x4
+	STR     r1, [r0, #DMC_T_RRD_REG]
+	LDR     r1, =0x6
+	STR     r1, [r0, #DMC_T_WR_REG]
+	LDR     r1, =0x3
+	STR     r1, [r0, #DMC_T_WTR_REG]
+	LDR     r1, =0x2
+	STR     r1, [r0, #DMC_T_XP_REG]
+	LDR     r1, =0x52
+	STR     r1, [r0, #DMC_T_XSR_REG]
+	LDR     r1, =0xc8
+	STR     r1, [r0, #DMC_T_ESR_REG]
+	LDR     r1, =0x0b0e
+	STR     r1, [r0, #DMC_T_FAW_REG]
+	LDR     r1, =0x3
+	STR     r1, [r0, #DMC_T_RDATA_EN]
+	LDR     r1, =0x1
+	STR     r1, [r0, #DMC_T_WRLAT_DIFF]
+	LDR     r1, =0x00210022
+	STR     r1, [r0, #DMC_MEMORY_CONFIG_REG]
+	LDR     r1, =0x0000007C
+	STR     r1, [r0, #DMC_MEMORY_CFG2_REG]
+	LDR     r1, =0x00000001
+	STR     r1, [r0, #DMC_MEMORY_CFG3_REG]
+	LDR     r1, =0x000000c0
+	STR     r1, [r0, #DMC_CHIP_0_CFG_REG]
+	LDR     r1, =0x00040c0
+	STR     r1, [r0, #DMC_CHIP_1_CFG_REG]
+
+	// Configure DDR2 Devices on Chip Select 0
+	// nop
+	LDR     r1, =0x000C0000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// pre-charge all
+	LDR     r1, =0x0
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_04:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_04
+
+	// extended mode register 2 (EMR2)
+	LDR     r1, =0x000A0000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// extended mode register 3 (EMR3)
+	LDR     r1, =0x000B0000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// extended mode register (EMR), OCD default state
+	LDR     r1, =0x00090000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// set mode register (MR) with DLL reset
+	LDR     r1,=0x00080B62
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// pre-charge all
+	LDR     r1, =0x0
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// auto-refresh
+	LDR     r1, =0x00040000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// auto-refresh
+	LDR     r1, =0x00040000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// set mode register (MR) without DLL reset
+	LDR     r1,=0x00080A62
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_05:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_05
+
+	// extended mode register (EMR) enable OCD defaults
+	LDR     r1, =0x00094384
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_06:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_06
+
+	// extended mode register (EMR) OCD Exit
+	LDR     r1, =0x00094004
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_07:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_07
+
+	// Configure DDR2 Devices on Chip Select 1
+	// send nop
+	// nop
+	LDR     r1, =0x001C0000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// pre-charge all
+	LDR     r1, =0x00100000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_08:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_08
+
+	// set extended mode register 2
+	LDR     r1, =0x001A0000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// set extended mode register 3
+	LDR     r1, =0x001B0000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	//  extended mode register (EMR) OCD default state
+	LDR     r1, =0x00190000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// mode register (MR) with DLL reset
+	LDR     r1,=0x00180B62
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// pre-charge all
+	LDR     r1, =0x00100000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// auto-refresh
+	LDR     r1, =0x00140000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// auto-refresh
+	LDR     r1, =0x00140000
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+
+	// mode register (MR) without DLL reset
+	LDR     r1,=0x00180A62
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_09:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_09
+
+	// extended mode register (EMR) enable OCD defaults
+	LDR     r1, =0x00194384
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_10:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_10
+
+	// extended mode register (EMR) OCD Exit
+	LDR     r1, =0x00194004
+	STR     r1, [r0, #DMC_DIRECT_CMD_REG]
+
+	// wait loop
+	LDR     r1, =0x0
+waitloop_11:
+	LDR     r3, [r0, #DMC_STATUS_REG]
+	ADD     r1, r1, #1
+	CMP     r1, #10
+	BLT     waitloop_11
+
+	// go command
+	LDR     r1, =DMC_COMMAND_GO
+	STR     r1, [r0, #DMC_COMMAND_REG]
+
+	// wait for ready
+waitloop_12:
+	LDR     r1, [r0,#DMC_STATUS_REG]
+	AND     r1, #0x3                // Mask of all but memc_status bits
+	TST     r1,#1
+	BEQ     waitloop_12
+
+	// PHY Squelch Training
+	LDR     r3, =0x1
+	STR     r3, [r2, #PHY_PTM_SQU_TRAINING]
+
+	LDR     r5, =0x80000000
+waitloop_13:
+	LDR     r4, =0
+waitloop_14:
+	LDR     r3, [r5, #0]
+	ADD     r4, #1
+	CMP     r4, #200
+	BNE     waitloop_14
+
+	// wait for ready
+	LDR     r3, [r2,#PHY_PTM_SQU_STAT]
+	TST     r3,#1
+	BEQ     waitloop_13
+
+	LDR     r3, =0
+	STR     r3, [r2, #PHY_PTM_SQU_TRAINING]
+
+	bx      lr
+	// end of dmc_init
+
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm
new file mode 100644
index 000000000..d0b792c35
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm
@@ -0,0 +1,127 @@
+//
+//  Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL35xSmc.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+  INCLUDE AsmMacroIoLib.inc
+
+  EXPORT  ArmPlatformSecBootAction
+  EXPORT  ArmPlatformInitializeBootMemory
+  IMPORT  PL35xSmcInitialize
+
+  PRESERVE8
+  AREA    CTA15x2BootMode, CODE, READONLY
+
+//
+// For each Chip Select: ChipSelect / SetCycle / SetOpMode
+//
+VersatileExpressSmcConfiguration
+    // NOR Flash 0
+    DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(0)
+    DCD     PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+    DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+    // NOR Flash 1
+    DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(4)
+    DCD     PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+    DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+    // SRAM
+    DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(2)
+    DCD     PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+    DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+    // Usb/Eth/VRAM
+    DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(3)
+    DCD     PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
+    DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+    // Memory Mapped Peripherals
+    DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(7)
+    DCD     PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+    DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+    // VRAM
+    DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(1)
+    DCD     0x00049249
+    DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+VersatileExpressSmcConfigurationEnd
+
+/**
+  Call at the beginning of the platform boot up
+
+  This function allows the firmware platform to do extra actions at the early
+  stage of the platform power up.
+
+  Note: This function must be implemented in assembler as there is no stack set up yet
+
+**/
+ArmPlatformSecBootAction
+  bx  lr
+
+/**
+  Initialize the memory where the initial stacks will reside
+
+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+  In some platform, this region is already initialized and the implementation of this function can
+  do nothing. This memory can also represent the Secure RAM.
+  This function is called before the satck has been set up. Its implementation must ensure the stack
+  pointer is not used (probably required to use assembly language)
+
+**/
+ArmPlatformInitializeBootMemory
+  mov   r5, lr
+
+  //
+  // Initialize PL354 SMC
+  //
+  LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
+  ldr   r2, =VersatileExpressSmcConfiguration
+  ldr   r3, =VersatileExpressSmcConfigurationEnd
+  blx   PL35xSmcInitialize
+
+  //
+  // Page mode setup for VRAM
+  //
+  LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
+
+  // Read current state
+  ldr     r0, [r2, #0]
+  ldr     r0, [r2, #0]
+  ldr     r0, = 0x00000000
+  str     r0, [r2, #0]
+  ldr     r0, [r2, #0]
+
+  // Enable page mode
+  ldr     r0, [r2, #0]
+  ldr     r0, [r2, #0]
+  ldr     r0, = 0x00000000
+  str     r0, [r2, #0]
+  ldr     r0, = 0x00900090
+  str     r0, [r2, #0]
+
+  // Confirm page mode enabled
+  ldr     r0, [r2, #0]
+  ldr     r0, [r2, #0]
+  ldr     r0, = 0x00000000
+  str     r0, [r2, #0]
+  ldr     r0, [r2, #0]
+
+ryan doesn't want this to happen
+
+  bx    r5
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c
new file mode 100644
index 000000000..4cda6c8e9
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c
@@ -0,0 +1,146 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <ArmPlatform.h>
+
+// Number of Virtual Memory Map Descriptors without a Logic Tile
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+
+  ASSERT(VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+      return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+      CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  // ReMap (Either NOR Flash or DRAM)
+  VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;
+
+  if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
+    // Map the NOR Flash as Secure Memory
+    if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_CACHED;
+    } else {
+      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_UNCACHED;
+    }
+  } else {
+    // DRAM mapping
+    VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+  }
+
+  // DDR
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // SMC CS7
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_ON_CHIP_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_ON_CHIP_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
+
+  // SMB CS0-CS1 - NOR Flash 1 & 2
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
+
+  // SMB CS2 - SRAM
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // SMB CS3-CS6 - Motherboard Peripherals
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length       = 2 * ARM_VE_SMB_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
+
+  // If a Logic Tile is connected to The ARM Versatile Express Motherboard
+  if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {
+      VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;
+      VirtualMemoryTable[Index].VirtualBase  = ARM_VE_EXT_AXI_BASE;
+      VirtualMemoryTable[Index].Length       = ARM_VE_EXT_AXI_SZ;
+      VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
+
+      ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
+  } else {
+    ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+  }
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase = 0;
+  VirtualMemoryTable[Index].VirtualBase  = 0;
+  VirtualMemoryTable[Index].Length       = 0;
+  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
+
+/**
+  Return the EFI Memory Map provided by extension memory on your platform
+
+  This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
+  Descriptor HOBs used by DXE core.
+
+  @param[out]   EfiMemoryMap        Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
+                                    EFI Memory region. This array must be ended by a zero-filled entry
+
+**/
+EFI_STATUS
+ArmPlatformGetAdditionalSystemMemory (
+  OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
+  )
+{
+  return EFI_UNSUPPORTED;
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c
new file mode 100644
index 000000000..d9d3ff731
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c
@@ -0,0 +1,74 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL310L2Cache.h>
+#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
+
+/**
+  Initialize the Secure peripherals and memory regions
+
+  If Trustzone is supported by your platform then this function makes the required initialization
+  of the secure peripherals and memory regions.
+
+**/
+VOID
+ArmPlatformTrustzoneInit (
+  VOID
+  )
+{
+  // No TZPC or TZASC on RTSM to initialize
+}
+
+/**
+  Initialize controllers that must setup at the early stage
+
+  Some peripherals must be initialized in Secure World.
+  For example, some L2x0 requires to be initialized in Secure World
+
+**/
+VOID
+ArmPlatformSecInitialize (
+  VOID
+  )
+{
+  // Configure periodic timer (TIMER0) for 1MHz operation
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+  // Configure 1MHz clock
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+  // Configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+  // Configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+}
+
+/**
+  Call before jumping to Normal World
+
+  This function allows the firmware platform to do extra actions before
+  jumping to the Normal World
+
+**/
+VOID
+ArmPlatformSecExtraAction (
+  IN  UINTN         MpId,
+  OUT UINTN*        JumpAddress
+  )
+{
+  *JumpAddress = PcdGet32(PcdFvBaseAddress);
+}