diff options
author | Ryan Harkin <ryan.harkin@linaro.org> | 2012-09-11 09:34:54 +0100 |
---|---|---|
committer | Ryan Harkin <ryan.harkin@linaro.org> | 2013-09-18 17:38:12 +0100 |
commit | 572d4a86fc875b66ae662294405be1f852490835 (patch) | |
tree | d5e05cf70c963e0385762e352a76f7beb7e9caad /ArmPkg | |
parent | c185513c8476cfa7d942f6114747256a0f14cc95 (diff) |
VEA5: create dedicated A5 CPU library
The A5 was using the A9 CPU library which has some TrustZone related code.
So I decided to create a dedicated library for A5, which is how the other
CPU types operate.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'ArmPkg')
-rw-r--r-- | ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c | 47 | ||||
-rw-r--r-- | ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf | 38 | ||||
-rw-r--r-- | ArmPkg/Include/Chipset/ArmCortexA5.h | 59 |
3 files changed, 144 insertions, 0 deletions
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c new file mode 100644 index 000000000..716a3d0a4 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c @@ -0,0 +1,47 @@ +/** @file + + Copyright (c) 2011-2012, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/ArmLib.h> +#include <Library/ArmCpuLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> + +#include <Chipset/ArmCortexA5.h> + +VOID +ArmCpuSetup ( + IN UINTN MpId + ) +{ + // Enable SWP instructions + ArmEnableSWPInstruction (); + + // Enable program flow prediction, if supported. + ArmEnableBranchPrediction (); + + // If MPCore then Enable the SCU + if (ArmIsMpCore()) { + // Signals the Cortex-A5 processor is taking part in coherency + ArmSetAuxCrBit (A5_FEATURE_SMP); + } +} + + +VOID +ArmCpuSetupSmpNonSecure ( + IN UINTN MpId + ) +{ +} diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf new file mode 100644 index 000000000..36ae596b2 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf @@ -0,0 +1,38 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmCortexA5Lib + FILE_GUID = c9709ea3-1beb-4806-889a-8a1d5e5e1697 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmCpuLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + ArmLib + IoLib + PcdLib + +[Sources.common] + ArmCortexA5Lib.c + +[FeaturePcd] + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPkg/Include/Chipset/ArmCortexA5.h b/ArmPkg/Include/Chipset/ArmCortexA5.h new file mode 100644 index 000000000..c9122709f --- /dev/null +++ b/ArmPkg/Include/Chipset/ArmCortexA5.h @@ -0,0 +1,59 @@ +/** @file + + Copyright (c) 2011, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_CORTEX_A5_H__ +#define __ARM_CORTEX_A5_H__ + +#include <Chipset/ArmV7.h> + +// +// Cortex A5 feature bit definitions +// +#define A5_FEATURE_PARITY (1<<9) +#define A5_FEATURE_AOW (1<<8) +#define A5_FEATURE_EXCL (1<<7) +#define A5_FEATURE_SMP (1<<6) +#define A5_FEATURE_FOZ (1<<3) +#define A5_FEATURE_DPREF (1<<2) +#define A5_FEATURE_HINT (1<<1) +#define A5_FEATURE_FWD (1<<0) + +// +// Cortex A5 Watchdog +// +#define ARM_A5_WATCHDOG_REGION 0x600 + +#define ARM_A5_WATCHDOG_LOAD_REGISTER 0x20 +#define ARM_A5_WATCHDOG_CONTROL_REGISTER 0x28 + +#define ARM_A5_WATCHDOG_WATCHDOG_MODE (1 << 3) +#define ARM_A5_WATCHDOG_TIMER_MODE (0 << 3) +#define ARM_A5_WATCHDOG_SINGLE_SHOT (0 << 1) +#define ARM_A5_WATCHDOG_AUTORELOAD (1 << 1) +#define ARM_A5_WATCHDOG_ENABLE 1 + +// +// SCU register offsets & masks +// +#define A5_SCU_CONTROL_OFFSET 0x0 +#define A5_SCU_CONFIG_OFFSET 0x4 +#define A5_SCU_INVALL_OFFSET 0xC +#define A5_SCU_FILT_START_OFFSET 0x40 +#define AA5SCU_FILT_END_OFFSET 0x44 +#define A5_SCU_SACR_OFFSET 0x50 +#define A5_SCU_SSACR_OFFSET 0x54 + + +#endif + |